Commits · master · haiyang3 / Verilog Ethernet

Apr 29, 2022
- 4.29 · 1245c82e
  Haiyang Zhang authored 3 years ago
  
  1245c82e
Apr 28, 2022
- move to none Vivado ip · 16519588
  haiyang3 authored 3 years ago
  
  16519588
Apr 27, 2022
- move axi size conv to fpga_core · 567e1d58
  Haiyang Zhang authored 3 years ago
  
  567e1d58
- modified top level interface to 256bit axis · d62d25fe
  Haiyang Zhang authored 3 years ago
  
  d62d25fe
Apr 26, 2022
- change toplevel · 35eda8e2
  haiyang3 authored 3 years ago
  
  35eda8e2
- removed wavedump · eb0ca3f6
  haiyang3 authored 3 years ago
  
  eb0ca3f6
- eth to axis streamer plus tb for ADM_PCIE_9V3 · 962c9c52
  haiyang3 authored 3 years ago
  
  962c9c52
Mar 30, 2022
- merged changes in axis · 84004c72
  Alex Forencich authored 3 years ago
  
  84004c72
- Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 · 073d50d9
  Alex Forencich authored 3 years ago
  
  073d50d9
Mar 28, 2022
- Add output pipeline to PTP clock CDC module · 6f2d581d
  Alex Forencich authored 3 years ago
  
  6f2d581d
- Add output pipeline to PTP clock module · 945f22fd
  Alex Forencich authored 3 years ago
  
  945f22fd
Mar 16, 2022
- Simplify logic in PTP clock CDC module · 108c02d7
  Alex Forencich authored 3 years ago
  
  108c02d7
- Simplify logic in PTP clock module · 0f2db26a
  Alex Forencich authored 3 years ago
  
  0f2db26a
- Remove deprecated assignments · 23fb9d0b
  Alex Forencich authored 3 years ago
  
  23fb9d0b
Jan 01, 2022
- Fix backpressure bug · 7d8b5560
  Alex Forencich authored 3 years ago
  
  7d8b5560
- Simplify logic · 853c1737
  Alex Forencich authored 3 years ago
  
  853c1737
Dec 27, 2021
- Lock package versions · 96716b05
  Alex Forencich authored 3 years ago
  
  96716b05
- Lock package versions · 98a324a0
  Alex Forencich authored 3 years ago
  
  98a324a0
- Specify min tox and venv versions · fef6b167
  Alex Forencich authored 3 years ago
  
  fef6b167
- Specify min tox and venv versions · 7f965700
  Alex Forencich authored 3 years ago
  
  7f965700
- Use available python 3 · 5cf2bcec
  Alex Forencich authored 3 years ago
  
  5cf2bcec
- Use available python 3 · 61fbb2d7
  Alex Forencich authored 3 years ago
  
  61fbb2d7
Dec 10, 2021
- Use start_soon instead of fork · 1f80696b
  Alex Forencich authored 3 years ago
  
  1f80696b
- merged changes in axis · 49f5507d
  Alex Forencich authored 3 years ago
  
  49f5507d
- Use start_soon instead of fork · 4df34f13
  Alex Forencich authored 3 years ago
  
  4df34f13
Nov 29, 2021
- Update axis_switch instances · 8e60adf5
  Alex Forencich authored 3 years ago
  
  8e60adf5
- merged changes in axis · 10a6eddf
  Alex Forencich authored 3 years ago
  
  10a6eddf
- Testbench parameter cleanup · 2a89fb93
  Alex Forencich authored 3 years ago
  
  2a89fb93
- Handle some zero-valued signal width settings · e4b47624
  Alex Forencich authored 3 years ago
  
  e4b47624
- Add support to demux for routing by tdest · 907081d2
  Alex Forencich authored 3 years ago
  
  907081d2
Nov 28, 2021
- Add UPDATE_TID parameter to set MSBs of tid based on source port · ccbca0c5
  Alex Forencich authored 3 years ago
  
  ccbca0c5
Nov 25, 2021
- Decouple tid/tdest signal widths for routing components · 24863398
  Alex Forencich authored 3 years ago
  
  24863398
Nov 24, 2021
- Handle out-of-range select as drop · 150d5ad0
  Alex Forencich authored 3 years ago
  
  150d5ad0
Nov 15, 2021
- Remove deprecated assigments · f40e6835
  Alex Forencich authored 3 years ago
  
  f40e6835
Nov 07, 2021
- Remove some lint · 8bd6c8ea
  Alex Forencich authored 3 years ago
  
  8bd6c8ea
- Use constants from cocotbext-eth · 32d99b4d
  Alex Forencich authored 3 years ago
  
  32d99b4d
Nov 03, 2021
- Update readme · 4cda6b07
  Alex Forencich authored 3 years ago
  
  4cda6b07
- Add 520N-MX 10G example design · d0522646
  Alex Forencich authored 3 years ago
  
  d0522646
- Reorganize PHY instances · 9e44987f
  Alex Forencich authored 3 years ago
  
  9e44987f
- Update QSF/SDC files · 728e86c5
  Alex Forencich authored 3 years ago
  
  728e86c5