Skip to content

GitLab

Explore

Sign in

Primary navigation

Project

V

Verilog Ethernet
- Activity
- Members
- Labels
- Issues
- Issue boards
- Milestones
- Wiki
- Environments
- Terraform modules
- Incidents

Snippets Groups Projects

962c9c52

Commit 962c9c52 authored 3 years ago by haiyang3

Downloads
- Patches
- Plain Diff

eth to axis streamer plus tb for ADM_PCIE_9V3

parent 84004c72

No related branches found

No related tags found

No related merge requests found

Changes 10

Hide whitespace changes

Inline Side-by-side

Showing

example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/results.xml 6 additions, 0 deletions

example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/results.xml
example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/sim_build/cmds.f 1 addition, 0 deletions

example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/sim_build/cmds.f
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v 22 additions, 1 deletion

example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v 91 additions, 16 deletions

example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile 1 addition, 1 deletion

example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/dump.vcd 0 additions, 0 deletions

example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/dump.vcd
example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/iverilog_dump.v 6 additions, 0 deletions

example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/iverilog_dump.v
example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/results.xml 6 additions, 0 deletions

example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/results.xml
example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/sim_build/cmds.f 1 addition, 0 deletions

example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/sim_build/cmds.f
example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py 64 additions, 2 deletions

example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py

with 198 additions and 20 deletions

Loading

0% Loading or .

You are about to add 0 people to the discussion. Proceed with caution.

Finish editing this message first!

Please register or sign in to comment