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haiyang3
Verilog Ethernet
Commits
e4b47624
Commit
e4b47624
authored
3 years ago
by
Alex Forencich
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Handle some zero-valued signal width settings
parent
907081d2
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4 changed files
rtl/axis_arb_mux.v
+3
-1
3 additions, 1 deletion
rtl/axis_arb_mux.v
rtl/axis_demux.v
+5
-3
5 additions, 3 deletions
rtl/axis_demux.v
rtl/axis_ram_switch.v
+14
-11
14 additions, 11 deletions
rtl/axis_ram_switch.v
rtl/axis_switch.v
+11
-8
11 additions, 8 deletions
rtl/axis_switch.v
with
33 additions
and
23 deletions
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