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Commit 8bd6c8ea authored by Alex Forencich's avatar Alex Forencich
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Remove some lint

parent 32d99b4d
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......@@ -246,7 +246,7 @@ class BaseRSerdesSource():
if cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
# ordered set in lane 0
data = BaseRBlockType.OS_START
for i in range(1,4):
for i in range(1, 4):
data |= dl[i] << i*8
if dl[0] == XgmiiCtrl.SIG_OS:
# signal ordered set
......@@ -262,7 +262,7 @@ class BaseRSerdesSource():
if cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
# ordered set in lane 4
data = BaseRBlockType.OS_04
for i in range(5,8):
for i in range(5, 8):
data |= dl[i] << i*8
if dl[4] == XgmiiCtrl.SIG_OS:
# signal ordered set
......
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