Add attributes to RAMs for proper synthesis in Quartus

rtl/axis_async_fifo.v

@@ -207,6 +207,7 @@ reg m_rst_sync2_reg = 1'b1;
 (* SHREG_EXTRACT = "NO" *)
 reg m_rst_sync3_reg = 1'b1;
 
+(* ramstyle = "no_rw_check" *)
 reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
 reg [WIDTH-1:0] mem_read_data_reg;
 reg mem_read_data_valid_reg = 1'b0;

rtl/axis_fifo.v

@@ -161,6 +161,7 @@ reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
 
+(* ramstyle = "no_rw_check" *)
 reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
 reg [WIDTH-1:0] mem_read_data_reg;
 reg mem_read_data_valid_reg = 1'b0;

rtl/axis_pipeline_fifo.v

@@ -182,17 +182,17 @@ if (LENGTH > 0) begin
     wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {FIFO_ADDR_WIDTH{1'b0}}});
     wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
 
-    (* ram_style = "distributed" *)
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
     reg [DATA_WIDTH-1:0] out_fifo_tdata[2**FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed" *)
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
     reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed" *)
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
     reg                  out_fifo_tlast[2**FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed" *)
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
     reg [ID_WIDTH-1:0]   out_fifo_tid[2**FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed" *)
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
     reg [DEST_WIDTH-1:0] out_fifo_tdest[2**FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed" *)
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
     reg [USER_WIDTH-1:0] out_fifo_tuser[2**FIFO_ADDR_WIDTH-1:0];
 
     assign m_axis_tready_int = !out_fifo_half_full_reg;