diff --git a/tb/baser.py b/tb/baser.py
index e6a773584f366831c07fb05c0fc94504980f07d8..0570ff7e97eec0ad3c4ad752e1b0b8ab6e829765 100644
--- a/tb/baser.py
+++ b/tb/baser.py
@@ -246,7 +246,7 @@ class BaseRSerdesSource():
                             if cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
                                 # ordered set in lane 0
                                 data = BaseRBlockType.OS_START
-                                for i in range(1,4):
+                                for i in range(1, 4):
                                     data |= dl[i] << i*8
                                 if dl[0] == XgmiiCtrl.SIG_OS:
                                     # signal ordered set
@@ -262,7 +262,7 @@ class BaseRSerdesSource():
                             if cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
                                 # ordered set in lane 4
                                 data = BaseRBlockType.OS_04
-                                for i in range(5,8):
+                                for i in range(5, 8):
                                     data |= dl[i] << i*8
                                 if dl[4] == XgmiiCtrl.SIG_OS:
                                     # signal ordered set