Skip to content

GitLab

Explore

Sign in

Primary navigation

Project

V

Verilog Ethernet
- Activity
- Members
- Labels
- Issues
- Issue boards
- Milestones
- Wiki
- Environments
- Terraform modules
- Incidents

Snippets Groups Projects

0aee8724

Commit 0aee8724 authored 3 years ago by Alex Forencich

Downloads
- Plain Diff

merged changes in axis

parents 6b18e56c 96a26e7a

No related branches found

No related tags found

No related merge requests found

Changes 3

Hide whitespace changes

Inline Side-by-side

Showing

lib/axis/rtl/axis_async_fifo.v 1 addition, 0 deletions

lib/axis/rtl/axis_async_fifo.v
lib/axis/rtl/axis_fifo.v 1 addition, 0 deletions

lib/axis/rtl/axis_fifo.v
lib/axis/rtl/axis_pipeline_fifo.v 6 additions, 6 deletions

lib/axis/rtl/axis_pipeline_fifo.v

with 8 additions and 6 deletions

Loading

0% Loading or .

You are about to add 0 people to the discussion. Proceed with caution.

Finish editing this message first!

Please register or sign in to comment