osu_fpga_toplevel.sv

/**
*	osu!fpga
*
*	An osu!-like rhythm game on DE2-115
*
*	See README for more information
*
*	Copyright (c) 2017 by Fang Lu and Xutao J. Jiang. See LICENSE file
*
*/
module osu_fpga_toplevel (
	input logic CLOCK_50,
	input logic [1:0] KEY,
	output logic [7:0] LEDG,
	output logic [17:0] LEDR,
	output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
	output logic [12:0] DRAM_ADDR,
	output logic [1:0] DRAM_BA,
	output logic DRAM_CAS_N, DRAM_CKE, DRAM_CS_N,
	inout wire [31:0] DRAM_DQ,
	output logic [3:0] DRAM_DQM,
	output logic DRAM_RAS_N, DRAM_WE_N, DRAM_CLK,
	inout wire PS2_KBCLK, PS2_KBDAT
);
	otogame main_soc (
		.clk_clk(CLOCK_50),
		.reset_reset_n(KEY[0]),
		.sdram_wire_addr(DRAM_ADDR),
		.sdram_wire_ba(DRAM_BA),
		.sdram_wire_cas_n(DRAM_CAS_N),
		.sdram_wire_cke(DRAM_CKE),
		.sdram_wire_cs_n(DRAM_CS_N),
		.sdram_wire_dq(DRAM_DQ),
		.sdram_wire_dqm(DRAM_DQM),
		.sdram_wire_ras_n(DRAM_RAS_N),
		.sdram_wire_we_n(DRAM_WE_N),
		.sdram_clk_clk(DRAM_CLK),
		.ps2_data_export(PS2_KBDAT),
		.ps2_clk_export(PS2_KBCLK)
	);

	// logic[7:0] kdr1, kdr2, kur1, kur2, kc;
	// logic[2:0] st;

	// ps2kb kb(.CLK(CLOCK_50), .RESET(~KEY[0]), .AVL_READ(0), .AVL_WRITE(0), .AVL_CS(0),
	//    .AVL_BYTE_EN(0), .AVL_ADDR(0), .AVL_WRITEDATA(0), .AVL_READDATA(0),
	//    .PS2_CLK(PS2_KBCLK), .PS2_DATA(PS2_KBDAT), .debug_state(LEDG[2:0]), .debug_kc(LEDR[7:0]),
	//    .debug_kdr1(kdr1), .debug_kdr2(kdr2), .debug_kur1(kur1), .debug_kur2(kur2));

	// hexdriver kd1l(.In(kdr1[3:0]), .Out(HEX0));
	// hexdriver kd1h(.In(kdr1[7:4]), .Out(HEX1));
	// hexdriver kd2l(.In(kdr2[3:0]), .Out(HEX2));
	// hexdriver kd2h(.In(kdr2[7:4]), .Out(HEX3));
	// hexdriver ku1l(.In(kur1[3:0]), .Out(HEX4));
	// hexdriver ku1h(.In(kur1[7:4]), .Out(HEX5));
	// hexdriver ku2l(.In(kur2[3:0]), .Out(HEX6));
	// hexdriver ku2h(.In(kur2[7:4]), .Out(HEX7));
	// hexdriver sthex(.In({1'b0,st}), .Out(HEX7));
endmodule