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paulrr2
fpga-network-stack
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xilinx-tcp-ip
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xilinx-tcp-ip
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Created with Raphaël 2.2.0
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Updated IPs for s_axilite
master
master
changes to script
Update README.md
Update README.md
Merge branch 'master' of https://github.com/fpgasystems/fpga-network-stack
Syncronization with github
Merge branch 'network_with_ooo'
ooo desn't hang
try to make ooo running
fixing issue with <64B packets on 64B data bus
change alignment of SIMD register write to 64B
Solve signal name problem in hdl/common/roce_stack.sv for 10G synthesis
no modification, test branch for ooo
Merge branch 'master' of gitlab.inf.ethz.ch:OU-SYSTEMS/fpga-network-stack
return true when port already open
Merge branch 'master' of gitlab.inf.ethz.ch:OU-SYSTEMS/fpga-network-stack
introducing response buffer to support up to 1024 connections
moved data conversion of RoCE to avoid critical warnings when roce stack is disabled
roce interface explanation
roce interface explanation
explanation of TCP interfaces
Merge branch 'master' of github.com:fpgasystems/fpga-network-stack
remove project from cmake
Update README.md
Update README.md
Update README.md
Update README.md
merge
deduplicate ip optinal header drop
fixing ip header drop
updating license & copyright
improving parametrization of tcp stack
fixing 10G tcp & udp
Merge branch 'master' of gitlab.inf.ethz.ch:OU-SYSTEMS/fpga-network-stack
adapting udp interface for 19.1
fix icmp width
Merge branch 'master' of gitlab.inf.ethz.ch:OU-SYSTEMS/fpga-network-stack
Merge branch 'master' of gitlab.inf.ethz.ch:OU-SYSTEMS/fpga-network-stack
fixin register slice for 256 & 128b
Merge branch 'master' of gitlab.inf.ethz.ch:OU-SYSTEMS/fpga-network-stack
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