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haiyang3
Verilog Ethernet
Commits
907081d2
Commit
907081d2
authored
3 years ago
by
Alex Forencich
Browse files
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Add support to demux for routing by tdest
parent
ccbca0c5
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Changes
4
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4 changed files
rtl/axis_demux.v
+30
-3
30 additions, 3 deletions
rtl/axis_demux.v
rtl/axis_demux_wrap.py
+5
-2
5 additions, 2 deletions
rtl/axis_demux_wrap.py
tb/axis_demux/Makefile
+3
-0
3 additions, 0 deletions
tb/axis_demux/Makefile
tb/axis_demux/test_axis_demux.py
+12
-4
12 additions, 4 deletions
tb/axis_demux/test_axis_demux.py
with
50 additions
and
9 deletions
rtl/axis_demux.v
+
30
−
3
View file @
907081d2
...
@@ -54,7 +54,9 @@ module axis_demux #
...
@@ -54,7 +54,9 @@ module axis_demux #
// Propagate tuser signal
// Propagate tuser signal
parameter
USER_ENABLE
=
1
,
parameter
USER_ENABLE
=
1
,
// tuser signal width
// tuser signal width
parameter
USER_WIDTH
=
1
parameter
USER_WIDTH
=
1
,
// route via tdest
parameter
TDEST_ROUTE
=
0
)
)
(
(
input
wire
clk
,
input
wire
clk
,
...
@@ -94,6 +96,21 @@ module axis_demux #
...
@@ -94,6 +96,21 @@ module axis_demux #
parameter
CL_M_COUNT
=
$
clog2
(
M_COUNT
);
parameter
CL_M_COUNT
=
$
clog2
(
M_COUNT
);
// check configuration
initial
begin
if
(
TDEST_ROUTE
)
begin
if
(
!
DEST_ENABLE
)
begin
$
error
(
"Error: TDEST_ROUTE set requires DEST_ENABLE set (instance %m)"
);
$
finish
;
end
if
(
S_DEST_WIDTH
<
CL_M_COUNT
)
begin
$
error
(
"Error: S_DEST_WIDTH too small for port count (instance %m)"
);
$
finish
;
end
end
end
reg
[
CL_M_COUNT
-
1
:
0
]
select_reg
=
{
CL_M_COUNT
{
1'b0
}}
,
select_ctl
,
select_next
;
reg
[
CL_M_COUNT
-
1
:
0
]
select_reg
=
{
CL_M_COUNT
{
1'b0
}}
,
select_ctl
,
select_next
;
reg
drop_reg
=
1'b0
,
drop_ctl
,
drop_next
;
reg
drop_reg
=
1'b0
,
drop_ctl
,
drop_next
;
reg
frame_reg
=
1'b0
,
frame_ctl
,
frame_next
;
reg
frame_reg
=
1'b0
,
frame_ctl
,
frame_next
;
...
@@ -133,8 +150,18 @@ always @* begin
...
@@ -133,8 +150,18 @@ always @* begin
if
(
!
frame_reg
&&
s_axis_tvalid
&&
s_axis_tready
)
begin
if
(
!
frame_reg
&&
s_axis_tvalid
&&
s_axis_tready
)
begin
// start of frame, grab select value
// start of frame, grab select value
select_ctl
=
select
;
if
(
TDEST_ROUTE
)
begin
drop_ctl
=
drop
||
select
>=
M_COUNT
;
if
(
M_COUNT
>
1
)
begin
select_ctl
=
s_axis_tdest
[
S_DEST_WIDTH
-
1
:
S_DEST_WIDTH
-
CL_M_COUNT
];
drop_ctl
=
s_axis_tdest
[
S_DEST_WIDTH
-
1
:
S_DEST_WIDTH
-
CL_M_COUNT
]
>=
M_COUNT
;
end
else
begin
select_ctl
=
0
;
drop_ctl
=
1'b0
;
end
end
else
begin
select_ctl
=
select
;
drop_ctl
=
drop
||
select
>=
M_COUNT
;
end
frame_ctl
=
1'b1
;
frame_ctl
=
1'b1
;
if
(
!
(
s_axis_tready
&&
s_axis_tvalid
&&
s_axis_tlast
))
begin
if
(
!
(
s_axis_tready
&&
s_axis_tvalid
&&
s_axis_tlast
))
begin
select_next
=
select_ctl
;
select_next
=
select_ctl
;
...
...
This diff is collapsed.
Click to expand it.
rtl/axis_demux_wrap.py
+
5
−
2
View file @
907081d2
...
@@ -89,7 +89,9 @@ module {{name}} #
...
@@ -89,7 +89,9 @@ module {{name}} #
// Propagate tuser signal
// Propagate tuser signal
parameter USER_ENABLE = 1,
parameter USER_ENABLE = 1,
// tuser signal width
// tuser signal width
parameter USER_WIDTH = 1
parameter USER_WIDTH = 1,
// route via tdest
parameter TDEST_ROUTE = 0
)
)
(
(
input wire clk,
input wire clk,
...
@@ -139,7 +141,8 @@ axis_demux #(
...
@@ -139,7 +141,8 @@ axis_demux #(
.S_DEST_WIDTH(S_DEST_WIDTH),
.S_DEST_WIDTH(S_DEST_WIDTH),
.M_DEST_WIDTH(M_DEST_WIDTH),
.M_DEST_WIDTH(M_DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
.USER_WIDTH(USER_WIDTH),
.TDEST_ROUTE(TDEST_ROUTE)
)
)
axis_demux_inst (
axis_demux_inst (
.clk(clk),
.clk(clk),
...
...
This diff is collapsed.
Click to expand it.
tb/axis_demux/Makefile
+
3
−
0
View file @
907081d2
...
@@ -46,6 +46,7 @@ export PARAM_M_DEST_WIDTH ?= 8
...
@@ -46,6 +46,7 @@ export PARAM_M_DEST_WIDTH ?= 8
export
PARAM_S_DEST_WIDTH
?=
$(
shell python
-c
"print(
$(
PARAM_M_DEST_WIDTH
)
+ (
$(
PARAM_PORTS
)
-1
)
.bit_length())"
)
export
PARAM_S_DEST_WIDTH
?=
$(
shell python
-c
"print(
$(
PARAM_M_DEST_WIDTH
)
+ (
$(
PARAM_PORTS
)
-1
)
.bit_length())"
)
export
PARAM_USER_ENABLE
?=
1
export
PARAM_USER_ENABLE
?=
1
export
PARAM_USER_WIDTH
?=
1
export
PARAM_USER_WIDTH
?=
1
export
PARAM_TDEST_ROUTE
?=
1
ifeq
($(SIM), icarus)
ifeq
($(SIM), icarus)
PLUSARGS
+=
-fst
PLUSARGS
+=
-fst
...
@@ -60,6 +61,7 @@ ifeq ($(SIM), icarus)
...
@@ -60,6 +61,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS
+=
-P
$(
TOPLEVEL
)
.M_DEST_WIDTH
=
$(
PARAM_M_DEST_WIDTH
)
COMPILE_ARGS
+=
-P
$(
TOPLEVEL
)
.M_DEST_WIDTH
=
$(
PARAM_M_DEST_WIDTH
)
COMPILE_ARGS
+=
-P
$(
TOPLEVEL
)
.USER_ENABLE
=
$(
PARAM_USER_ENABLE
)
COMPILE_ARGS
+=
-P
$(
TOPLEVEL
)
.USER_ENABLE
=
$(
PARAM_USER_ENABLE
)
COMPILE_ARGS
+=
-P
$(
TOPLEVEL
)
.USER_WIDTH
=
$(
PARAM_USER_WIDTH
)
COMPILE_ARGS
+=
-P
$(
TOPLEVEL
)
.USER_WIDTH
=
$(
PARAM_USER_WIDTH
)
COMPILE_ARGS
+=
-P
$(
TOPLEVEL
)
.TDEST_ROUTE
=
$(
PARAM_TDEST_ROUTE
)
ifeq
($(WAVES), 1)
ifeq
($(WAVES), 1)
VERILOG_SOURCES
+=
iverilog_dump.v
VERILOG_SOURCES
+=
iverilog_dump.v
...
@@ -78,6 +80,7 @@ else ifeq ($(SIM), verilator)
...
@@ -78,6 +80,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS
+=
-GM_DEST_WIDTH
=
$(
PARAM_M_DEST_WIDTH
)
COMPILE_ARGS
+=
-GM_DEST_WIDTH
=
$(
PARAM_M_DEST_WIDTH
)
COMPILE_ARGS
+=
-GUSER_ENABLE
=
$(
PARAM_USER_ENABLE
)
COMPILE_ARGS
+=
-GUSER_ENABLE
=
$(
PARAM_USER_ENABLE
)
COMPILE_ARGS
+=
-GUSER_WIDTH
=
$(
PARAM_USER_WIDTH
)
COMPILE_ARGS
+=
-GUSER_WIDTH
=
$(
PARAM_USER_WIDTH
)
COMPILE_ARGS
+=
-GTDEST_ROUTE
=
$(
PARAM_TDEST_ROUTE
)
ifeq
($(WAVES), 1)
ifeq
($(WAVES), 1)
COMPILE_ARGS
+=
--trace-fst
COMPILE_ARGS
+=
--trace-fst
...
...
This diff is collapsed.
Click to expand it.
tb/axis_demux/test_axis_demux.py
+
12
−
4
View file @
907081d2
...
@@ -82,7 +82,13 @@ async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=N
...
@@ -82,7 +82,13 @@ async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=N
tb
=
TB
(
dut
)
tb
=
TB
(
dut
)
id_count
=
2
**
len
(
tb
.
source
.
bus
.
tid
)
id_width
=
len
(
tb
.
source
.
bus
.
tid
)
id_count
=
2
**
id_width
id_mask
=
id_count
-
1
dest_width
=
len
(
tb
.
sink
[
0
].
bus
.
tid
)
dest_count
=
2
**
dest_width
dest_mask
=
dest_count
-
1
cur_id
=
1
cur_id
=
1
...
@@ -100,7 +106,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=N
...
@@ -100,7 +106,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=N
for
test_data
in
[
payload_data
(
x
)
for
x
in
payload_lengths
()]:
for
test_data
in
[
payload_data
(
x
)
for
x
in
payload_lengths
()]:
test_frame
=
AxiStreamFrame
(
test_data
)
test_frame
=
AxiStreamFrame
(
test_data
)
test_frame
.
tid
=
cur_id
test_frame
.
tid
=
cur_id
test_frame
.
tdest
=
cur_id
test_frame
.
tdest
=
cur_id
|
(
port
<<
dest_width
)
test_frames
.
append
(
test_frame
)
test_frames
.
append
(
test_frame
)
await
tb
.
source
.
send
(
test_frame
)
await
tb
.
source
.
send
(
test_frame
)
...
@@ -112,7 +118,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=N
...
@@ -112,7 +118,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=N
assert
rx_frame
.
tdata
==
test_frame
.
tdata
assert
rx_frame
.
tdata
==
test_frame
.
tdata
assert
rx_frame
.
tid
==
test_frame
.
tid
assert
rx_frame
.
tid
==
test_frame
.
tid
assert
rx_frame
.
tdest
==
test_frame
.
tdest
assert
rx_frame
.
tdest
==
(
test_frame
.
tdest
&
dest_mask
)
assert
not
rx_frame
.
tuser
assert
not
rx_frame
.
tuser
assert
tb
.
sink
[
port
].
empty
()
assert
tb
.
sink
[
port
].
empty
()
...
@@ -154,9 +160,10 @@ tests_dir = os.path.dirname(__file__)
...
@@ -154,9 +160,10 @@ tests_dir = os.path.dirname(__file__)
rtl_dir
=
os
.
path
.
abspath
(
os
.
path
.
join
(
tests_dir
,
'
..
'
,
'
..
'
,
'
rtl
'
))
rtl_dir
=
os
.
path
.
abspath
(
os
.
path
.
join
(
tests_dir
,
'
..
'
,
'
..
'
,
'
rtl
'
))
@pytest.mark.parametrize
(
"
tdest_route
"
,
[
0
,
1
])
@pytest.mark.parametrize
(
"
data_width
"
,
[
8
,
16
,
32
])
@pytest.mark.parametrize
(
"
data_width
"
,
[
8
,
16
,
32
])
@pytest.mark.parametrize
(
"
ports
"
,
[
4
])
@pytest.mark.parametrize
(
"
ports
"
,
[
4
])
def
test_axis_demux
(
request
,
ports
,
data_width
):
def
test_axis_demux
(
request
,
ports
,
data_width
,
tdest_route
):
dut
=
"
axis_demux
"
dut
=
"
axis_demux
"
wrapper
=
f
"
{
dut
}
_wrap_
{
ports
}
"
wrapper
=
f
"
{
dut
}
_wrap_
{
ports
}
"
module
=
os
.
path
.
splitext
(
os
.
path
.
basename
(
__file__
))[
0
]
module
=
os
.
path
.
splitext
(
os
.
path
.
basename
(
__file__
))[
0
]
...
@@ -187,6 +194,7 @@ def test_axis_demux(request, ports, data_width):
...
@@ -187,6 +194,7 @@ def test_axis_demux(request, ports, data_width):
parameters
[
'
S_DEST_WIDTH
'
]
=
parameters
[
'
M_DEST_WIDTH
'
]
+
(
ports
-
1
).
bit_length
()
parameters
[
'
S_DEST_WIDTH
'
]
=
parameters
[
'
M_DEST_WIDTH
'
]
+
(
ports
-
1
).
bit_length
()
parameters
[
'
USER_ENABLE
'
]
=
1
parameters
[
'
USER_ENABLE
'
]
=
1
parameters
[
'
USER_WIDTH
'
]
=
1
parameters
[
'
USER_WIDTH
'
]
=
1
parameters
[
'
TDEST_ROUTE
'
]
=
tdest_route
extra_env
=
{
f
'
PARAM_
{
k
}
'
:
str
(
v
)
for
k
,
v
in
parameters
.
items
()}
extra_env
=
{
f
'
PARAM_
{
k
}
'
:
str
(
v
)
for
k
,
v
in
parameters
.
items
()}
...
...
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