rtl/axis_adapter.v · 073d50d9dc0423c495db15d238e1933dcc9caa80 · haiyang3 / Verilog Ethernet · GitLab

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verilog-ethernet
rtl
axis_adapter.v

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Mar 30, 2022
073d50d9

Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 · 073d50d9
Alex Forencich authored Mar 30, 2022

073d50d9

Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
Alex Forencich authored Mar 30, 2022

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