gl - pipeline fixes

gl/gl_frame_buffer.sv

@@ -73,8 +73,8 @@ module gl_frame_buffer (
 
 	// VGA Pipelined continuous read
 
-	logic vga_rc_en, vga_fb_en, vga_pl_en;
-	logic vga_rc_en_next, vga_fb_en_next, vga_pl_en_next;
+	logic vga_rc_en, vga_fb_en, vga_pl_en, vga_out_en;
+	logic vga_rc_en_next, vga_fb_en_next, vga_pl_en_next, vga_out_en_next;
 	// Pipeline step out data
 	logic vga_fb_req, vga_fb_req_in;
 	logic [19:0] vga_fb_addr, vga_fb_addr_in;
@@ -83,6 +83,10 @@ module gl_frame_buffer (
 	// Pipeline step coordinates
 	logic [19:0] vga_rc_coord, vga_fb_coord, vga_pl_coord;
 	logic [19:0] vga_rc_coord_in, vga_fb_coord_in, vga_pl_coord_in;
+	// PL usage
+	logic vga_from_pl, vga_from_pl_next;
+	// SRAM Cache usage
+	logic vga_from_cache, vga_from_cache_next;
 	// SRAM 8-bit reads cache
 	logic [19:0] vga_fb_prev_addr, vga_fb_prev_addr_in;
 	logic [15:0] vga_fb_prev_data, vga_fb_prev_data_in;
@@ -92,36 +96,40 @@ module gl_frame_buffer (
 	// FB read1 wiring
 	assign read1_addr = vga_fb_addr;
 	assign read1_req = vga_fb_req;
-	// VGA Return value wiring
-	assign VGA_RGB = vga_pl_data;
 
 	always_ff @(posedge CLK) begin
 		if(RESET) begin
 			vga_rc_en <= 1'b0;
 			vga_fb_en <= 1'b0;
 			vga_pl_en <= 1'b0;
+			vga_out_en <= 1'b0;
 			vga_fb_req <= 1'b0;
 			vga_fb_addr <= 0;
-			vga_fb_data <= 0;
+			// vga_fb_data <= 0;
 			vga_pl_data <= 0;
 			vga_rc_coord <= 0;
 			vga_fb_coord <= 0;
 			vga_pl_coord <= 0;
 			vga_fb_prev_addr <= 20'hFFFFF;
 			vga_fb_prev_data <= 0;
+			vga_from_pl <= 1'b0;
+			vga_from_cache <= 1'b0;
 		end else begin
 			vga_rc_en <= vga_rc_en_next;
 			vga_fb_en <= vga_fb_en_next;
 			vga_pl_en <= vga_pl_en_next;
+			vga_out_en <= vga_out_en_next;
 			vga_fb_req <= vga_fb_req_in;
 			vga_fb_addr <= vga_fb_addr_in;
-			vga_fb_data <= vga_fb_data_in;
+			// vga_fb_data <= vga_fb_data_in;
 			vga_pl_data <= vga_pl_data_in;
 			vga_rc_coord <= vga_rc_coord_in;
 			vga_fb_coord <= vga_fb_coord_in;
 			vga_pl_coord <= vga_pl_coord_in;
 			vga_fb_prev_addr <= vga_fb_prev_addr_in;
 			vga_fb_prev_data <= vga_fb_prev_data_in;
+			vga_from_pl <= vga_from_pl_next;
+			vga_from_cache <= vga_from_cache_next;
 		end
 
 	end
@@ -137,6 +145,7 @@ module gl_frame_buffer (
 		vga_rc_en_next = VGA_REQ;
 		vga_fb_en_next = vga_rc_en;
 		vga_pl_en_next = vga_fb_en;
+		vga_out_en_next = vga_pl_en;
 		vga_rc_coord_in = {VGA_X, VGA_Y[8:0], ~BUF_ACTIVE};
 		vga_fb_coord_in = vga_rc_coord;
 		vga_pl_coord_in = vga_fb_addr;
@@ -148,6 +157,8 @@ module gl_frame_buffer (
 		RC_ADDR = vga_rc_coord_in;
 		RC_WE = 1'b0;
 		PL_ADDR = 8'hXX;
+		vga_from_pl_next = 1'b0;
+		vga_from_cache_next = 1'b0;
 
 		// VGA Pipeline
 
@@ -182,17 +193,23 @@ module gl_frame_buffer (
 			if (~vga_fb_req) begin
 				// This should only happen when cached read occurs
 				// Reading from the next adjacent location in background
-				vga_fb_data_in = vga_fb_prev_data;
+				// vga_fb_data_in = vga_fb_prev_data;
+				vga_from_cache_next = 1'b1;
 			end else begin
-				vga_fb_data_in = read1_data;
+				// vga_fb_data_in = read1_data;
 				vga_fb_prev_addr_in = vga_fb_addr;
-				vga_fb_prev_data_in = read1_data;
+				// vga_fb_prev_data_in = read1_data;
 			end
-		end else begin
-			vga_fb_data_in = vga_fb_data;
 		end
 		// Step 4: read palette
 		if (vga_pl_en) begin
+			if (vga_from_cache) begin
+				vga_fb_data = vga_fb_prev_data;
+			end else begin
+				vga_fb_data = read1_data;
+				vga_fb_prev_data_in = read1_data;
+			end
+
 			if (vga_pl_coord[19:16] >= 4'hA) begin
 				// A palette access
 				rc_avail = 1'b0;
@@ -203,7 +220,8 @@ module gl_frame_buffer (
 					// Lower bits
 					PL_ADDR = vga_fb_data[7:0];
 				end
-				vga_pl_data_in = PL_DATA_OUT;
+				vga_pl_data_in = 24'hff0000;
+				vga_from_pl_next = 1'b1;
 			end else begin
 				// Keep data from memory
 				// Up-sample RGB16 to RGB24: prioritize web-safe colors
@@ -213,8 +231,19 @@ module gl_frame_buffer (
 								  vga_fb_data[4:0],   vga_fb_data[3:1]};
 			end
 		end else begin
+			vga_fb_data = 16'hXXXX;
 			vga_pl_data_in = vga_pl_data;
 		end
+
+		// End: assign output to either SRAM output or PL output
+		if (vga_out_en) begin
+			if (vga_from_pl) begin
+				VGA_RGB = PL_DATA_OUT;
+			end else begin
+				VGA_RGB = vga_pl_data;
+			end
+		end else
+			VGA_RGB = 24'h0000ff;
 	end
 
 endmodule