osu_fpga_toplevel.sv

module osu_fpga_toplevel (
	input logic CLOCK_50,
	input logic[3:0] KEY,
	inout wire PS2_KBCLK, PS2_KBDAT,
	output logic [6:0] HEX0, HEX1, HEX4, HEX6
);


logic [7:0] keycode;
logic [2:0] state, counter;

ps2 kb(.CLK(CLOCK_50), .RESET(~KEY[0]), .AVL_READ(0), .AVL_WRITE(0), .AVL_CS(0),
	   .AVL_BYTE_EN(0), .AVL_ADDR(0), .AVL_WRITEDATA(0), .AVL_READDATA(0),
	   .PS2_CLK(PS2_KBCLK), .PS2_DATA(PS2_KBDAT),
	   .debug_keycode(keycode), .debug_state(state), .debug_counter(counter));

hexdriver h0(.In(keycode[3:0]), .Out(HEX0));
hexdriver h1(.In(keycode[7:4]), .Out(HEX1));
hexdriver h4(.In({1'b0, state}), .Out(HEX4));
hexdriver h6(.In({1'b0, counter}), .Out(HEX6));

endmodule