osu_fpga_toplevel_nativelink_simulation.rpt 987 B
Info: Start Nativelink Simulation process
========= EDA Simulation Settings =====================
Sim Mode : RTL
Family : cycloneive
Quartus root : c:/intelfpga_lite/17.1/quartus/bin64/
Quartus sim root : c:/intelfpga_lite/17.1/quartus/eda/sim_lib
Simulation Tool : modelsim-altera
Simulation Language : systemverilog
Simulation Mode : GUI
Sim Output File :
Sim SDF file :
Sim dir : simulation\modelsim
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Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script c:/intelfpga_lite/17.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File osu_fpga_toplevel_run_msim_rtl_systemverilog.do already exists - backing up current file as osu_fpga_toplevel_run_msim_rtl_systemverilog.do.bak2
Info: Spawning ModelSim-Altera Simulation software
Info: NativeLink simulation flow was successful