From ecf7cd5373120350041261627b065aa8455d89bf Mon Sep 17 00:00:00 2001
From: David Sidler <david.sidler@inf.ethz.ch>
Date: Fri, 30 Aug 2019 11:56:06 +0200
Subject: [PATCH] fix icmp width
---
hdl/common/network_stack.sv | 73 +++++++++++++++++++++++++++++++++----
projects/network_stack.tcl | 10 +++++
2 files changed, 76 insertions(+), 7 deletions(-)
diff --git a/hdl/common/network_stack.sv b/hdl/common/network_stack.sv
index d056e15..ad233ac 100755
--- a/hdl/common/network_stack.sv
+++ b/hdl/common/network_stack.sv
@@ -1599,13 +1599,6 @@ register_slice_wrapper #(.WIDTH(WIDTH)) axis_register_arp_in_slice(
.aresetn(net_aresetn),
.s_axis(axis_iph_to_arp_slice),
.m_axis(axis_arp_slice_to_arp)
-);
- // ICMP Input Slice
-register_slice_wrapper #(.WIDTH(WIDTH)) axis_register_icmp_in_slice(
- .aclk(net_clk),
- .aresetn(net_aresetn),
- .s_axis(axis_iph_to_icmp_slice),
- .m_axis(axis_icmp_slice_to_icmp)
);
// UDP Input Slice
register_slice_wrapper #(.WIDTH(WIDTH)) axis_register_upd_in_slice(
@@ -1642,6 +1635,72 @@ register_slice_wrapper #(.WIDTH(WIDTH)) axis_register_roce_out_slice(
.s_axis(axis_roce_to_roce_slice),
.m_axis(axis_roce_slice_to_merge)
);
+generate
+if (WIDTH==64) begin
+// ICMP Input Slice
+register_slice_wrapper #(.WIDTH(WIDTH)) axis_register_icmp_in_slice(
+ .aclk(net_clk),
+ .aresetn(net_aresetn),
+ .s_axis(axis_iph_to_icmp_slice),
+ .m_axis(axis_icmp_slice_to_icmp)
+);
+end
+if (WIDTH==128) begin
+// ICMP Input Slice
+//axis_register_slice_512 axis_register_icmp_in_slice(
+axis_128_to_64_converter icmp_in_data_converter (
+ .aclk(net_clk),
+ .aresetn(net_aresetn),
+ .s_axis_tvalid(axis_iph_to_icmp_slice.valid),
+ .s_axis_tready(axis_iph_to_icmp_slice.ready),
+ .s_axis_tdata(axis_iph_to_icmp_slice.data),
+ .s_axis_tkeep(axis_iph_to_icmp_slice.keep),
+ .s_axis_tlast(axis_iph_to_icmp_slice.last),
+ .m_axis_tvalid(axis_icmp_slice_to_icmp.valid),
+ .m_axis_tready(axis_icmp_slice_to_icmp.ready),
+ .m_axis_tdata(axis_icmp_slice_to_icmp.data),
+ .m_axis_tkeep(axis_icmp_slice_to_icmp.keep),
+ .m_axis_tlast(axis_icmp_slice_to_icmp.last)
+);
+end
+if (WIDTH==256) begin
+// ICMP Input Slice
+//axis_register_slice_512 axis_register_icmp_in_slice(
+axis_256_to_64_converter icmp_in_data_converter (
+ .aclk(net_clk),
+ .aresetn(net_aresetn),
+ .s_axis_tvalid(axis_iph_to_icmp_slice.valid),
+ .s_axis_tready(axis_iph_to_icmp_slice.ready),
+ .s_axis_tdata(axis_iph_to_icmp_slice.data),
+ .s_axis_tkeep(axis_iph_to_icmp_slice.keep),
+ .s_axis_tlast(axis_iph_to_icmp_slice.last),
+ .m_axis_tvalid(axis_icmp_slice_to_icmp.valid),
+ .m_axis_tready(axis_icmp_slice_to_icmp.ready),
+ .m_axis_tdata(axis_icmp_slice_to_icmp.data),
+ .m_axis_tkeep(axis_icmp_slice_to_icmp.keep),
+ .m_axis_tlast(axis_icmp_slice_to_icmp.last)
+);
+end
+if (WIDTH==512) begin
+// ICMP Input Slice
+//axis_register_slice_512 axis_register_icmp_in_slice(
+axis_512_to_64_converter icmp_in_data_converter (
+ .aclk(net_clk),
+ .aresetn(net_aresetn),
+ .s_axis_tvalid(axis_iph_to_icmp_slice.valid),
+ .s_axis_tready(axis_iph_to_icmp_slice.ready),
+ .s_axis_tdata(axis_iph_to_icmp_slice.data),
+ .s_axis_tkeep(axis_iph_to_icmp_slice.keep),
+ .s_axis_tlast(axis_iph_to_icmp_slice.last),
+ .m_axis_tvalid(axis_icmp_slice_to_icmp.valid),
+ .m_axis_tready(axis_icmp_slice_to_icmp.ready),
+ .m_axis_tdata(axis_icmp_slice_to_icmp.data),
+ .m_axis_tkeep(axis_icmp_slice_to_icmp.keep),
+ .m_axis_tlast(axis_icmp_slice_to_icmp.last)
+);
+end
+endgenerate
+
/*
* Network Controller
diff --git a/projects/network_stack.tcl b/projects/network_stack.tcl
index fb7fd4b..ad7b57d 100755
--- a/projects/network_stack.tcl
+++ b/projects/network_stack.tcl
@@ -118,11 +118,21 @@ set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {8} CONFIG.M_TDATA_NUM_BYTES {
generate_target {instantiation_template} [get_files $device_ip_dir/axis_64_to_128_converter/axis_64_to_128_converter.xci]
update_compile_order -fileset sources_1
+create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_128_to_64_converter -dir $device_ip_dir
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {16} CONFIG.M_TDATA_NUM_BYTES {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1} CONFIG.Component_Name {axis_128_to_64_converter}] [get_ips axis_128_to_64_converter]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_128_to_64_converter/axis_128_to_64_converter.xci]
+update_compile_order -fileset sources_1
+
create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_64_to_256_converter -dir $device_ip_dir
set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {8} CONFIG.M_TDATA_NUM_BYTES {32} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1} CONFIG.TDEST_WIDTH {1} CONFIG.Component_Name {axis_64_to_256_converter}] [get_ips axis_64_to_256_converter]
generate_target {instantiation_template} [get_files $device_ip_dir/axis_64_to_256_converter/axis_64_to_256_converter.xci]
update_compile_order -fileset sources_1
+create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_256_to_64_converter -dir $device_ip_dir
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {32} CONFIG.M_TDATA_NUM_BYTES {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1} CONFIG.Component_Name {axis_256to_64_converter}] [get_ips axis_256_to_64_converter]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_256_to_64_converter/axis_256_to_64_converter.xci]
+update_compile_order -fileset sources_1
+
#HLS IP cores
create_ip -name toe -vendor ethz.systems -library hls -version 1.6 -module_name toe_ip -dir $device_ip_dir
--
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