From 666993aadca2f5a156b6e35741865331d0d0533a Mon Sep 17 00:00:00 2001 From: mchiosa <monica.chiosa@inf.ethz.ch> Date: Fri, 21 Feb 2020 10:20:33 +0100 Subject: [PATCH] Solve signal name problem in hdl/common/roce_stack.sv for 10G synthesis --- hdl/common/roce_stack.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hdl/common/roce_stack.sv b/hdl/common/roce_stack.sv index 67a9fdb..53bc471 100755 --- a/hdl/common/roce_stack.sv +++ b/hdl/common/roce_stack.sv @@ -197,10 +197,10 @@ axis_512_to_64_converter roce_read_data_converter ( axis_512_to_64_converter roce_tx_data_converter ( .aclk(net_clk), // input wire aclk .aresetn(net_aresetn), // input wire aresetn - .s_axis_tvalid(s_axis_roce_role_tx_data.valid), // input wire s_axis_tvalid - .s_axis_tready(s_axis_roce_role_tx_data.ready), // output wire s_axis_tready - .s_axis_tdata(s_axis_roce_role_tx_data.data), // input wire [63 : 0] s_axis_tdata - .s_axis_tkeep(s_axis_roce_role_tx_data.keep), // input wire [7 : 0] s_axis_tkeep + .s_axis_tvalid(s_axis_tx_data.valid), // input wire s_axis_tvalid + .s_axis_tready(s_axis_tx_data.ready), // output wire s_axis_tready + .s_axis_tdata(s_axis_tx_data.data), // input wire [63 : 0] s_axis_tdata + .s_axis_tkeep(s_axis_tx_data.keep), // input wire [7 : 0] s_axis_tkeep .s_axis_tlast(s_axis_tx_data.last), // input wire s_axis_tlast .m_axis_tvalid(axis_tx_data.valid), // output wire m_axis_tvalid .m_axis_tready(axis_tx_data.ready), // input wire m_axis_tready -- GitLab