diff --git a/hdl/common/network_stack.sv b/hdl/common/network_stack.sv
index 07dddb036ad43686e1e470778563173499b7a468..b79ee91c0bde046f870c5d9930870ebc53e4646c 100755
--- a/hdl/common/network_stack.sv
+++ b/hdl/common/network_stack.sv
@@ -803,6 +803,38 @@ axis_register_slice_64 axis_register_AXI_S (
.m_axis_tlast(axis_slice_to_ibh.last) // output wire m_axis_tlast
);
end
+if (WIDTH==128) begin
+axis_register_slice_128 axis_register_AXI_S (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(s_axis_net.valid), // input wire s_axis_tvalid
+ .s_axis_tready(s_axis_net.ready), // output wire s_axis_tready
+ .s_axis_tdata(s_axis_net.data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(s_axis_net.keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(s_axis_net.last), // input wire s_axis_tlast
+ .m_axis_tvalid(axis_slice_to_ibh.valid), // output wire m_axis_tvalid
+ .m_axis_tready(axis_slice_to_ibh.ready), // input wire m_axis_tready
+ .m_axis_tdata(axis_slice_to_ibh.data), // output wire [63 : 0] m_axis_tdata
+ .m_axis_tkeep(axis_slice_to_ibh.keep), // output wire [7 : 0] m_axis_tkeep
+ .m_axis_tlast(axis_slice_to_ibh.last) // output wire m_axis_tlast
+);
+end
+if (WIDTH==256) begin
+axis_register_slice_256 axis_register_AXI_S (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(s_axis_net.valid), // input wire s_axis_tvalid
+ .s_axis_tready(s_axis_net.ready), // output wire s_axis_tready
+ .s_axis_tdata(s_axis_net.data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(s_axis_net.keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(s_axis_net.last), // input wire s_axis_tlast
+ .m_axis_tvalid(axis_slice_to_ibh.valid), // output wire m_axis_tvalid
+ .m_axis_tready(axis_slice_to_ibh.ready), // input wire m_axis_tready
+ .m_axis_tdata(axis_slice_to_ibh.data), // output wire [63 : 0] m_axis_tdata
+ .m_axis_tkeep(axis_slice_to_ibh.keep), // output wire [7 : 0] m_axis_tkeep
+ .m_axis_tlast(axis_slice_to_ibh.last) // output wire m_axis_tlast
+);
+end
if (WIDTH==512) begin
axis_register_slice_512 axis_register_AXI_S (
.aclk(net_clk), // input wire aclk
@@ -1036,6 +1068,222 @@ axis_interconnect_2to1 mac_merger (
//.S02_ARB_REQ_SUPPRESS(1'b0) // input S01_ARB_REQ_SUPPRESS
);
end
+if (WIDTH==128) begin
+axi_stream #(.WIDTH(128)) axis_icmp_slice_to_merge();
+axis_64_to_128_converter icmp_out_data_converter (
+ .aclk(net_clk),
+ .aresetn(net_aresetn),
+ .s_axis_tvalid(axis_icmp_to_icmp_slice.valid),
+ .s_axis_tready(axis_icmp_to_icmp_slice.ready),
+ .s_axis_tdata(axis_icmp_to_icmp_slice.data),
+ .s_axis_tkeep(axis_icmp_to_icmp_slice.keep),
+ .s_axis_tlast(axis_icmp_to_icmp_slice.last),
+ .s_axis_tdest(0),
+ .m_axis_tvalid(axis_icmp_slice_to_merge.valid),
+ .m_axis_tready(axis_icmp_slice_to_merge.ready),
+ .m_axis_tdata(axis_icmp_slice_to_merge.data),
+ .m_axis_tkeep(axis_icmp_slice_to_merge.keep),
+ .m_axis_tlast(axis_icmp_slice_to_merge.last),
+ .m_axis_tdest()
+);
+// merges icmp and tcp
+axis_interconnect_128_4to1 ip_merger (
+ .ACLK(net_clk), // input wire ACLK
+ .ARESETN(net_aresetn), // input wire ARESETN
+ .S00_AXIS_ACLK(net_clk), // input wire S00_AXIS_ACLK
+ .S01_AXIS_ACLK(net_clk), // input wire S01_AXIS_ACLK
+ .S02_AXIS_ACLK(net_clk), // input wire S02_AXIS_ACLK
+ .S03_AXIS_ACLK(net_clk), // input wire S03_AXIS_ACLK
+ .S00_AXIS_ARESETN(net_aresetn), // input wire S00_AXIS_ARESETN
+ .S01_AXIS_ARESETN(net_aresetn), // input wire S01_AXIS_ARESETN
+ .S02_AXIS_ARESETN(net_aresetn), // input wire S02_AXIS_ARESETN
+ .S03_AXIS_ARESETN(net_aresetn), // input wire S03_AXIS_ARESETN
+
+ .S00_AXIS_TVALID(axis_icmp_slice_to_merge.valid), // input wire S00_AXIS_TVALID
+ .S00_AXIS_TREADY(axis_icmp_slice_to_merge.ready), // output wire S00_AXIS_TREADY
+ .S00_AXIS_TDATA(axis_icmp_slice_to_merge.data), // input wire [63 : 0] S00_AXIS_TDATA
+ .S00_AXIS_TKEEP(axis_icmp_slice_to_merge.keep), // input wire [7 : 0] S00_AXIS_TKEEP
+ .S00_AXIS_TLAST(axis_icmp_slice_to_merge.last), // input wire S00_AXIS_TLAST
+
+ .S01_AXIS_TVALID(axis_udp_slice_to_merge.valid), // input wire S01_AXIS_TVALID
+ .S01_AXIS_TREADY(axis_udp_slice_to_merge.ready), // output wire S01_AXIS_TREADY
+ .S01_AXIS_TDATA(axis_udp_slice_to_merge.data), // input wire [63 : 0] S01_AXIS_TDATA
+ .S01_AXIS_TKEEP(axis_udp_slice_to_merge.keep), // input wire [7 : 0] S01_AXIS_TKEEP
+ .S01_AXIS_TLAST(axis_udp_slice_to_merge.last), // input wire S01_AXIS_TLAST
+
+ .S02_AXIS_TVALID(axis_toe_to_toe_slice.valid), // input wire S02_AXIS_TVALID
+ .S02_AXIS_TREADY(axis_toe_to_toe_slice.ready), // output wire S02_AXIS_TREADY
+ .S02_AXIS_TDATA(axis_toe_to_toe_slice.data), // input wire [63 : 0] S02_AXIS_TDATA
+ .S02_AXIS_TKEEP(axis_toe_to_toe_slice.keep), // input wire [7 : 0] S02_AXIS_TKEEP
+ .S02_AXIS_TLAST(axis_toe_to_toe_slice.last), // input wire S02_AXIS_TLAST
+
+ .S03_AXIS_TVALID(axis_roce_slice_to_merge.valid), // input wire S01_AXIS_TVALID
+ .S03_AXIS_TREADY(axis_roce_slice_to_merge.ready), // output wire S01_AXIS_TREADY
+ .S03_AXIS_TDATA(axis_roce_slice_to_merge.data), // input wire [63 : 0] S01_AXIS_TDATA
+ .S03_AXIS_TKEEP(axis_roce_slice_to_merge.keep), // input wire [7 : 0] S01_AXIS_TKEEP
+ .S03_AXIS_TLAST(axis_roce_slice_to_merge.last), // input wire S01_AXIS_TLAST
+
+ .M00_AXIS_ACLK(net_clk), // input wire M00_AXIS_ACLK
+ .M00_AXIS_ARESETN(net_aresetn), // input wire M00_AXIS_ARESETN
+ .M00_AXIS_TVALID(axis_intercon_to_mie.valid), // output wire M00_AXIS_TVALID
+ .M00_AXIS_TREADY(axis_intercon_to_mie.ready), // input wire M00_AXIS_TREADY
+ .M00_AXIS_TDATA(axis_intercon_to_mie.data), // output wire [63 : 0] M00_AXIS_TDATA
+ .M00_AXIS_TKEEP(axis_intercon_to_mie.keep), // output wire [7 : 0] M00_AXIS_TKEEP
+ .M00_AXIS_TLAST(axis_intercon_to_mie.last), // output wire M00_AXIS_TLAST
+ .S00_ARB_REQ_SUPPRESS(1'b0), // input wire S00_ARB_REQ_SUPPRESS
+ .S01_ARB_REQ_SUPPRESS(1'b0), // input wire S01_ARB_REQ_SUPPRESS
+ .S02_ARB_REQ_SUPPRESS(1'b0), // input wire S02_ARB_REQ_SUPPRESS
+ .S03_ARB_REQ_SUPPRESS(1'b0) // input wire S02_ARB_REQ_SUPPRESS
+);
+
+// merges ip and arp
+axis_interconnect_128_2to1 mac_merger (
+ .ACLK(net_clk), // input ACLK
+ .ARESETN(net_aresetn), // input ARESETN
+ .S00_AXIS_ACLK(net_clk), // input S00_AXIS_ACLK
+ .S01_AXIS_ACLK(net_clk), // input S01_AXIS_ACLK
+ //.S02_AXIS_ACLK(net_clk), // input S01_AXIS_ACLK
+ .S00_AXIS_ARESETN(net_aresetn), // input S00_AXIS_ARESETN
+ .S01_AXIS_ARESETN(net_aresetn), // input S01_AXIS_ARESETN
+ //.S02_AXIS_ARESETN(net_aresetn), // input S01_AXIS_ARESETN
+ .S00_AXIS_TVALID(axis_arp_to_arp_slice.valid), // input S00_AXIS_TVALID
+ .S00_AXIS_TREADY(axis_arp_to_arp_slice.ready), // output S00_AXIS_TREADY
+ .S00_AXIS_TDATA(axis_arp_to_arp_slice.data), // input [63 : 0] S00_AXIS_TDATA
+ .S00_AXIS_TKEEP(axis_arp_to_arp_slice.keep), // input [7 : 0] S00_AXIS_TKEEP
+ .S00_AXIS_TLAST(axis_arp_to_arp_slice.last), // input S00_AXIS_TLAST
+
+ .S01_AXIS_TVALID(axis_mie_to_intercon.valid), // input S01_AXIS_TVALID
+ .S01_AXIS_TREADY(axis_mie_to_intercon.ready), // output S01_AXIS_TREADY
+ .S01_AXIS_TDATA(axis_mie_to_intercon.data), // input [63 : 0] S01_AXIS_TDATA
+ .S01_AXIS_TKEEP(axis_mie_to_intercon.keep), // input [7 : 0] S01_AXIS_TKEEP
+ .S01_AXIS_TLAST(axis_mie_to_intercon.last), // input S01_AXIS_TLAST
+
+ /*.S02_AXIS_TVALID(axis_ethencode_to_intercon.valid), // input S01_AXIS_TVALID
+ .S02_AXIS_TREADY(axis_ethencode_to_intercon.ready), // output S01_AXIS_TREADY
+ .S02_AXIS_TDATA(axis_ethencode_to_intercon.data), // input [63 : 0] S01_AXIS_TDATA
+ .S02_AXIS_TKEEP(axis_ethencode_to_intercon.keep), // input [7 : 0] S01_AXIS_TKEEP
+ .S02_AXIS_TLAST(axis_ethencode_to_intercon.last), // input S01_AXIS_TLAST*/
+
+ .M00_AXIS_ACLK(net_clk), // input M00_AXIS_ACLK
+ .M00_AXIS_ARESETN(net_aresetn), // input M00_AXIS_ARESETN
+ .M00_AXIS_TVALID(m_axis_net.valid), // output M00_AXIS_TVALID
+ .M00_AXIS_TREADY(m_axis_net.ready), // input M00_AXIS_TREADY
+ .M00_AXIS_TDATA(m_axis_net.data), // output [63 : 0] M00_AXIS_TDATA
+ .M00_AXIS_TKEEP(m_axis_net.keep), // output [7 : 0] M00_AXIS_TKEEP
+ .M00_AXIS_TLAST(m_axis_net.last), // output M00_AXIS_TLAST
+ .S00_ARB_REQ_SUPPRESS(1'b0), // input S00_ARB_REQ_SUPPRESS
+ .S01_ARB_REQ_SUPPRESS(1'b0) // input S01_ARB_REQ_SUPPRESS
+ //.S02_ARB_REQ_SUPPRESS(1'b0) // input S01_ARB_REQ_SUPPRESS
+);
+end
+if (WIDTH==256) begin
+axi_stream #(.WIDTH(256)) axis_icmp_slice_to_merge();
+axis_64_to_256_converter icmp_out_data_converter (
+ .aclk(net_clk),
+ .aresetn(net_aresetn),
+ .s_axis_tvalid(axis_icmp_to_icmp_slice.valid),
+ .s_axis_tready(axis_icmp_to_icmp_slice.ready),
+ .s_axis_tdata(axis_icmp_to_icmp_slice.data),
+ .s_axis_tkeep(axis_icmp_to_icmp_slice.keep),
+ .s_axis_tlast(axis_icmp_to_icmp_slice.last),
+ .s_axis_tdest(0),
+ .m_axis_tvalid(axis_icmp_slice_to_merge.valid),
+ .m_axis_tready(axis_icmp_slice_to_merge.ready),
+ .m_axis_tdata(axis_icmp_slice_to_merge.data),
+ .m_axis_tkeep(axis_icmp_slice_to_merge.keep),
+ .m_axis_tlast(axis_icmp_slice_to_merge.last),
+ .m_axis_tdest()
+);
+// merges icmp and tcp
+axis_interconnect_256_4to1 ip_merger (
+ .ACLK(net_clk), // input wire ACLK
+ .ARESETN(net_aresetn), // input wire ARESETN
+ .S00_AXIS_ACLK(net_clk), // input wire S00_AXIS_ACLK
+ .S01_AXIS_ACLK(net_clk), // input wire S01_AXIS_ACLK
+ .S02_AXIS_ACLK(net_clk), // input wire S02_AXIS_ACLK
+ .S03_AXIS_ACLK(net_clk), // input wire S03_AXIS_ACLK
+ .S00_AXIS_ARESETN(net_aresetn), // input wire S00_AXIS_ARESETN
+ .S01_AXIS_ARESETN(net_aresetn), // input wire S01_AXIS_ARESETN
+ .S02_AXIS_ARESETN(net_aresetn), // input wire S02_AXIS_ARESETN
+ .S03_AXIS_ARESETN(net_aresetn), // input wire S03_AXIS_ARESETN
+
+ .S00_AXIS_TVALID(axis_icmp_slice_to_merge.valid), // input wire S00_AXIS_TVALID
+ .S00_AXIS_TREADY(axis_icmp_slice_to_merge.ready), // output wire S00_AXIS_TREADY
+ .S00_AXIS_TDATA(axis_icmp_slice_to_merge.data), // input wire [63 : 0] S00_AXIS_TDATA
+ .S00_AXIS_TKEEP(axis_icmp_slice_to_merge.keep), // input wire [7 : 0] S00_AXIS_TKEEP
+ .S00_AXIS_TLAST(axis_icmp_slice_to_merge.last), // input wire S00_AXIS_TLAST
+
+ .S01_AXIS_TVALID(axis_udp_slice_to_merge.valid), // input wire S01_AXIS_TVALID
+ .S01_AXIS_TREADY(axis_udp_slice_to_merge.ready), // output wire S01_AXIS_TREADY
+ .S01_AXIS_TDATA(axis_udp_slice_to_merge.data), // input wire [63 : 0] S01_AXIS_TDATA
+ .S01_AXIS_TKEEP(axis_udp_slice_to_merge.keep), // input wire [7 : 0] S01_AXIS_TKEEP
+ .S01_AXIS_TLAST(axis_udp_slice_to_merge.last), // input wire S01_AXIS_TLAST
+
+ .S02_AXIS_TVALID(axis_toe_to_toe_slice.valid), // input wire S02_AXIS_TVALID
+ .S02_AXIS_TREADY(axis_toe_to_toe_slice.ready), // output wire S02_AXIS_TREADY
+ .S02_AXIS_TDATA(axis_toe_to_toe_slice.data), // input wire [63 : 0] S02_AXIS_TDATA
+ .S02_AXIS_TKEEP(axis_toe_to_toe_slice.keep), // input wire [7 : 0] S02_AXIS_TKEEP
+ .S02_AXIS_TLAST(axis_toe_to_toe_slice.last), // input wire S02_AXIS_TLAST
+
+ .S03_AXIS_TVALID(axis_roce_slice_to_merge.valid), // input wire S01_AXIS_TVALID
+ .S03_AXIS_TREADY(axis_roce_slice_to_merge.ready), // output wire S01_AXIS_TREADY
+ .S03_AXIS_TDATA(axis_roce_slice_to_merge.data), // input wire [63 : 0] S01_AXIS_TDATA
+ .S03_AXIS_TKEEP(axis_roce_slice_to_merge.keep), // input wire [7 : 0] S01_AXIS_TKEEP
+ .S03_AXIS_TLAST(axis_roce_slice_to_merge.last), // input wire S01_AXIS_TLAST
+
+ .M00_AXIS_ACLK(net_clk), // input wire M00_AXIS_ACLK
+ .M00_AXIS_ARESETN(net_aresetn), // input wire M00_AXIS_ARESETN
+ .M00_AXIS_TVALID(axis_intercon_to_mie.valid), // output wire M00_AXIS_TVALID
+ .M00_AXIS_TREADY(axis_intercon_to_mie.ready), // input wire M00_AXIS_TREADY
+ .M00_AXIS_TDATA(axis_intercon_to_mie.data), // output wire [63 : 0] M00_AXIS_TDATA
+ .M00_AXIS_TKEEP(axis_intercon_to_mie.keep), // output wire [7 : 0] M00_AXIS_TKEEP
+ .M00_AXIS_TLAST(axis_intercon_to_mie.last), // output wire M00_AXIS_TLAST
+ .S00_ARB_REQ_SUPPRESS(1'b0), // input wire S00_ARB_REQ_SUPPRESS
+ .S01_ARB_REQ_SUPPRESS(1'b0), // input wire S01_ARB_REQ_SUPPRESS
+ .S02_ARB_REQ_SUPPRESS(1'b0), // input wire S02_ARB_REQ_SUPPRESS
+ .S03_ARB_REQ_SUPPRESS(1'b0) // input wire S02_ARB_REQ_SUPPRESS
+);
+
+// merges ip and arp
+axis_interconnect_256_2to1 mac_merger (
+ .ACLK(net_clk), // input ACLK
+ .ARESETN(net_aresetn), // input ARESETN
+ .S00_AXIS_ACLK(net_clk), // input S00_AXIS_ACLK
+ .S01_AXIS_ACLK(net_clk), // input S01_AXIS_ACLK
+ //.S02_AXIS_ACLK(net_clk), // input S01_AXIS_ACLK
+ .S00_AXIS_ARESETN(net_aresetn), // input S00_AXIS_ARESETN
+ .S01_AXIS_ARESETN(net_aresetn), // input S01_AXIS_ARESETN
+ //.S02_AXIS_ARESETN(net_aresetn), // input S01_AXIS_ARESETN
+ .S00_AXIS_TVALID(axis_arp_to_arp_slice.valid), // input S00_AXIS_TVALID
+ .S00_AXIS_TREADY(axis_arp_to_arp_slice.ready), // output S00_AXIS_TREADY
+ .S00_AXIS_TDATA(axis_arp_to_arp_slice.data), // input [63 : 0] S00_AXIS_TDATA
+ .S00_AXIS_TKEEP(axis_arp_to_arp_slice.keep), // input [7 : 0] S00_AXIS_TKEEP
+ .S00_AXIS_TLAST(axis_arp_to_arp_slice.last), // input S00_AXIS_TLAST
+
+ .S01_AXIS_TVALID(axis_mie_to_intercon.valid), // input S01_AXIS_TVALID
+ .S01_AXIS_TREADY(axis_mie_to_intercon.ready), // output S01_AXIS_TREADY
+ .S01_AXIS_TDATA(axis_mie_to_intercon.data), // input [63 : 0] S01_AXIS_TDATA
+ .S01_AXIS_TKEEP(axis_mie_to_intercon.keep), // input [7 : 0] S01_AXIS_TKEEP
+ .S01_AXIS_TLAST(axis_mie_to_intercon.last), // input S01_AXIS_TLAST
+
+ /*.S02_AXIS_TVALID(axis_ethencode_to_intercon.valid), // input S01_AXIS_TVALID
+ .S02_AXIS_TREADY(axis_ethencode_to_intercon.ready), // output S01_AXIS_TREADY
+ .S02_AXIS_TDATA(axis_ethencode_to_intercon.data), // input [63 : 0] S01_AXIS_TDATA
+ .S02_AXIS_TKEEP(axis_ethencode_to_intercon.keep), // input [7 : 0] S01_AXIS_TKEEP
+ .S02_AXIS_TLAST(axis_ethencode_to_intercon.last), // input S01_AXIS_TLAST*/
+
+ .M00_AXIS_ACLK(net_clk), // input M00_AXIS_ACLK
+ .M00_AXIS_ARESETN(net_aresetn), // input M00_AXIS_ARESETN
+ .M00_AXIS_TVALID(m_axis_net.valid), // output M00_AXIS_TVALID
+ .M00_AXIS_TREADY(m_axis_net.ready), // input M00_AXIS_TREADY
+ .M00_AXIS_TDATA(m_axis_net.data), // output [63 : 0] M00_AXIS_TDATA
+ .M00_AXIS_TKEEP(m_axis_net.keep), // output [7 : 0] M00_AXIS_TKEEP
+ .M00_AXIS_TLAST(m_axis_net.last), // output M00_AXIS_TLAST
+ .S00_ARB_REQ_SUPPRESS(1'b0), // input S00_ARB_REQ_SUPPRESS
+ .S01_ARB_REQ_SUPPRESS(1'b0) // input S01_ARB_REQ_SUPPRESS
+ //.S02_ARB_REQ_SUPPRESS(1'b0) // input S01_ARB_REQ_SUPPRESS
+);
+end
if (WIDTH==512) begin
axi_stream #(.WIDTH(512)) axis_icmp_slice_to_merge();
axis_64_to_512_converter icmp_out_data_converter (
diff --git a/hdl/common/tcp_stack.sv b/hdl/common/tcp_stack.sv
index bc0a4fe6370d25a46af37c2eef4a6ce8f279982d..8984bde9b55a7298a774c7b332d980ef3ea76fc3 100755
--- a/hdl/common/tcp_stack.sv
+++ b/hdl/common/tcp_stack.sv
@@ -494,7 +494,140 @@ axis_64_to_512_converter tcp_txwrite_data_converter (
.m_axis_tdest() // output wire m_axis_tlast
);
end
+if (WIDTH==128) begin
+//TCP Data Path
+`ifndef RX_DDR_BYPASS
+axis_512_to_128_converter tcp_rxread_data_converter (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(s_axis_mem_read_data[ddrPortNetworkRx].valid), // input wire s_axis_tvalid
+ .s_axis_tready(s_axis_mem_read_data[ddrPortNetworkRx].ready), // output wire s_axis_tready
+ .s_axis_tdata(s_axis_mem_read_data[ddrPortNetworkRx].data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(s_axis_mem_read_data[ddrPortNetworkRx].keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(s_axis_mem_read_data[ddrPortNetworkRx].last), // input wire s_axis_tlast
+ .m_axis_tvalid(axis_rxread_data.valid), // output wire m_axis_tvalid
+ .m_axis_tready(axis_rxread_data.ready), // input wire m_axis_tready
+ .m_axis_tdata(axis_rxread_data.data), // output wire [511 : 0] m_axis_tdata
+ .m_axis_tkeep(axis_rxread_data.keep), // output wire [63 : 0] m_axis_tkeep
+ .m_axis_tlast(axis_rxread_data.last) // output wire m_axis_tlast
+);
+axis_128_to_512_converter tcp_rxwrite_data_converter (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(axis_rxwrite_data.valid), // input wire s_axis_tvalid
+ .s_axis_tready(axis_rxwrite_data.ready), // output wire s_axis_tready
+ .s_axis_tdata(axis_rxwrite_data.data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(axis_rxwrite_data.keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(axis_rxwrite_data.last), // input wire s_axis_tlast
+ .s_axis_tdest(1'b0), // input wire s_axis_tlast
+ .m_axis_tvalid(m_axis_mem_write_data[ddrPortNetworkRx].valid), // output wire m_axis_tvalid
+ .m_axis_tready(m_axis_mem_write_data[ddrPortNetworkRx].ready), // input wire m_axis_tready
+ .m_axis_tdata(m_axis_mem_write_data[ddrPortNetworkRx].data), // output wire [511 : 0] m_axis_tdata
+ .m_axis_tkeep(m_axis_mem_write_data[ddrPortNetworkRx].keep), // output wire [63 : 0] m_axis_tkeep
+ .m_axis_tlast(m_axis_mem_write_data[ddrPortNetworkRx].last), // output wire m_axis_tlast
+ .m_axis_tdest() // output wire m_axis_tlast
+);
+`endif
+axis_512_to_128_converter tcp_txread_data_converter (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(s_axis_mem_read_data[ddrPortNetworkTx].valid), // input wire s_axis_tvalid
+ .s_axis_tready(s_axis_mem_read_data[ddrPortNetworkTx].ready), // output wire s_axis_tready
+ .s_axis_tdata(s_axis_mem_read_data[ddrPortNetworkTx].data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(s_axis_mem_read_data[ddrPortNetworkTx].keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(s_axis_mem_read_data[ddrPortNetworkTx].last), // input wire s_axis_tlast
+ .m_axis_tvalid(axis_txread_data.valid), // output wire m_axis_tvalid
+ .m_axis_tready(axis_txread_data.ready), // input wire m_axis_tready
+ .m_axis_tdata(axis_txread_data.data), // output wire [511 : 0] m_axis_tdata
+ .m_axis_tkeep(axis_txread_data.keep), // output wire [63 : 0] m_axis_tkeep
+ .m_axis_tlast(axis_txread_data.last) // output wire m_axis_tlast
+);
+
+axis_128_to_512_converter tcp_txwrite_data_converter (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(axis_txwrite_data.valid), // input wire s_axis_tvalid
+ .s_axis_tready(axis_txwrite_data.ready), // output wire s_axis_tready
+ .s_axis_tdata(axis_txwrite_data.data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(axis_txwrite_data.keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(axis_txwrite_data.last), // input wire s_axis_tlast
+ .s_axis_tdest(1'b0), // input wire s_axis_tlast
+ .m_axis_tvalid(m_axis_mem_write_data[ddrPortNetworkTx].valid), // output wire m_axis_tvalid
+ .m_axis_tready(m_axis_mem_write_data[ddrPortNetworkTx].ready), // input wire m_axis_tready
+ .m_axis_tdata(m_axis_mem_write_data[ddrPortNetworkTx].data), // output wire [511 : 0] m_axis_tdata
+ .m_axis_tkeep(m_axis_mem_write_data[ddrPortNetworkTx].keep), // output wire [63 : 0] m_axis_tkeep
+ .m_axis_tlast(m_axis_mem_write_data[ddrPortNetworkTx].last), // output wire m_axis_tlast
+ .m_axis_tdest() // output wire m_axis_tlast
+);
+end
+if (WIDTH==256) begin
+//TCP Data Path
+`ifndef RX_DDR_BYPASS
+axis_512_to_256_converter tcp_rxread_data_converter (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(s_axis_mem_read_data[ddrPortNetworkRx].valid), // input wire s_axis_tvalid
+ .s_axis_tready(s_axis_mem_read_data[ddrPortNetworkRx].ready), // output wire s_axis_tready
+ .s_axis_tdata(s_axis_mem_read_data[ddrPortNetworkRx].data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(s_axis_mem_read_data[ddrPortNetworkRx].keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(s_axis_mem_read_data[ddrPortNetworkRx].last), // input wire s_axis_tlast
+ .m_axis_tvalid(axis_rxread_data.valid), // output wire m_axis_tvalid
+ .m_axis_tready(axis_rxread_data.ready), // input wire m_axis_tready
+ .m_axis_tdata(axis_rxread_data.data), // output wire [511 : 0] m_axis_tdata
+ .m_axis_tkeep(axis_rxread_data.keep), // output wire [63 : 0] m_axis_tkeep
+ .m_axis_tlast(axis_rxread_data.last) // output wire m_axis_tlast
+);
+
+axis_256_to_512_converter tcp_rxwrite_data_converter (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(axis_rxwrite_data.valid), // input wire s_axis_tvalid
+ .s_axis_tready(axis_rxwrite_data.ready), // output wire s_axis_tready
+ .s_axis_tdata(axis_rxwrite_data.data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(axis_rxwrite_data.keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(axis_rxwrite_data.last), // input wire s_axis_tlast
+ .s_axis_tdest(1'b0), // input wire s_axis_tlast
+ .m_axis_tvalid(m_axis_mem_write_data[ddrPortNetworkRx].valid), // output wire m_axis_tvalid
+ .m_axis_tready(m_axis_mem_write_data[ddrPortNetworkRx].ready), // input wire m_axis_tready
+ .m_axis_tdata(m_axis_mem_write_data[ddrPortNetworkRx].data), // output wire [511 : 0] m_axis_tdata
+ .m_axis_tkeep(m_axis_mem_write_data[ddrPortNetworkRx].keep), // output wire [63 : 0] m_axis_tkeep
+ .m_axis_tlast(m_axis_mem_write_data[ddrPortNetworkRx].last), // output wire m_axis_tlast
+ .m_axis_tdest() // output wire m_axis_tlast
+);
+`endif
+axis_512_to_256_converter tcp_txread_data_converter (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(s_axis_mem_read_data[ddrPortNetworkTx].valid), // input wire s_axis_tvalid
+ .s_axis_tready(s_axis_mem_read_data[ddrPortNetworkTx].ready), // output wire s_axis_tready
+ .s_axis_tdata(s_axis_mem_read_data[ddrPortNetworkTx].data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(s_axis_mem_read_data[ddrPortNetworkTx].keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(s_axis_mem_read_data[ddrPortNetworkTx].last), // input wire s_axis_tlast
+ .m_axis_tvalid(axis_txread_data.valid), // output wire m_axis_tvalid
+ .m_axis_tready(axis_txread_data.ready), // input wire m_axis_tready
+ .m_axis_tdata(axis_txread_data.data), // output wire [511 : 0] m_axis_tdata
+ .m_axis_tkeep(axis_txread_data.keep), // output wire [63 : 0] m_axis_tkeep
+ .m_axis_tlast(axis_txread_data.last) // output wire m_axis_tlast
+);
+
+axis_256_to_512_converter tcp_txwrite_data_converter (
+ .aclk(net_clk), // input wire aclk
+ .aresetn(net_aresetn), // input wire aresetn
+ .s_axis_tvalid(axis_txwrite_data.valid), // input wire s_axis_tvalid
+ .s_axis_tready(axis_txwrite_data.ready), // output wire s_axis_tready
+ .s_axis_tdata(axis_txwrite_data.data), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(axis_txwrite_data.keep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(axis_txwrite_data.last), // input wire s_axis_tlast
+ .s_axis_tdest(1'b0), // input wire s_axis_tlast
+ .m_axis_tvalid(m_axis_mem_write_data[ddrPortNetworkTx].valid), // output wire m_axis_tvalid
+ .m_axis_tready(m_axis_mem_write_data[ddrPortNetworkTx].ready), // input wire m_axis_tready
+ .m_axis_tdata(m_axis_mem_write_data[ddrPortNetworkTx].data), // output wire [511 : 0] m_axis_tdata
+ .m_axis_tkeep(m_axis_mem_write_data[ddrPortNetworkTx].keep), // output wire [63 : 0] m_axis_tkeep
+ .m_axis_tlast(m_axis_mem_write_data[ddrPortNetworkTx].last), // output wire m_axis_tlast
+ .m_axis_tdest() // output wire m_axis_tlast
+);
+end
if (WIDTH==512) begin
//TCP Data Path
assign axis_rxread_data.valid = s_axis_mem_read_data[ddrPortNetworkRx].valid;
diff --git a/projects/network_stack.tcl b/projects/network_stack.tcl
index 9017eac76d6af8b71976b1e9c55187539e945b45..fb7fd4b9874a37bf3ce41839915e20e1be9b3320 100755
--- a/projects/network_stack.tcl
+++ b/projects/network_stack.tcl
@@ -51,6 +51,26 @@ set_property -dict [list CONFIG.C_NUM_SI_SLOTS {4} CONFIG.SWITCH_TDATA_NUM_BYTES
generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_4to1/axis_interconnect_4to1.xci]
update_compile_order -fileset sources_1
+create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_128_2to1 -dir $device_ip_dir
+set_property -dict [list CONFIG.C_NUM_SI_SLOTS {2} CONFIG.SWITCH_TDATA_NUM_BYTES {16} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {16} CONFIG.S00_AXIS_TDATA_NUM_BYTES {16} CONFIG.S01_AXIS_TDATA_NUM_BYTES {16} CONFIG.M00_S01_CONNECTIVITY {true}] [get_ips axis_interconnect_128_2to1]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_128_2to1/axis_interconnect_128_2to1.xci]
+update_compile_order -fileset sources_1
+
+create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_128_4to1 -dir $device_ip_dir
+set_property -dict [list CONFIG.C_NUM_SI_SLOTS {4} CONFIG.SWITCH_TDATA_NUM_BYTES {16} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_S02_AXIS_REG_CONFIG {1} CONFIG.C_S03_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {16} CONFIG.S00_AXIS_TDATA_NUM_BYTES {16} CONFIG.S01_AXIS_TDATA_NUM_BYTES {16} CONFIG.S02_AXIS_TDATA_NUM_BYTES {16} CONFIG.S03_AXIS_TDATA_NUM_BYTES {16} CONFIG.M00_S01_CONNECTIVITY {true} CONFIG.M00_S02_CONNECTIVITY {true} CONFIG.M00_S03_CONNECTIVITY {true}] [get_ips axis_interconnect_128_4to1]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_4to1/axis_interconnect_128_4to1.xci]
+update_compile_order -fileset sources_1
+
+create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_256_2to1 -dir $device_ip_dir
+set_property -dict [list CONFIG.C_NUM_SI_SLOTS {2} CONFIG.SWITCH_TDATA_NUM_BYTES {32} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {32} CONFIG.S00_AXIS_TDATA_NUM_BYTES {32} CONFIG.S01_AXIS_TDATA_NUM_BYTES {32} CONFIG.M00_S01_CONNECTIVITY {true}] [get_ips axis_interconnect_256_2to1]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_256_2to1/axis_interconnect_256_2to1.xci]
+update_compile_order -fileset sources_1
+
+create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_256_4to1 -dir $device_ip_dir
+set_property -dict [list CONFIG.C_NUM_SI_SLOTS {4} CONFIG.SWITCH_TDATA_NUM_BYTES {32} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_S02_AXIS_REG_CONFIG {1} CONFIG.C_S03_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {32} CONFIG.S00_AXIS_TDATA_NUM_BYTES {32} CONFIG.S01_AXIS_TDATA_NUM_BYTES {32} CONFIG.S02_AXIS_TDATA_NUM_BYTES {32} CONFIG.S03_AXIS_TDATA_NUM_BYTES {32} CONFIG.M00_S01_CONNECTIVITY {true} CONFIG.M00_S02_CONNECTIVITY {true} CONFIG.M00_S03_CONNECTIVITY {true}] [get_ips axis_interconnect_256_4to1]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_4to1/axis_interconnect_256_4to1.xci]
+update_compile_order -fileset sources_1
+
create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_512_2to1 -dir $device_ip_dir
set_property -dict [list CONFIG.C_NUM_SI_SLOTS {2} CONFIG.SWITCH_TDATA_NUM_BYTES {64} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {64} CONFIG.S00_AXIS_TDATA_NUM_BYTES {64} CONFIG.S01_AXIS_TDATA_NUM_BYTES {64} CONFIG.M00_S01_CONNECTIVITY {true}] [get_ips axis_interconnect_512_2to1]
generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_512_2to1/axis_interconnect_512_2to1.xci]
@@ -61,7 +81,6 @@ set_property -dict [list CONFIG.C_NUM_SI_SLOTS {4} CONFIG.SWITCH_TDATA_NUM_BYTES
generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_4to1/axis_interconnect_512_4to1.xci]
update_compile_order -fileset sources_1
-
#Data Width Converter
create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_64_to_512_converter -dir $device_ip_dir
@@ -74,6 +93,35 @@ set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {64} CONFIG.M_TDATA_NUM_BYTES
generate_target {instantiation_template} [get_files $device_ip_dir/axis_512_to_64_converter/axis_512_to_64_converter.xci]
update_compile_order -fileset sources_1
+create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_128_to_512_converter -dir $device_ip_dir
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {16} CONFIG.M_TDATA_NUM_BYTES {64} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1} CONFIG.TDEST_WIDTH {1} CONFIG.Component_Name {axis_128_to_512_converter}] [get_ips axis_128_to_512_converter]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_128_to_512_converter/axis_128_to_512_converter.xci]
+update_compile_order -fileset sources_1
+
+create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_512_to_128_converter -dir $device_ip_dir
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {64} CONFIG.M_TDATA_NUM_BYTES {16} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1} CONFIG.Component_Name {axis_512_to_128_converter}] [get_ips axis_512_to_128_converter]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_512_to_128_converter/axis_512_to_128_converter.xci]
+update_compile_order -fileset sources_1
+
+create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_256_to_512_converter -dir $device_ip_dir
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {32} CONFIG.M_TDATA_NUM_BYTES {64} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1} CONFIG.TDEST_WIDTH {1} CONFIG.Component_Name {axis_256_to_512_converter}] [get_ips axis_256_to_512_converter]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_256_to_512_converter/axis_256_to_512_converter.xci]
+update_compile_order -fileset sources_1
+
+create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_512_to_256_converter -dir $device_ip_dir
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {64} CONFIG.M_TDATA_NUM_BYTES {32} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1} CONFIG.Component_Name {axis_512_to_256_converter}] [get_ips axis_512_to_256_converter]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_512_to_256_converter/axis_512_to_256_converter.xci]
+update_compile_order -fileset sources_1
+
+create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_64_to_128_converter -dir $device_ip_dir
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {8} CONFIG.M_TDATA_NUM_BYTES {16} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1} CONFIG.TDEST_WIDTH {1} CONFIG.Component_Name {axis_64_to_128_converter}] [get_ips axis_64_to_128_converter]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_64_to_128_converter/axis_64_to_128_converter.xci]
+update_compile_order -fileset sources_1
+
+create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_64_to_256_converter -dir $device_ip_dir
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {8} CONFIG.M_TDATA_NUM_BYTES {32} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1} CONFIG.TDEST_WIDTH {1} CONFIG.Component_Name {axis_64_to_256_converter}] [get_ips axis_64_to_256_converter]
+generate_target {instantiation_template} [get_files $device_ip_dir/axis_64_to_256_converter/axis_64_to_256_converter.xci]
+update_compile_order -fileset sources_1
#HLS IP cores