From 1b8bd097c44eeb38be498ac2c7e72aaa9884b65c Mon Sep 17 00:00:00 2001
From: David Sidler <david.sidler@inf.ethz.ch>
Date: Fri, 21 Feb 2020 23:06:04 -0800
Subject: [PATCH] change alignment of SIMD register write to 64B
---
hdl/common/network_controller.sv | 23 +++++++++--------------
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/hdl/common/network_controller.sv b/hdl/common/network_controller.sv
index 5c0043e..88eb82c 100644
--- a/hdl/common/network_controller.sv
+++ b/hdl/common/network_controller.sv
@@ -347,6 +347,7 @@ wire axis_legacy_merge_metadata_valid;
wire axis_legacy_merge_metadata_ready;
wire[159:0] axis_legacy_merge_metadata_data;
+
// Two-clock cmd_fifo: 2 stage synchronization
axis_data_fifo_160_cc cmd_fifo (
.s_axis_aclk (pcie_clk), // input wire s_axis_aresetn
@@ -693,7 +694,7 @@ begin
s_axim.bvalid <= 1'b0;
axis_by_tx_metadata_valid <= 1'b0;
- mmwriteAddr = (s_axim.awaddr[11:0] >> 5);
+ mmwriteAddr = (s_axim.awaddr[11:0] >> 6); //64B aligned addresses for AVX -> no alignment issues with PCIe 8x or 16x
if (s_axim.awvalid && s_axim.awready) begin
s_axim.awready <= 1'b0;
@@ -718,7 +719,7 @@ begin
GPIO_REG_POST: begin
// sw data is 32 bits aligned
- /* s_axim.wdata[31:0] -> op - sw: 8 bits
+ /* s_axim.wdata[31:0] -> op - sw: 32 bits
[63:32] -> qpn - sw: 32 bits
[127:64] -> originAddr - sw: 64 bits
[191:128] -> targetAddr - sw: 64 bits
@@ -732,20 +733,14 @@ begin
axis_by_tx_metadata_data[6:3] <= s_axim.wdata[35:32];
axis_by_tx_metadata_data[26:7] <= 0; // 20 bits
- // originAddr - use only 48 b from the sw, that last 2 bits are set to zero
- // [127:64]
- axis_by_tx_metadata_data[28:27] <= 0; // 2 bits
- axis_by_tx_metadata_data[74:29] <= s_axim.wdata[113:66];
+ // originAddr - use only 48 b from the sw [127:64]
+ axis_by_tx_metadata_data[74:27] <= s_axim.wdata[113:64];
- // targetAddr - use only 48 b from the sw, that last 2 bits are set to zero
- // [191:128]
- axis_by_tx_metadata_data[76:75] <= 0; // 2 bits
- axis_by_tx_metadata_data[122:77] <= s_axim.wdata[177:130];
+ // targetAddr - use only 48 b from the sw [191:128]
+ axis_by_tx_metadata_data[122:75] <= s_axim.wdata[177:128];
- // size
- // [255:192]
- axis_by_tx_metadata_data[125:123] <= 0; // 3 bits
- axis_by_tx_metadata_data[154:126] <= s_axim.wdata[223:195];
+ // size [255:192]
+ axis_by_tx_metadata_data[154:123] <= s_axim.wdata[223:192];
axis_by_tx_metadata_valid <= 1'b1;
s_axim.bvalid <= 1'b0;
--
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