diff --git a/decoder-configuration.k b/decoder-configuration.k index 58219f187ecf372d0a0abc0f6b8f918dbedcc446..c42bd340bdfd2d332d7ec88e04221171369fb39a 100644 --- a/decoder-configuration.k +++ b/decoder-configuration.k @@ -1,3 +1,5 @@ +requires "x86-syntax.k" // Really hoping for a better module system sometime soon. These should *not* depend on each other. + requires "registers.k" requires "categories.k" @@ -20,6 +22,7 @@ module DECODER-CONFIGURATION imports REGISTERS-SYNTAX imports DECODER-INTERFACE imports CATEGORIES-SYNTAX + imports X86-SYNTAX syntax Modes ::= "mode64" | "mode32" | "mode16" syntax K ::= "ResetDecoder" @@ -34,6 +37,7 @@ module DECODER-CONFIGURATION <decoderOriginalBuffer> .Ints </decoderOriginalBuffer> <prefixes> .Set </prefixes> <disassemblerOut> "" </disassemblerOut> + <decodedInstruction> $FakeInstruction </decodedInstruction> <suffix> "" </suffix> <ATTRIBUTES> .List </ATTRIBUTES> @@ -182,6 +186,7 @@ module DECODER-CONFIGURATION <prefixes> .Set </prefixes> <suffix> "" </suffix> <disassemblerOut> "" </disassemblerOut> + <decodedInstruction> $FakeInstruction </decodedInstruction> <ATTRIBUTES> .List </ATTRIBUTES> <OPERANDS> .List </OPERANDS> <CATEGORY> "CATEGORY_NO_CATEGORY" </CATEGORY> diff --git a/decoder.k b/decoder.k index 60fe9d731b35811cc464670fbff7bfd9ce17d8ec..dcd9cdff48b4080b540f5726e0497471f7a244f1 100644 --- a/decoder.k +++ b/decoder.k @@ -38,41 +38,12 @@ module DECODER imports X86-SYNTAX syntax K ::= "SetMode" | "DecodePrefixes" | "ScanForVEX" | "ScanForEVEX" | "ScanForOpcode" | "ScanForMODRM" | "ScanForSIB" | "Disassemble" | "OutputDisassembly" | "IncrementInstruction" - - syntax Int ::= IntModeFromSymbol(K) [function] - - rule IntModeFromSymbol(mode16) => 0 - rule IntModeFromSymbol(mode32) => 1 - rule IntModeFromSymbol(mode64) => 2 - - rule <k> SetMode => . ... </k> - <MODE> _ => IntModeFromSymbol(S) </MODE> - <SMODE> _ => IntModeFromSymbol(S2) </SMODE> - <mode> S </mode> - <smode> S2 </smode> + + syntax K ::= "DecodeSemantics" // TODO maybe, split the decoder out from the disassembler so different 'backends' like this can be swapped out with more modularity. syntax K ::= "ExitAtEnd" syntax K ::= InitDecoder(Int, Ints) - syntax Int ::= lengthInts(Ints) [function] - rule lengthInts(.Ints) => 0 - rule lengthInts(I Is) => 1 +Int lengthInts(Is) - - syntax Ints ::= reverseInts(Ints) [function] - syntax Ints ::= reverseIntsAux(Ints, Ints) [function] - - rule reverseInts(Is) => reverseIntsAux(Is, .Ints) - rule reverseIntsAux(I Is1, Is2) => reverseIntsAux(Is1, I Is2) - rule reverseIntsAux(.Ints, Is) => Is - - syntax Ints ::= padInts(Ints, Int) [function] - syntax Ints ::= padIntsAux(Ints, Int) [function] - - - rule padInts(Is, L) => reverseInts(padIntsAux(reverseInts(Is), L -Int lengthInts(Is))) - rule padIntsAux(Is, L) => 0 padIntsAux(Is, L -Int 1) requires L >Int 0 - rule padIntsAux(Is, 0) => Is - rule Decode(Addr:Int, Bytes:Ints) => ResetDecoder ~> InitDecoder(Addr, Bytes) ~> @@ -87,18 +58,29 @@ module DECODER OSZ_NONTERM ~> DynamicDecodeInstruction ~> Disassemble ~> + DecodeSemantics ~> OutputDisassembly rule <k> InitDecoder(A, B) => . ... </k> <decoderBuffer> _ => B </decoderBuffer> <instructionpointer> _ => A </instructionpointer> - rule <k> OutputDisassembly => DecodedInstruction(Q, S, INumOSZToOpcode(N, O -Int 1) .Operands) ... </k> + syntax Int ::= IntModeFromSymbol(K) [function] + + rule IntModeFromSymbol(mode16) => 0 + rule IntModeFromSymbol(mode32) => 1 + rule IntModeFromSymbol(mode64) => 2 + + rule <k> SetMode => . ... </k> + <MODE> _ => IntModeFromSymbol(S) </MODE> + <SMODE> _ => IntModeFromSymbol(S2) </SMODE> + <mode> S </mode> + <smode> S2 </smode> + + + rule <k> OutputDisassembly => DecodedInstruction(Q, S, I) ... </k> <ilen> Q </ilen> - <REP> R </REP> - <INUM> N </INUM> - <EOSZ> O </EOSZ> - <suffix> SF </suffix> + <decodedInstruction> I </decodedInstruction> <disassemblerOut> S </disassemblerOut> syntax K ::= "ResetREX" @@ -404,13 +386,6 @@ module DECODER syntax K ::= "VerifyEVEX" - syntax Int ::= CountInInts(Ints) [function] - rule CountInInts(.Ints) => 0 - rule CountInInts(I:Int Is) => 1 +Int CountInInts(Is) - -/* syntax Int ::= ComputePositionFromRemaining(Ints) [function] - rule ComputePositionFromRemaining(Is) => 14 -Int CountInInts(Is)*/ - rule <k> ScanForEVEXOpcode => VerifyEVEX ... </k> <dynamicDecoderBuffer> _ => I Is </dynamicDecoderBuffer> <decoderBuffer> I:Int Is:Ints => Is:Ints </decoderBuffer> @@ -1215,9 +1190,7 @@ module DECODER rule <k> WriteMemoryDisplacement => . ... </k> <DISPWIDTH> 0 </DISPWIDTH> - syntax K ::= "ChangeDispWidth" | "DoWriteDisplacement" - - + syntax K ::= "DoWriteDisplacement" syntax Int ::= ComputeScaledDisp(Int, Int, Int, Int) [function] // AVX512 instructions multiply disp by elementsize and nelem, but only if disp is width 8 rule ComputeScaledDisp(D, _, _, W) => D requires W =/=Int 8 @@ -1225,17 +1198,6 @@ module DECODER rule ComputeScaledDisp(D, _, 0, 8) => D // Should not happen rule ComputeScaledDisp(D, E, N, 8) => D *Int (E /Int 8) *Int N requires E =/=Int 0 andBool N =/=Int 0 - rule <k> WriteLiteralDisp ~> DoWriteDisplacement => . ... </k> - <disassemblerOut> S => S +String "0x" +String Base2String(ComputeScaledDisp(D, E, N, DW), 16) </disassemblerOut> - <BASE0> REG_INVALID </BASE0> - <INDEX> REG_INVALID </INDEX> - <DISP> D </DISP> - <ELEMENTSIZE> E </ELEMENTSIZE> - <NELEM> N </NELEM> - <DISPWIDTH> DW </DISPWIDTH> - <EASZ> 3 </EASZ> - requires DW <Int 0 andBool D >=Int 0 - rule <k> WriteLiteralDisp ~> DoWriteDisplacement => . ... </k> <disassemblerOut> S => S +String "0x" +String Base2String((1 <<Int 64) +Int ComputeScaledDisp(D, E, N, DW), 16) </disassemblerOut> <BASE0> REG_INVALID </BASE0> @@ -1398,7 +1360,7 @@ module DECODER rule ExtensionString(0, 1) => "" rule ExtensionString(I, 0) => "" - rule ExtendToWidth(I, W, C) => ExtensionString((W /Int 4) -Int lengthString(Base2String(I, 16)), C) +String Base2String(I, 16) ~> WritePrevString requires (8 dividesInt W) + rule ExtendToWidth(I, W, C) => ExtensionString((W /Int 4) -Int lengthString(Base2String(I, 16)), C) +String Base2String(I, 16) requires (8 dividesInt W) rule <k> S:String ~> WritePrevString => . ... </k> <disassemblerOut> S1 => S1 +String S </disassemblerOut> @@ -1431,18 +1393,18 @@ module DECODER rule <k> WriteImm0 => WriteImm0Unsigned ... </k> <IMM0SIGNED> 0 </IMM0SIGNED> - rule <k> WriteOperand(OperandMetadata(OPERAND_IMM0, _, _, _, _, _, _)) => WriteImm0 ... </k> + rule <k> WriteOperand(OperandMetadata(OPERAND_IMM0, _, _, _, _, _, _)) => WriteImm0 ~> WritePrevString ... </k> <disassemblerOut> S => S +String "$0x" </disassemblerOut> - rule <k> WriteOperand(OperandMetadata(OPERAND_IMM1, _, _, _, _, _, _)) => ExtendToWidth(I, 8, 0) ... </k> + rule <k> WriteOperand(OperandMetadata(OPERAND_IMM1, _, _, _, _, _, _)) => ExtendToWidth(I, 8, 0) ~> WritePrevString ... </k> <UIMM1> I </UIMM1> <disassemblerOut> S => S +String "$0x" </disassemblerOut> - rule <k> WriteOperand(OperandMetadata(OPERAND_PTR, _, _, _, _, _, _)) => ExtendToWidth(I, 64, 0) ... </k> + rule <k> WriteOperand(OperandMetadata(OPERAND_PTR, _, _, _, _, _, _)) => ExtendToWidth(I, 64, 0) ~> WritePrevString ... </k> <DISP> I </DISP> <mode> mode64 </mode> // This rule actually seems to be dead. No instruction that exists in 64 bit mode uses PTR operands. - rule <k> WriteOperand(OperandMetadata(OPERAND_PTR, _, _, _, _, _, _)) => ExtendToWidth(I, 32, 0) ... </k> + rule <k> WriteOperand(OperandMetadata(OPERAND_PTR, _, _, _, _, _, _)) => ExtendToWidth(I, 32, 0) ~> WritePrevString ... </k> <DISP> I </DISP> <mode> M </mode> requires M =/=K mode64 @@ -1457,7 +1419,7 @@ module DECODER rule RELBRModeBits(mode32) => 32 rule RELBRModeBits(mode16) => 16 - rule <k> WriteOperand(OperandMetadata(OPERAND_RELBR, _, _, _, _, _, _)) => ExtendToWidth((Ip +Int I +Int Q) &Int RELBRAddrMask(O), RELBRModeBits(M), 0) ... </k> // +1? + rule <k> WriteOperand(OperandMetadata(OPERAND_RELBR, _, _, _, _, _, _)) => ExtendToWidth((Ip +Int I +Int Q) &Int RELBRAddrMask(O), RELBRModeBits(M), 0) ~> WritePrevString ... </k> // +1? <decoderBuffer> Is </decoderBuffer> <ilen> Q </ilen> <disassemblerOut> S => S +String "0x" </disassemblerOut> @@ -1509,5 +1471,132 @@ module DECODER rule <k> DynamicDecodeInstruction ~> Disassemble ~> OutputDisassembly => ErrorNoDynamicRuleMatched ... </k> [owise] + syntax K ::= "DecodeOpcode" | "DecodeMPXPointer" | "StartDecodeOperands" + + rule DecodeSemantics => DecodeOpcode ~> DecodeMPXPointer ~> StartDecodeOperands + + rule <k> DecodeOpcode => . ... </k> + <decodedInstruction> _ => INumOSZToOpcode(N, S -Int 1) .Operands </decodedInstruction> + <INUM> N </INUM> + <EOSZ> S </EOSZ> + + + rule <k> DecodeMPXPointer => . ... </k> // TODO - The semantics don't support MPX yet. + + syntax K ::= DecodeOperands(List) | DecodeOperand(KItem) + + rule <k> StartDecodeOperands => DecodeOperands(ReverseList(L)) ... </k> + <OPERANDS> L </OPERANDS> + <ATTRIBUTES> S </ATTRIBUTES> + requires A_ATT_OPERAND_ORDER_EXCEPTION in S + + rule <k> StartDecodeOperands => DecodeOperands(L) ... </k> // We build this list in the reverse order from the normal disassembly because we prepend to the Operands List + <OPERANDS> L </OPERANDS> + <ATTRIBUTES> S </ATTRIBUTES> + requires notBool(A_ATT_OPERAND_ORDER_EXCEPTION in S) + + syntax K ::= "AppendLastOperand" + + rule <k> O:Operand ~> AppendLastOperand => . ... </k> + <decodedInstruction> Op:Opcode Os => Op O, Os </decodedInstruction> + + rule <k> DecodeOperands(ListItem(Op) L) => DecodeOperand(Op) ~> AppendLastOperand ~> DecodeOperands(L) ... </k> + + rule DecodeOperands(.List) => . + + syntax K ::= "DecodeMEM0" | "DecodeMEM1" | "DecodeAGEN" + + rule <k> DecodeOperand(OperandMetadata(OPERAND_MEM0, _, VIS, _, _, _, _)) => DecodeMEM0 ... </k> + <CATEGORY> C </CATEGORY> + requires VIS =/=K SUPPRESSED orBool C ==String "CATEGORY_STRINGOP" + + rule <k> DecodeOperand(OperandMetadata(OPERAND_MEM0, _, VIS, _, _, _, _)) => . </k> + <CATEGORY> C </CATEGORY> [owise] + + rule <k> DecodeMEM0 => DecodeMem(D, B, I, S) ... </k> + <DISP> D </DISP> + <BASE0> B </BASE0> + <INDEX> I </INDEX> + <SCALE> S </SCALE> + + rule <k> DecodeOperand(OperandMetadata(OPERAND_MEM1, _, VIS, _, _, _, _)) => DecodeMEM1 ... </k> + <CATEGORY> C </CATEGORY> + requires VIS =/=K SUPPRESSED orBool C ==String "CATEGORY_STRINGOP" + + rule <k> DecodeMEM1 => DecodeMem(0, B, REG_INVALID, 0) ... </k> + <BASE1> B </BASE1> + + rule <k> DecodeOperand(OperandMetadata(OPERAND_AGEN, _, VIS, _, _, _, _)) => DecodeAGEN ... </k> + + rule <k> DecodeOperand(_) ~> AppendLastOperand => . ... </k> [owise] // For tests + + rule <k> DecodeAGEN => DecodeMem(D, B, I, S) ... </k> // Actually basically the same as MEM0 I think. Going to put off changing this in case it really is this simple. + <DISP> D </DISP> + <BASE0> B </BASE0> + <INDEX> I </INDEX> + <SCALE> S </SCALE> + + syntax Mem ::= DecodeMem(Int, K, K, Int) [function] + + rule DecodeMem(D, REG_INVALID, REG_INVALID, _) => $D // TODO: This is wrong. We cannot use immediates as a form of absolute addressing. + rule DecodeMem(D:Int, REG_RIP, REG_INVALID, _) => D (%rip) // RIP *CANNOT* be used with an index register. + rule DecodeMem(D, B, REG_INVALID, S) => D ({DisassemblerRegisterToSemanticsRegister(B, false)}:>R64) requires B =/=K REG_RIP andBool B =/=K REG_INVALID + rule DecodeMem(D, REG_INVALID, I, S) => D (, {DisassemblerRegisterToSemanticsRegister(I, false)}:>R64, S) requires I =/=K REG_INVALID + rule DecodeMem(D, B, I, S) => D ({DisassemblerRegisterToSemanticsRegister(B, false)}:>R64, {DisassemblerRegisterToSemanticsRegister(I, false)}:>R64, S) [owise] + syntax K ::= "ConvertLastStringToImm" + + rule S:String ~> ConvertLastStringToImm => $ String2Base(S, 16) + + rule <k> DecodeOperand(OperandMetadata(OPERAND_IMM0, _, VIS, _, _, _, _)) => WriteImm0 ~> ConvertLastStringToImm ... </k> requires VIS =/=K SUPPRESSED + rule <k> DecodeOperand(OperandMetadata(OPERAND_IMM1, _, VIS, _, _, _, _)) => ExtendToWidth(I, 8, 0) ~> ConvertLastStringToImm ... </k> + <UIMM1> I </UIMM1> + requires VIS =/=K SUPPRESSED + + rule <k> DecodeOperand(OperandMetadata(NAME, _, SUPPRESSED, _, _, _, _)) ~> AppendLastOperand => . ... </k> + <CATEGORY> C </CATEGORY> + requires notBool((NAME ==K OPERAND_MEM0 orBool NAME ==K OPERAND_MEM1 orBool NAME ==K OPERAND_AGEN) andBool C ==String "CATEGORY_STRINGOP") + + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG0, false, VIS, _, _, _, _)) => DisassemblerRegisterToSemanticsRegister(R, VIS ==K IMPLICIT) ... </k> + <REG0> R </REG0> + requires VIS =/=K SUPPRESSED + + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG1, false, VIS, _, _, _, _)) => DisassemblerRegisterToSemanticsRegister(R, VIS ==K IMPLICIT) ... </k> + <REG1> R </REG1> + requires VIS =/=K SUPPRESSED + + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG0, true, _, _, _, _, _)) => . ... </k> // TODO: See disassembler section. I believe the semantics don't support this yet. + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG1, true, _, _, _, _, _)) => . ... </k> + + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG2, false, VIS, _, _, _, _)) => DisassemblerRegisterToSemanticsRegister(R, VIS ==K IMPLICIT) ... </k> + <REG2> R </REG2> + requires VIS =/=K SUPPRESSED + + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG3, false, VIS, _, _, _, _)) => DisassemblerRegisterToSemanticsRegister(R, VIS ==K IMPLICIT) ... </k> + <REG3> R </REG3> + requires VIS =/=K SUPPRESSED + + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG4, false, VIS, _, _, _, _)) => DisassemblerRegisterToSemanticsRegister(R, VIS ==K IMPLICIT) ... </k> + <REG4> R </REG4> + requires VIS =/=K SUPPRESSED + + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG5, false, VIS, _, _, _, _)) => DisassemblerRegisterToSemanticsRegister(R, VIS ==K IMPLICIT) ... </k> + <REG5> R </REG5> + requires VIS =/=K SUPPRESSED + + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG6, false, VIS, _, _, _, _)) => DisassemblerRegisterToSemanticsRegister(R, VIS ==K IMPLICIT) ... </k> + <REG6> R </REG6> + requires VIS =/=K SUPPRESSED + + rule <k> DecodeOperand(OperandMetadata(OPERAND_REG7, false, VIS, _, _, _, _)) => DisassemblerRegisterToSemanticsRegister(R, VIS ==K IMPLICIT) ... </k> + <REG7> R </REG7> + requires VIS =/=K SUPPRESSED + + rule <k> DecodeOperand(OperandMetadata(OPERAND_RELBR, _, _, _, _, _, _)) => ExtendToWidth((Ip +Int I +Int Q) &Int RELBRAddrMask(O), RELBRModeBits(M), 0) ~> ConvertLastStringToImm ... </k> // +1? + <decoderBuffer> Is </decoderBuffer> + <ilen> Q </ilen> + <instructionpointer> Ip </instructionpointer> + <DISP> I </DISP> + <EOSZ> O </EOSZ> + <mode> M </mode> endmodule diff --git a/generated_decoder_rules.k b/generated_decoder_rules.k index 8744e2f3b036b2d3c609a8b9a23c7a15dd5cd10c..ae515ecbdf88355a2fa9a1d2043ce5c8ea2dd5c8 100644 --- a/generated_decoder_rules.k +++ b/generated_decoder_rules.k @@ -10,14 +10,14 @@ syntax OperandVisibility ::= "SUPPRESSED" | "IMPLICIT" | "EXPLICIT" syntax OperandWidth ::= Int | "AUTO" | "VECTOR" | "SSZ" | "ASZ" syntax KResult ::= OperandWidth syntax KItem ::= OperandMetadata(KItem, Bool, OperandVisibility, KItem, OperandWidth, OperandWidth, OperandWidth) -syntax K ::= "OUTREGToBASE0" -rule <k> OUTREGToBASE0 => . ... </k> -<OUTREG> M </OUTREG> -<BASE0> _ => M </BASE0> syntax K ::= "OUTREGToSEG0" rule <k> OUTREGToSEG0 => . ... </k> <OUTREG> M </OUTREG> <SEG0> _ => M </SEG0> +syntax K ::= "OUTREGToBASE0" +rule <k> OUTREGToBASE0 => . ... </k> +<OUTREG> M </OUTREG> +<BASE0> _ => M </BASE0> syntax K ::= "OUTREGToINDEX" rule <k> OUTREGToINDEX => . ... </k> <OUTREG> M </OUTREG> @@ -46,11 +46,11 @@ syntax K ::= "OUTREGToREG3" rule <k> OUTREGToREG3 => . ... </k> <OUTREG> M </OUTREG> <REG3> _ => M </REG3> -syntax KItem ::= "A_DOUBLE_WIDE_OUTPUT" | "A_INDEX_REG_IS_POINTER" | "A_SPECIAL_AGEN_REQUIRED" | "A_ATT_OPERAND_ORDER_EXCEPTION" | "A_SCATTER" | "A_DISP8_TUPLE4" | "A_DISP8_GPR_WRITER_LDOP_D" | "A_DISP8_TUPLE2" | "A_GATHER" | "A_AMDONLY" | "A_REQUIRES_ALIGNMENT" | "A_MXCSR_RD" | "A_HLE_REL_ABLE" | "A_LOCKABLE" | "A_NOTSX_COND" | "A_SKIPLOW64" | "A_DISP8_GPR_READER_WORD" | "A_MEMORY_FAULT_SUPPRESSION" | "A_DISP8_TUPLE1_WORD" | "A_DISP8_GSCAT" | "A_maskop" | "A_PREFETCH" | "A_DWORD_INDICES" | "A_QWORD_INDICES" | "A_HLE_ACQ_ABLE" | "A_NO_RIP_REL" | "A_DISP8_HALF" | "A_PROTECTED_MODE" | "A_EXCEPTION_BR" | "A_X87_CONTROL" | "A_xmm_state_r" | "A_DISP8_FULL" | "A_DISP8_SCALAR" | "A_INDIRECT_BRANCH" | "A_HALF_WIDE_OUTPUT" | "A_FAR_XFER" | "A_IMPLICIT_ONE" | "A_DISP8_FULLMEM" | "A_DISP8_EIGHTHMEM" | "A_x87_mmx_state_w" | "A_DISP8_GPR_READER" | "A_DISP8_GPR_WRITER_STORE" | "A_DISP8_GPR_WRITER_LDOP_Q" | "A_NOP" | "A_NONTEMPORAL" | "A_ELEMENT_SIZE_d" | "A_MASK_AS_CONTROL" | "A_RING0" | "A_MULTISOURCE4" | "A_DISP8_MOVDDUP" | "A_BROADCAST_ENABLED" | "A_NOTSX" | "A_KMASK" | "A_x87_mmx_state_r" | "A_xmm_state_w" | "A_xmm_state_cw" | "A_MASKOP_EVEX" | "A_MASK_VARIABLE_MEMOP" | "A_DISP8_MEM128" | "A_DISP8_GPR_WRITER_STORE_BYTE" | "A_MPX_PREFIX_ABLE" | "A_gather" | "A_x87_mmx_state_cw" | "A_DISP8_GPR_WRITER_STORE_WORD" | "A_DISP8_QUARTERMEM" | "A_BYTEOP" | "A_MXCSR" | "A_fixed_base0" | "A_DISP8_TUPLE1_BYTE" | "A_MMX_EXCEPT" | "A_DISP8_GPR_READER_BYTE" | "A_SCALABLE" | "A_DISP8_TUPLE8" | "A_DISP8_TUPLE1" | "A_SKIPLOW32" | "A_simd_scalar" | "A_IGNORES_OSFXSR" | "A_DISP8_HALFMEM" | "A_LOCKED" | "A_ELEMENT_SIZE_q" | "A_DOUBLE_WIDE_MEMOP" | "A_X87_NOWAIT" | "A_SIMD_SCALAR" | "A_DISP8_TUPLE1_4X" | "A_REP" | "A_fixed_base1" -syntax KItem ::= "OPERAND_SEG0" | "OPERAND_IMM0" | "OPERAND_REG6" | "OPERAND_BCAST" | "OPERAND_RELBR" | "OPERAND_REG5" | "OPERAND_INDEX" | "OPERAND_SCALE" | "OPERAND_SEG1" | "OPERAND_REG8" | "OPERAND_MEM1" | "OPERAND_MEM0" | "OPERAND_AGEN" | "OPERAND_REG0" | "OPERAND_REG1" | "OPERAND_IMM1" | "OPERAND_REG2" | "OPERAND_PTR" | "OPERAND_REG3" | "OPERAND_REG7" | "OPERAND_BASE0" | "OPERAND_REG4" | "OPERAND_BASE1" +syntax KItem ::= "A_REQUIRES_ALIGNMENT" | "A_maskop" | "A_DISP8_FULL" | "A_x87_mmx_state_cw" | "A_MASK_AS_CONTROL" | "A_DISP8_TUPLE1_4X" | "A_DISP8_SCALAR" | "A_DISP8_HALF" | "A_gather" | "A_SCATTER" | "A_DISP8_FULLMEM" | "A_fixed_base1" | "A_MEMORY_FAULT_SUPPRESSION" | "A_DISP8_MEM128" | "A_SKIPLOW64" | "A_NO_RIP_REL" | "A_DISP8_GPR_READER" | "A_MASKOP_EVEX" | "A_DISP8_GSCAT" | "A_MULTISOURCE4" | "A_xmm_state_cw" | "A_LOCKABLE" | "A_ATT_OPERAND_ORDER_EXCEPTION" | "A_EXCEPTION_BR" | "A_DISP8_GPR_WRITER_LDOP_Q" | "A_AMDONLY" | "A_NOP" | "A_MXCSR" | "A_REP" | "A_SKIPLOW32" | "A_SIMD_SCALAR" | "A_ELEMENT_SIZE_q" | "A_DISP8_TUPLE1_WORD" | "A_DWORD_INDICES" | "A_NONTEMPORAL" | "A_SPECIAL_AGEN_REQUIRED" | "A_DISP8_QUARTERMEM" | "A_DISP8_EIGHTHMEM" | "A_DOUBLE_WIDE_MEMOP" | "A_PREFETCH" | "A_DISP8_GPR_READER_WORD" | "A_QWORD_INDICES" | "A_ELEMENT_SIZE_d" | "A_DISP8_TUPLE1" | "A_DISP8_TUPLE1_BYTE" | "A_xmm_state_r" | "A_FAR_XFER" | "A_DISP8_GPR_WRITER_STORE" | "A_xmm_state_w" | "A_INDIRECT_BRANCH" | "A_DISP8_MOVDDUP" | "A_DISP8_GPR_WRITER_LDOP_D" | "A_DISP8_TUPLE2" | "A_MMX_EXCEPT" | "A_HLE_ACQ_ABLE" | "A_MPX_PREFIX_ABLE" | "A_IGNORES_OSFXSR" | "A_KMASK" | "A_HALF_WIDE_OUTPUT" | "A_x87_mmx_state_w" | "A_MASK_VARIABLE_MEMOP" | "A_DISP8_GPR_READER_BYTE" | "A_X87_NOWAIT" | "A_GATHER" | "A_MXCSR_RD" | "A_IMPLICIT_ONE" | "A_PROTECTED_MODE" | "A_DISP8_TUPLE4" | "A_X87_CONTROL" | "A_fixed_base0" | "A_x87_mmx_state_r" | "A_NOTSX" | "A_BROADCAST_ENABLED" | "A_DISP8_HALFMEM" | "A_HLE_REL_ABLE" | "A_BYTEOP" | "A_DOUBLE_WIDE_OUTPUT" | "A_simd_scalar" | "A_RING0" | "A_NOTSX_COND" | "A_LOCKED" | "A_INDEX_REG_IS_POINTER" | "A_DISP8_GPR_WRITER_STORE_WORD" | "A_SCALABLE" | "A_DISP8_GPR_WRITER_STORE_BYTE" | "A_DISP8_TUPLE8" +syntax KItem ::= "OPERAND_REG5" | "OPERAND_AGEN" | "OPERAND_BASE0" | "OPERAND_REG1" | "OPERAND_BCAST" | "OPERAND_RELBR" | "OPERAND_IMM1" | "OPERAND_REG8" | "OPERAND_IMM0" | "OPERAND_REG2" | "OPERAND_SEG1" | "OPERAND_SEG0" | "OPERAND_REG3" | "OPERAND_BASE1" | "OPERAND_MEM1" | "OPERAND_REG0" | "OPERAND_PTR" | "OPERAND_REG6" | "OPERAND_REG7" | "OPERAND_INDEX" | "OPERAND_REG4" | "OPERAND_SCALE" | "OPERAND_MEM0" syntax KItem ::= "xed_bits_t" | "xed_reg_enum_t" syntax K ::= "DynamicDecodeInstruction" -syntax IClass ::= "VFMADDSUBPS" | "PUNPCKHDQ" | "VZEROUPPER" | "HSUBPS" | "GETSEC" | "FSTP" | "RDSSPD" | "PSRLDQ" | "SCASD" | "PADDQ" | "UD0" | "VPMULHRSW" | "BEXTR" | "FNOP" | "VMOVHPS" | "MAXPD" | "KANDNB" | "FLDENV" | "CVTSD2SS" | "VPACKSSWB" | "PMOVZXWD" | "VPMINSD" | "FDIVRP" | "WRGSBASE" | "VPEXTRD" | "LDS" | "VEXPANDPS" | "VPTERNLOGD" | "VPUNPCKHWD" | "VCVTPS2PH" | "ENDBR32" | "VPERM2F128" | "FNSTSW" | "CMOVNL" | "VSCATTERDPS" | "PUNPCKHQDQ" | "MULPS" | "ORPD" | "PEXTRW_SSE4" | "VFIXUPIMMPS" | "CMOVBE" | "VPMAXUD" | "VCVTPH2PS" | "VFMADDPD" | "VFRCZSS" | "ADC" | "VPADDUSW" | "VPSCATTERDD" | "VSHUFPS" | "VMOVLHPS" | "MOVLPS" | "IRETD" | "VPMOVB2M" | "FCMOVBE" | "SFENCE" | "FXRSTOR64" | "UNPCKHPD" | "VHSUBPS" | "MAXSS" | "CLFLUSH" | "VFNMSUB132SS" | "VPSLLVD" | "FCMOVNE" | "LODSW" | "VPSUBSB" | "BNDMOV" | "VPERMQ" | "ADDSUBPD" | "VPMOVM2W" | "VPMOVMSKB" | "KORQ" | "SLDT" | "VPLZCNTQ" | "XTEST" | "VPANDD" | "INSW" | "FINCSTP" | "VINSERTI32X4" | "VPERMIL2PD" | "VMINSS" | "PMINUB" | "VMOVSHDUP" | "PFRSQIT1" | "VFNMADD132PD" | "ADOX" | "PEXTRQ" | "MOVMSKPD" | "PUNPCKLWD" | "BLCMSK" | "CLTS" | "VPAVGB" | "PFPNACC" | "NOT" | "VPROLD" | "FMULP" | "VMCLEAR" | "ROUNDSS" | "WRFSBASE" | "CLWB" | "MOVDQA" | "MOVSXD" | "PACKUSDW" | "VPHADDUBQ" | "SHLX" | "VPMACSSWD" | "VPCMPEQW" | "VPMULLW" | "VPANDND" | "AND" | "FISUBR" | "AESENC" | "VCMPSD" | "VFRCZPD" | "VPSUBB" | "VPSHLW" | "PSUBSB" | "CMPXCHG_LOCK" | "NOP" | "CMPSB" | "PMOVSXBD" | "CVTPS2PI" | "VPERMPS" | "VSHUFI32X4" | "VEXTRACTI32X8" | "DIVSS" | "VCVTDQ2PD" | "RSQRTSS" | "RDMSR" | "VPXOR" | "FLDZ" | "VPBROADCASTQ" | "VPSRLVW" | "KANDND" | "VCVTSS2SI" | "VPERMILPD" | "VMOVDQA32" | "KORTESTW" | "FIADD" | "VPMACSSDQL" | "XOR" | "VDIVSS" | "MUL" | "CLFLUSHOPT" | "BTC_LOCK" | "VROUNDPS" | "PACKSSWB" | "RCPPS" | "PUNPCKLBW" | "VALIGNQ" | "BLSR" | "VFNMADDPD" | "MOVD" | "VPMAXUB" | "BLENDPS" | "VPMADD52LUQ" | "RET_FAR" | "VPERMD" | "STI" | "TPAUSE" | "CMOVNLE" | "RDPKRU" | "VPTESTMQ" | "VBROADCASTF32X2" | "FLDL2E" | "PSHUFB" | "VFNMADD132PS" | "ADD_LOCK" | "VMOVNTDQA" | "PEXTRD" | "VSHUFPD" | "CMC" | "BSWAP" | "VPHADDWQ" | "VPBROADCASTD" | "FSCALE" | "VPSIGNW" | "VRCP14SS" | "VSCALEFPS" | "RDTSC" | "VPTESTNMQ" | "VP4DPWSSD" | "VCOMISS" | "VPHADDBD" | "LWPVAL" | "PHSUBD" | "PUSHAD" | "FIDIVR" | "FUCOMPP" | "KORB" | "CQO" | "MASKMOVQ" | "VPUNPCKHBW" | "VCVTSI2SD" | "VUNPCKLPS" | "KSHIFTLD" | "VPMACSSWW" | "CMOVLE" | "JB" | "VGETMANTPS" | "REP_MOVSB" | "VPSLLVQ" | "VPMAXUQ" | "KTESTD" | "VFNMSUB213PD" | "SETZ" | "VPSHLD" | "WRPKRU" | "VPCOMPRESSB" | "VEXTRACTF32X4" | "CLC" | "VPSHUFHW" | "PADDB" | "VSCATTERPF1DPD" | "VPSHLDVD" | "VROUNDSS" | "CVTSI2SD" | "VFMADD231PD" | "VRSQRT14SD" | "FSUBRP" | "VFMSUBADD213PS" | "PDEP" | "INVLPG" | "VPSIGND" | "VXORPS" | "VPERMI2D" | "VPSHLB" | "FCMOVNB" | "AESKEYGENASSIST" | "KANDQ" | "VPHADDUDQ" | "VFMADDSUB132PD" | "GF2P8AFFINEINVQB" | "PSUBW" | "VMULPS" | "IMUL" | "VRSQRT14PD" | "JMP" | "VFMSUBPD" | "MAXPS" | "INTO" | "STOSW" | "STOSB" | "VFMADDSUB132PS" | "VPRORQ" | "VCOMPRESSPS" | "VPMACSSDQH" | "VAESDECLAST" | "FCMOVNBE" | "ANDN" | "VPMACSSDD" | "VCVTPS2DQ" | "VRNDSCALEPS" | "CMPXCHG16B" | "VINSERTI32X8" | "VPSRAD" | "PSLLDQ" | "VINSERTF32X8" | "VPBLENDW" | "MOVBE" | "VPCMOV" | "JL" | "PSIGND" | "PI2FW" | "PMOVSXBQ" | "VRSQRT28PD" | "PINSRW" | "VDIVPS" | "INCSSPQ" | "KSHIFTLB" | "REPE_CMPSW" | "VPADDSB" | "T1MSKC" | "PREFETCHWT1" | "VDPPS" | "VPEXPANDD" | "VPCOMUD" | "FIDIV" | "PACKSSDW" | "STD" | "VPCMPGTQ" | "VPEXTRB" | "PSIGNB" | "SALC" | "VCVTPS2UDQ" | "VPINSRD" | "VFMSUB213PD" | "SETSSBSY" | "KANDW" | "VFMADD231PS" | "VPSHLDVW" | "PADDUSB" | "VGATHERPF1QPS" | "PCONFIG" | "LEA" | "PMULHUW" | "RSM" | "VPMOVZXWQ" | "LFS" | "VPABSD" | "VFMSUB231PS" | "VPMASKMOVQ" | "VFMADD213PD" | "RDPID" | "CPUID" | "RDGSBASE" | "VPBROADCASTW" | "RCL" | "CVTSS2SD" | "PSLLD" | "REP_MOVSD" | "FADDP" | "VPERMI2PD" | "VXORPD" | "CDQE" | "PUSHA" | "PABSD" | "VPMINSQ" | "VERR" | "POR" | "SHUFPD" | "PFMIN" | "BLSI" | "VSCATTERPF0DPS" | "VMOVDQU" | "VPMACSWD" | "PSUBD" | "BNDCL" | "VPSHRDD" | "FNSAVE" | "JO" | "VPXORD" | "DPPS" | "MOVSW" | "VPMINUQ" | "KTESTQ" | "KTESTW" | "VFNMSUB213SD" | "XSAVEC" | "PCMPGTB" | "VCVTPS2UQQ" | "SAR" | "VPMOVUSDB" | "PHSUBSW" | "BLCS" | "VGETMANTSS" | "VPCMPEQQ" | "VUNPCKLPD" | "MOVMSKPS" | "REPE_CMPSB" | "VPEXTRW" | "VCVTPS2QQ" | "VPACKUSDW" | "PF2ID" | "VGATHERPF0DPD" | "FNINIT" | "VPSLLD" | "PSRAD" | "VGATHERPF1DPS" | "ADDSS" | "CMOVNZ" | "VPADDB" | "ADDPD" | "VUNPCKHPS" | "PFRCPIT2" | "VPMINUD" | "VEXTRACTI32X4" | "KXORD" | "AAD" | "DIVPS" | "VRCP14PS" | "PINSRQ" | "VFNMADD132SD" | "WRMSR" | "VANDNPS" | "VRSQRT14SS" | "VFMSUB213PS" | "VBROADCASTSS" | "FABS" | "VPTESTNMD" | "SYSCALL" | "VFNMSUB132PD" | "CMPSD" | "PREFETCHW" | "FSINCOS" | "MOVNTQ" | "MOVNTSD" | "VPORD" | "VADDPS" | "VBLENDVPS" | "TZMSK" | "VPOPCNTD" | "VCVTPD2QQ" | "CVTPI2PS" | "VPSLLDQ" | "BTR" | "VPGATHERDD" | "VPSHRDQ" | "XADD" | "VSCALEFSD" | "CMOVNBE" | "FSETPM287_NOP" | "VPDPWSSD" | "REPE_SCASB" | "VPBLENDMQ" | "VPMOVZXDQ" | "PMADDWD" | "VCVTTPS2QQ" | "PFMAX" | "VFMSUBADDPD" | "POPFD" | "PCMPEQQ" | "VCVTUQQ2PS" | "PAVGUSB" | "KXORW" | "PMINSB" | "VGETEXPPD" | "PINSRB" | "VSUBPS" | "FBLD" | "VRNDSCALESS" | "VPROTB" | "INC_LOCK" | "DEC" | "MOVDIR64B" | "PREFETCHT1" | "VLDDQU" | "VCVTSD2SI" | "XSAVES64" | "PMOVZXDQ" | "VMOVSD" | "DAA" | "VCVTUSI2SD" | "VPSRLQ" | "VPSLLQ" | "VPMOVSXBW" | "BLCFILL" | "VMRUN" | "VAESIMC" | "VUCOMISD" | "PUSHFD" | "SQRTPD" | "VPSHRDVW" | "VDPPD" | "ADDPS" | "SQRTSS" | "VPUNPCKLDQ" | "VPCOMPRESSD" | "VPINSRB" | "INSERTQ" | "LWPINS" | "PSUBQ" | "VEXTRACTI64X2" | "VFPCLASSSD" | "ANDNPS" | "PMULLD" | "KXNORD" | "PHMINPOSUW" | "VCVTTPS2DQ" | "VMCALL" | "VFNMSUB231PS" | "VFMSUBADD213PD" | "FISTP" | "VDBPSADBW" | "XSAVES" | "VANDPS" | "VFMADD132SS" | "VEXPANDPD" | "VROUNDPD" | "VPERMI2Q" | "VINSERTI64X2" | "VPCOMD" | "BTS" | "VPMOVSWB" | "VCMPPS" | "VCVTPS2PD" | "CMOVZ" | "VMOVDQA" | "PHADDSW" | "FISUB" | "VEXTRACTI128" | "VCOMISD" | "VPMULLD" | "VFNMADD231PD" | "VPUNPCKLWD" | "VPSUBQ" | "REPE_SCASD" | "PAUSE" | "ROL" | "INT3" | "SETNBE" | "VSUBSD" | "VSCATTERPF1DPS" | "TEST" | "FCHS" | "VFNMADDPS" | "ENCLV" | "VPMOVDW" | "JP" | "VPMACSDQH" | "VFMADDSS" | "VPMOVSQW" | "INVEPT" | "VPROTD" | "VMOVAPS" | "VAESENC" | "VPMAXSD" | "VFNMADDSS" | "VFMSUBADD132PD" | "VFNMADD213SS" | "ENCLU" | "EXTRQ" | "SCASW" | "CMPPS" | "VCVTTSD2USI" | "VFMSUBADD231PS" | "VGETMANTSD" | "DIV" | "VFMADD132SD" | "MOVUPS" | "XGETBV" | "VCVTUSI2SS" | "FFREE" | "BTS_LOCK" | "PSHUFD" | "UMWAIT" | "FLD" | "SHL" | "OUTSW" | "CMOVNO" | "VPMOVUSDW" | "VFNMSUBSS" | "FLD1" | "VPROTQ" | "FDIVP" | "PBLENDVB" | "PUNPCKLDQ" | "VPPERM" | "XRSTORS64" | "VCVTUQQ2PD" | "VEXTRACTPS" | "MOVSS" | "VMOVDDUP" | "PFSQRT" | "PFACC" | "BLSMSK" | "SYSRET" | "VPMINUB" | "PSHUFHW" | "UD1" | "PMAXUB" | "FENI8087_NOP" | "MOV" | "STOSD" | "VPSHAD" | "VPSUBUSB" | "CALL_NEAR" | "MOVNTPD" | "VPEXTRQ" | "KANDNQ" | "FCOM" | "VPSRAVQ" | "BSF" | "VCVTTSD2SI" | "SETNO" | "NEG" | "FST" | "KXNORB" | "VPCOMPRESSW" | "MOVDQU" | "VBROADCASTF32X8" | "CMOVS" | "REP_INSB" | "AAM" | "VSHUFF64X2" | "VMOVDQU32" | "FXCH" | "VPERMT2W" | "ADC_LOCK" | "KSHIFTLW" | "JNB" | "VPMOVSXBD" | "VPAVGW" | "STC" | "MOVQ" | "VPMOVM2B" | "VUCOMISS" | "BSR" | "MOVSQ" | "KANDNW" | "FDIV" | "REP_LODSD" | "MFENCE" | "PSIGNW" | "VPMADD52HUQ" | "INVD" | "OUTSB" | "SBB" | "KXNORW" | "VPAND" | "PADDW" | "VFMADDSD" | "BLENDPD" | "IN" | "VBLENDPD" | "VPMOVSDW" | "PEXTRW" | "VFMADDSUB231PD" | "REP_STOSQ" | "VGATHERQPS" | "LZCNT" | "XORPS" | "CLGI" | "VGF2P8AFFINEQB" | "WBINVD" | "SMSW" | "VPHADDSW" | "LSS" | "MOVQ2DQ" | "KADDD" | "VPHADDUWQ" | "REP_MOVSW" | "VFMADD213PS" | "MOVUPD" | "CVTTPS2PI" | "HSUBPD" | "PMADDUBSW" | "VFNMSUBPS" | "VPUNPCKHQDQ" | "REP_INSW" | "VPERMT2B" | "OR_LOCK" | "VSCATTERDPD" | "BNDCN" | "PFNACC" | "LODSB" | "WRSSD" | "VPROLVQ" | "EXTRACTPS" | "VPGATHERDQ" | "ENCLS" | "VBLENDVPD" | "VFNMSUB213PS" | "VPXORQ" | "SHLD" | "VSCALEFSS" | "VMAXPS" | "VGATHERDPS" | "MINPD" | "VPCMPEQD" | "VSHUFF32X4" | "VPMACSDD" | "VPSRAVD" | "PCMPESTRI" | "PMOVSXWD" | "FCOMP" | "VGF2P8AFFINEINVQB" | "FISTTP" | "VBROADCASTF64X4" | "VPSUBSW" | "PCMPISTRI" | "VCVTSS2SD" | "PMOVSXBW" | "PSRLQ" | "VPABSQ" | "SAVEPREVSSP" | "PHSUBW" | "AESDEC" | "LOOPNE" | "PSUBSW" | "BLENDVPS" | "VPMOVZXBD" | "VMOVD" | "DEC_LOCK" | "PMOVZXBW" | "MOVNTI" | "VFNMADD231SS" | "VEXTRACTF64X2" | "XLAT" | "UMONITOR" | "VMOVNTDQ" | "VMOVDQU64" | "VFMSUB231PD" | "KNOTW" | "FFREEP" | "VPSIGNB" | "PCMPISTRM" | "VPMAXSW" | "VPINSRW" | "VPACKSSDW" | "PUSHF" | "PMAXSW" | "BT" | "VFIXUPIMMSD" | "CVTSD2SI" | "VEXTRACTF32X8" | "VPSCATTERDQ" | "VPMOVZXBQ" | "VPSHAQ" | "SHR" | "AESENCLAST" | "PMOVZXWQ" | "VMOVAPD" | "VSTMXCSR" | "SAHF" | "VBLENDMPD" | "REP_STOSD" | "VSCATTERPF0QPD" | "FYL2X" | "VMOVMSKPD" | "SHRD" | "VCVTQQ2PS" | "DAS" | "PREFETCHNTA" | "VPCMPISTRI" | "SETNZ" | "REP_STOSB" | "VRCPSS" | "VFMADD213SS" | "VPERMI2PS" | "MOVNTSS" | "BNDSTX" | "BNDLDX" | "SUBPD" | "SQRTPS" | "VFMSUBSS" | "VPSRLDQ" | "SETB" | "REPNE_CMPSW" | "STOSQ" | "VFMSUBPS" | "VPMOVSDB" | "VSQRTPD" | "SGDT" | "VPBROADCASTMW2D" | "FPATAN" | "V4FNMADDPS" | "VCVTTPS2UDQ" | "REPNE_SCASW" | "SCASB" | "VPHADDUBW" | "VPBROADCASTMB2Q" | "VPSHLDW" | "PFMUL" | "VREDUCESD" | "KORTESTD" | "PCMPGTW" | "VUNPCKHPD" | "MOVSHDUP" | "LGDT" | "VPCOMW" | "PSRLD" | "VPSHRDW" | "VPMOVSXWD" | "CWDE" | "STR" | "VCVTPD2UQQ" | "VPSCATTERQQ" | "PMAXSB" | "FIMUL" | "VSCATTERPF0DPD" | "VPSRLD" | "VFNMADDSD" | "PSHUFLW" | "SETBE" | "VPMACSWW" | "VFNMADD213PD" | "INT" | "VFNMSUB231PD" | "VPRORD" | "BLCIC" | "VPHSUBDQ" | "SHA1NEXTE" | "FTST" | "VPHADDW" | "VCVTUDQ2PD" | "POPA" | "V4FMADDPS" | "BNDMK" | "ANDNPD" | "XSAVEOPT64" | "VPERMT2Q" | "VMPTRST" | "VSQRTSD" | "FLDL2T" | "VFPCLASSSS" | "VPMAXSB" | "PCMPEQW" | "CMPSD_XMM" | "RDPMC" | "PINSRD" | "SUB" | "SETS" | "VEXTRACTF64X4" | "FUCOMP" | "PTWRITE" | "VMOVSS" | "VCVTSI2SS" | "VPUNPCKLBW" | "OUTSD" | "VPROLQ" | "VPSHLDD" | "VPRORVD" | "VGATHERPF0QPD" | "SHA256MSG2" | "VHADDPS" | "PUSH" | "SETNB" | "ADDSUBPS" | "SETLE" | "VPERMIL2PS" | "RET_NEAR" | "VCVTTSS2SI" | "VBROADCASTI64X2" | "VGATHERQPD" | "CBW" | "VCVTTPD2DQ" | "VPROTW" | "FDISI8087_NOP" | "ENTER" | "VPHADDBQ" | "VGETMANTPD" | "LFENCE" | "CDQ" | "VPCMPGTD" | "REP_OUTSW" | "FXRSTOR" | "VRCP28SS" | "CLD" | "PMULHRW" | "KORD" | "VMOVUPS" | "VPINSRQ" | "SUB_LOCK" | "VSCATTERPF1QPS" | "CMPXCHG16B_LOCK" | "VPSRLVQ" | "REPNE_CMPSQ" | "VCVTSD2USI" | "PCMPESTRM" | "VPCOMUQ" | "VPANDN" | "VMINSD" | "VLDMXCSR" | "PF2IW" | "FXAM" | "IDIV" | "VPERMT2PS" | "VMOVHPD" | "MOVSX" | "VPSUBUSW" | "ORPS" | "PMULDQ" | "VGETEXPSS" | "VPALIGNR" | "VAESDEC" | "VPTESTNMW" | "XABORT" | "SETNLE" | "KUNPCKDQ" | "VMULPD" | "VPHADDD" | "VCVTTPD2UDQ" | "VPCONFLICTQ" | "XSAVEOPT" | "VRANGESD" | "VPCONFLICTD" | "VPTESTNMB" | "REP_OUTSB" | "MOVDDUP" | "VPMOVSXWQ" | "JLE" | "PMOVSXDQ" | "VPSHAB" | "VALIGND" | "VPOPCNTQ" | "VMAXSD" | "JMP_FAR" | "XADD_LOCK" | "FNSTCW" | "AESDECLAST" | "COMISS" | "VBROADCASTI32X8" | "MOVSLDUP" | "UCOMISD" | "REPE_SCASW" | "FLDCW" | "VP4DPWSSDS" | "PMULHW" | "SETNP" | "FICOM" | "ENDBR64" | "PMINSD" | "SHA1RNDS4" | "VPSADBW" | "VMOVMSKPS" | "MOVHPD" | "PEXTRB" | "VFPCLASSPD" | "FICOMP" | "VFPCLASSPS" | "VPSLLW" | "CLRSSBSY" | "VREDUCEPS" | "VPCMPESTRI" | "LDDQU" | "VRANGESS" | "VPTESTMW" | "VFMSUBADD231PD" | "JNO" | "VPMADCSSWD" | "PCMPEQB" | "VBROADCASTF64X2" | "CVTPS2DQ" | "REP_INSD" | "PFCPIT1" | "VPSRAVW" | "FADD" | "FRNDINT" | "VPMAXUW" | "VPHMINPOSUW" | "PCMPGTQ" | "LEAVE" | "SETP" | "VANDNPD" | "BTR_LOCK" | "VPMOVUSQB" | "VMAXSS" | "VPMULHW" | "CRC32" | "VPSHRDVQ" | "PREFETCH_RESERVED" | "VMOVLPD" | "PREFETCH_EXCLUSIVE" | "VCVTTPD2UQQ" | "VBROADCASTF128" | "LDMXCSR" | "VPMADCSWD" | "VRSQRTPS" | "LIDT" | "VINSERTF32X4" | "SWAPGS" | "PMINSW" | "FCOMPP" | "CVTTSD2SI" | "PMAXUD" | "VMINPD" | "XCHG" | "CALL_FAR" | "VPLZCNTD" | "VFNMADD231PS" | "XEND" | "VINSERTF64X2" | "VPANDNQ" | "CMPSW" | "GF2P8MULB" | "VRSQRTSS" | "SUBSD" | "VINSERTPS" | "WBNOINVD" | "FMUL" | "VPCMPUD" | "VFNMSUB132PS" | "SETL" | "VSQRTSS" | "VRSQRT28PS" | "PSRLW" | "VADDSD" | "VCVTSD2SS" | "SHUFPS" | "VINSERTI64X4" | "VPCLMULQDQ" | "VPMULTISHIFTQB" | "SYSRET_AMD" | "PREFETCHT0" | "WRUSSD" | "LLDT" | "VMPTRLD" | "MOVNTDQ" | "VRCP14SD" | "KSHIFTRD" | "CVTSI2SS" | "VRSQRT28SS" | "VPCMPEQB" | "FCMOVE" | "KNOTQ" | "CLI" | "JNBE" | "RDSEED" | "PAND" | "KANDD" | "XSAVEC64" | "VBROADCASTSD" | "MULPD" | "VMREAD" | "MOVHPS" | "AESIMC" | "VFMSUBADD132PS" | "IRETQ" | "PSUBB" | "VPEXPANDQ" | "VPSHUFD" | "XSAVE64" | "PABSB" | "AAS" | "VPGATHERQQ" | "VPMULHUW" | "XRSTORS" | "PSRAW" | "MOVSB" | "REP_LODSW" | "RDFSBASE" | "VFMADDSUB213PD" | "KMOVB" | "VCVTUDQ2PS" | "VGETEXPPS" | "VSUBSS" | "FDIVR" | "FXSAVE" | "VPMOVUSQD" | "VPSLLVW" | "VPMOVWB" | "VPERM2I128" | "VPMASKMOVD" | "SQRTSD" | "FCMOVNU" | "VMULSD" | "PUNPCKHBW" | "UNPCKLPD" | "CLDEMOTE" | "VPMOVZXBW" | "VFMADD213SD" | "FUCOM" | "FLDLG2" | "VFNMSUBSD" | "VFNMADD231SD" | "VMWRITE" | "PMOVMSKB" | "MPSADBW" | "VPADDD" | "VPSHLDVQ" | "VPHADDBW" | "VFNMSUB231SS" | "VPADDSW" | "CMPSS" | "KORW" | "VPCMPB" | "VSHUFI64X2" | "VPGATHERQD" | "VRANGEPS" | "XSETBV" | "VREDUCESS" | "CMOVO" | "POPCNT" | "VPSCATTERQD" | "VFMADD231SS" | "VPBLENDD" | "FLDLN2" | "PFADD" | "VTESTPS" | "ADDSD" | "BLSIC" | "VRCPPS" | "VMXON" | "VPMOVZXWD" | "BEXTR_XOP" | "SHA256MSG1" | "XOR_LOCK" | "VSCATTERPF0QPS" | "VPHSUBWD" | "AAA" | "MOVDIRI" | "VMOVDQU8" | "CVTTPD2PI" | "CVTSS2SI" | "VPMOVSQD" | "UNPCKLPS" | "VMASKMOVPS" | "VCVTPD2PS" | "PFRCP" | "JZ" | "VFIXUPIMMSS" | "LODSQ" | "VPERMT2D" | "VPMOVM2Q" | "KMOVQ" | "MAXSD" | "VMOVSLDUP" | "PUSHFQ" | "VPMOVUSQW" | "POP" | "SYSEXIT" | "VRNDSCALEPD" | "VPCOMQ" | "VPROLVD" | "SBB_LOCK" | "VORPD" | "VMINPS" | "VPCOMB" | "JNP" | "VPBROADCASTB" | "KXORQ" | "FCOMI" | "LSL" | "MOVZX" | "VBROADCASTI128" | "VMOVNTPS" | "VPERMI2W" | "PMINUW" | "REP_MOVSQ" | "MOVNTDQA" | "WRUSSQ" | "MONITOR" | "FXTRACT" | "LGS" | "NOT_LOCK" | "KUNPCKBW" | "VPCOMPRESSQ" | "VMMCALL" | "CVTPD2PS" | "PCMPGTD" | "MINSS" | "VPHSUBBW" | "RSQRTPS" | "KSHIFTLQ" | "PREFETCHT2" | "SHRX" | "MOVSD_XMM" | "FSUB" | "CMPXCHG8B" | "VPMOVQD" | "PEXT" | "VINSERTF64X4" | "MINSD" | "INC" | "PADDSW" | "XRSTOR64" | "CMOVP" | "VPERMPD" | "KADDB" | "SKINIT" | "FSTPNCE" | "VEXTRACTI64X4" | "VCVTQQ2PD" | "VCVTTPS2UQQ" | "STGI" | "RDSSPQ" | "VBLENDMPS" | "VORPS" | "REP_LODSB" | "VPMINSB" | "VBROADCASTI32X4" | "VPMOVQ2M" | "FUCOMI" | "FILD" | "VPOPCNTB" | "JBE" | "VPMOVM2D" | "LOOPE" | "FSQRT" | "VPBLENDMD" | "VPABSW" | "LES" | "VMASKMOVPD" | "JNZ" | "KNOTB" | "VFMSUB231SD" | "SCASQ" | "FCOMIP" | "VMSAVE" | "VPERMW" | "PHADDW" | "CMPXCHG" | "VFNMSUB213SS" | "VPSHAW" | "CWD" | "VCVTPD2DQ" | "VMOVLPS" | "CMOVNS" | "CVTDQ2PD" | "PADDUSW" | "REPNE_CMPSB" | "FPTAN" | "VAESENCLAST" | "VDIVSD" | "JNS" | "VADDSS" | "SLWPCB" | "MOVHLPS" | "INSERTPS" | "VPCMPESTRM" | "VPCOMUB" | "VFMADDSUBPD" | "KADDW" | "VSUBPD" | "VMXOFF" | "VFMSUB132PS" | "PMOVZXBD" | "CVTTPS2DQ" | "VSQRTPS" | "ARPL" | "VCVTSS2USI" | "VMOVDQU16" | "BTC" | "SETNL" | "VMLAUNCH" | "V4FMADDSS" | "REPNE_SCASB" | "VPERMB" | "CMOVNP" | "VFMSUBSD" | "VPANDQ" | "COMISD" | "VBROADCASTI64X4" | "VPERMI2B" | "REP_LODSQ" | "HADDPS" | "JS" | "NEG_LOCK" | "PXOR" | "HADDPD" | "VPERMILPS" | "KMOVW" | "VMOVNTPD" | "POPF" | "VPSHUFB" | "VFNMADD213PS" | "VRCP28PD" | "VANDPD" | "KXORB" | "CVTPI2PD" | "JNL" | "VFNMADD132SS" | "MOVLPD" | "RORX" | "VPCMPUQ" | "KUNPCKWD" | "JECXZ" | "PMOVSXWQ" | "GF2P8AFFINEQB" | "VADDSUBPS" | "PADDSB" | "CLZERO" | "VPSHUFLW" | "FBSTP" | "PI2FD" | "VRCP14PD" | "VCMPSS" | "VPADDW" | "VPADDUSB" | "VMOVUPD" | "VFMADD231SD" | "PABSW" | "MOVAPS" | "VRNDSCALESD" | "AND_LOCK" | "CVTTSS2SI" | "VPMOVQW" | "VDIVPD" | "VCVTPD2UDQ" | "INVLPGA" | "VPHADDWD" | "VPCMPISTRM" | "PSLLW" | "VPMADDUBSW" | "VAESKEYGENASSIST" | "SARX" | "VFMSUB132SS" | "VSCATTERPF1QPD" | "VFNMSUB132SD" | "VPMOVQB" | "XORPD" | "KTESTB" | "VPHADDUWD" | "PUNPCKLQDQ" | "VERW" | "ROUNDPS" | "LAR" | "VPUNPCKHDQ" | "VPMOVW2M" | "MASKMOVDQU" | "CLAC" | "VRSQRT28SD" | "VREDUCEPD" | "V4FNMADDSS" | "UD2" | "VPCMPUW" | "VZEROALL" | "VPCMPGTW" | "VCMPPD" | "VMFUNC" | "VMOVHLPS" | "CVTTPD2DQ" | "SHA256RNDS2" | "FYL2XP1" | "MOV_CR" | "SHA1MSG1" | "VPMOVDB" | "KANDB" | "JRCXZ" | "LLWPCB" | "FCMOVU" | "INCSSPD" | "SETO" | "PBLENDW" | "SYSENTER" | "FCMOVB" | "CMPXCHG8B_LOCK" | "VFMSUB231SS" | "VPMULLQ" | "CMOVB" | "SYSCALL_AMD" | "HLT" | "UNPCKHPS" | "FNCLEX" | "VPDPWSSDS" | "VINSERTF128" | "PSWAPD" | "VFNMSUBPD" | "MULX" | "KORTESTB" | "MOVNTPS" | "VADDPD" | "VPSHRDVD" | "BLENDVPD" | "RCPSS" | "RCR" | "STAC" | "VBROADCASTI32X2" | "VRSQRT14PS" | "INSD" | "REPNE_SCASD" | "PMAXUW" | "PCLMULQDQ" | "VGATHERPF1QPD" | "REPNE_CMPSD" | "MOV_DR" | "PSUBUSB" | "VEXP2PS" | "VMOVQ" | "OUT" | "CVTDQ2PS" | "LAHF" | "VPBLENDMB" | "VGETEXPSD" | "JCXZ" | "FRSTOR" | "CMPPD" | "CVTPD2DQ" | "VPDPBUSDS" | "CMOVL" | "VPSHUFBITQMB" | "DIVPD" | "FWAIT" | "PMULLW" | "PHADDD" | "VMLOAD" | "VRCP28SD" | "VPOPCNTW" | "VADDSUBPD" | "VPHADDUBD" | "PACKUSWB" | "VFMSUB213SD" | "EMMS" | "ROUNDSD" | "PFSUBR" | "LTR" | "BLCI" | "VFMADDPS" | "SUBSS" | "CMP" | "VPSHLDQ" | "CMOVNB" | "IRET" | "VPMINUW" | "FPREM1" | "KSHIFTRW" | "VPHSUBSW" | "INVVPID" | "DIVSD" | "VPCMPQ" | "VPBLENDMW" | "REPE_SCASQ" | "VEXTRACTF128" | "FIST" | "RDTSCP" | "KSHIFTRB" | "PMOVZXBQ" | "BOUND" | "FPREM" | "KADDQ" | "SETNS" | "VMULSS" | "VMOVDQA64" | "FNSTENV" | "VRCP28PS" | "VPUNPCKLQDQ" | "RDRAND" | "REPE_CMPSD" | "VPTESTMB" | "PSADBW" | "VFMADD132PD" | "PAVGB" | "VHSUBPD" | "VPMULUDQ" | "VMASKMOVDQU" | "PMULHRSW" | "VPMULDQ" | "VPMADDWD" | "FCOS" | "LMSW" | "VBROADCASTF32X4" | "REPNE_SCASQ" | "PMULUDQ" | "VPMOVUSWB" | "VPMINSW" | "VPACKUSWB" | "INVPCID" | "VPTEST" | "VMAXPD" | "VFNMADD213SD" | "REPE_CMPSQ" | "FSIN" | "UCOMISS" | "VMPSADBW" | "VFMADDSUB231PS" | "VGATHERPF0QPS" | "MULSD" | "WRSSQ" | "RSTORSSP" | "VPCMPW" | "VTESTPD" | "VFIXUPIMMPD" | "VPABSB" | "F2XM1" | "TZCNT" | "VPMACSDQL" | "PSLLQ" | "VPSUBW" | "VPSRLVD" | "VBLENDPS" | "VCVTDQ2PS" | "ADD" | "VPMAXSQ" | "MWAIT" | "SUBPS" | "VSCALEFPD" | "FLDPI" | "PMAXSD" | "VROUNDSD" | "ANDPD" | "FDECSTP" | "BLSFILL" | "VPSRAW" | "SIDT" | "VPTESTMD" | "CMPSQ" | "VPSHLQ" | "VRANGEPD" | "ANDPS" | "ROUNDPD" | "XRSTOR" | "MULSS" | "BZHI" | "ROR" | "KNOTD" | "INT1" | "VFMADDSUB213PS" | "VGATHERPF0DPS" | "VPMOVSQB" | "PALIGNR" | "BNDCU" | "VPADDQ" | "VPBLENDVB" | "VHADDPD" | "VCOMPRESSPD" | "PFSUB" | "VPTERNLOGQ" | "VSCATTERQPD" | "CVTPD2PI" | "POPAD" | "PFCMPGT" | "VFNMSUB231SD" | "VPHSUBD" | "REP_STOSW" | "PFCMPGE" | "VCVTTPD2QQ" | "MINPS" | "VPMOVSXDQ" | "VPORQ" | "VFMSUB213SS" | "VPHSUBW" | "PADDD" | "VPMOVSXBQ" | "VPCOMUW" | "VFMSUB132SD" | "VGF2P8MULB" | "VPSUBD" | "VPMOVD2M" | "VPCMPGTB" | "DPPD" | "PSHUFW" | "XBEGIN" | "MWAITX" | "VPSRAQ" | "KMOVD" | "VPDPBUSD" | "PFCMPEQ" | "KSHIFTRQ" | "FSUBP" | "PMINUD" | "VFRCZSD" | "MOVSD" | "SHA1MSG2" | "XSAVE" | "VPCMPD" | "MOVAPD" | "MOVLHPS" | "JNLE" | "VMRESUME" | "VFMSUBADDPS" | "STMXCSR" | "VPERMT2PD" | "PUNPCKHWD" | "FSUBR" | "VPSRLW" | "FXSAVE64" | "VPOR" | "PANDN" | "POPFQ" | "LOOP" | "VFRCZPS" | "VFMSUB132PD" | "MOVDQ2Q" | "VINSERTI128" | "PAVGW" | "LODSD" | "VEXP2PD" | "VPRORVQ" | "PTEST" | "VGATHERPF1DPD" | "CVTPS2PD" | "VSCATTERQPS" | "REP_OUTSD" | "VPEXTRW_C5" | "VPEXPANDW" | "MONITORX" | "VCVTTSS2USI" | "VFMADD132PS" | "INSB" | "VPCMPUB" | "KXNORQ" | "PCMPEQD" | "VGATHERDPD" | "FUCOMIP" | "VPEXPANDB" | "OR" | "FEMMS" | "PSUBUSW" | "ADCX" | "VPHADDDQ" | "KORTESTQ" +syntax IClass ::= "VSHUFI32X4" | "CVTTPD2DQ" | "XORPS" | "LFS" | "PFCPIT1" | "MOV_CR" | "VMOVSLDUP" | "PSIGND" | "REP_OUTSB" | "VCVTPD2DQ" | "MOVNTSS" | "POPF" | "VPMOVZXBQ" | "SWAPGS" | "VPMAXUW" | "FSIN" | "VCVTSD2USI" | "VPMOVQD" | "VPMOVZXWD" | "VPMOVUSDW" | "REP_MOVSQ" | "KSHIFTLD" | "REP_LODSD" | "PADDQ" | "GETSEC" | "PACKUSWB" | "REPNE_SCASW" | "BTR" | "PSHUFB" | "MOVMSKPD" | "PMOVZXWQ" | "VPMOVSDW" | "FLDLG2" | "PAUSE" | "SETNZ" | "KADDD" | "KANDNB" | "CVTTSD2SI" | "VGATHERPF0QPD" | "VPADDD" | "KSHIFTLQ" | "PREFETCHT0" | "VFNMSUB213SD" | "JMP" | "BLSFILL" | "VPGATHERDD" | "VPERMILPD" | "VPOPCNTW" | "VUCOMISD" | "VPMOVM2Q" | "SBB" | "FXRSTOR64" | "VINSERTI32X4" | "MASKMOVQ" | "PSWAPD" | "KNOTW" | "REPNE_CMPSB" | "SHLD" | "VFMADD213PS" | "RSQRTPS" | "VPMULLQ" | "VRANGESD" | "VPAVGB" | "MWAITX" | "VPBLENDMD" | "REP_MOVSB" | "GF2P8MULB" | "VPMOVM2W" | "WRMSR" | "SETNB" | "PSHUFHW" | "PCMPGTD" | "XOR" | "VGATHERPF1DPD" | "MOVSLDUP" | "VMOVAPS" | "VPMAXSD" | "VRCP14PS" | "SHRD" | "VFPCLASSSD" | "XLAT" | "KSHIFTRB" | "PSUBUSW" | "SETB" | "DPPS" | "VBROADCASTSS" | "FFREEP" | "VPSHUFD" | "PCMPISTRM" | "MOVUPD" | "KNOTD" | "FDIVRP" | "PF2ID" | "VPCOMW" | "VPSHAQ" | "FWAIT" | "VLDMXCSR" | "VMOVDDUP" | "RET_NEAR" | "VPMOVUSQD" | "VFNMADD213SD" | "VFPCLASSPS" | "FMUL" | "VPADDSW" | "VPMOVM2B" | "FLDZ" | "JLE" | "VPOR" | "VMULSS" | "VFMSUB231SD" | "FCOM" | "FSUBRP" | "PSUBB" | "VRNDSCALESS" | "XEND" | "VSTMXCSR" | "FABS" | "VFNMADDSD" | "FXRSTOR" | "VPXORD" | "FDECSTP" | "VPHMINPOSUW" | "CALL_FAR" | "VMOVLPS" | "VFIXUPIMMPD" | "VPMOVW2M" | "KORB" | "VSCATTERPF0QPD" | "VADDSD" | "LODSW" | "FLDENV" | "CLTS" | "VFNMADD213PS" | "VPSHAW" | "FLDCW" | "VPSLLVW" | "PFMAX" | "PCMPGTW" | "TZMSK" | "FSINCOS" | "ENCLU" | "MOVDIR64B" | "FPATAN" | "VCVTTSS2USI" | "VPCMPUD" | "DPPD" | "WRSSQ" | "VRSQRT14SD" | "JB" | "VCVTPH2PS" | "ANDPD" | "CMPXCHG16B_LOCK" | "PSLLD" | "VPMULLW" | "CVTDQ2PD" | "VFMADD231SS" | "STI" | "PMINSW" | "KANDW" | "MOVSB" | "VPHADDDQ" | "FNSAVE" | "MOVLPS" | "VPMOVUSQW" | "PHSUBW" | "SETO" | "MULSS" | "STC" | "VEXTRACTI64X4" | "PFNACC" | "VPSUBW" | "SETL" | "CPUID" | "FCOMPP" | "RDPMC" | "AESKEYGENASSIST" | "VPMINSB" | "VPSRLDQ" | "VPROLVQ" | "VPMADD52HUQ" | "VFMSUB132PS" | "VINSERTF64X4" | "PMULHW" | "VPHADDUWQ" | "VPACKSSWB" | "VUNPCKHPD" | "VPMACSWW" | "CVTPD2DQ" | "KXNORB" | "VCVTTSD2SI" | "VPBLENDD" | "IDIV" | "VPBROADCASTMW2D" | "VFMSUBPS" | "VMLAUNCH" | "MOVQ" | "RDTSCP" | "FCMOVNU" | "LMSW" | "LSS" | "VPCMPUQ" | "V4FMADDPS" | "FXSAVE" | "MAXSD" | "MOVSHDUP" | "VPMOVDB" | "CVTSI2SD" | "PSLLQ" | "KORTESTB" | "RDSSPQ" | "VGATHERPF0QPS" | "VPSRLVD" | "RDPID" | "VMLOAD" | "VPCOMQ" | "VMAXPD" | "PADDW" | "VTESTPD" | "VPDPWSSD" | "VPADDUSB" | "BZHI" | "VPMULDQ" | "VFNMADD132SS" | "LAHF" | "MOVNTDQA" | "VPUNPCKLBW" | "VPSADBW" | "CVTPS2PD" | "KANDQ" | "REPE_SCASD" | "VUNPCKLPS" | "SETLE" | "VPXOR" | "RORX" | "VCVTUSI2SS" | "VFMADD213PD" | "VPMULUDQ" | "VPMULHW" | "KORQ" | "CLZERO" | "VFMADD132SS" | "VPANDNQ" | "VPMOVZXDQ" | "FSETPM287_NOP" | "KUNPCKDQ" | "VMOVDQA32" | "NEG" | "MOV_DR" | "VCVTPD2UQQ" | "VPHADDUWD" | "VSCATTERPF0QPS" | "VPSRAW" | "MULX" | "VSUBPD" | "SETZ" | "LEA" | "POPFQ" | "VCVTTPD2UDQ" | "AAM" | "MOVSD" | "CMPXCHG8B" | "CLC" | "KTESTQ" | "VFMSUBADD231PS" | "VPHADDBW" | "PHADDSW" | "ADDPS" | "SCASQ" | "SHA256MSG1" | "MPSADBW" | "STOSB" | "VPMOVSDB" | "VSCATTERPF1DPS" | "VDPPD" | "SHA1MSG2" | "VSQRTPD" | "SQRTPD" | "POR" | "PCMPGTQ" | "VFMADDSUB213PS" | "DAA" | "VEXTRACTF64X4" | "VPSHUFBITQMB" | "OUTSD" | "CMOVLE" | "PUSHFQ" | "VPSCATTERQQ" | "PHADDD" | "VPDPWSSDS" | "ADDSUBPD" | "VFMADDPS" | "PEXTRQ" | "VPTESTNMB" | "RET_FAR" | "VPROLVD" | "VFNMSUBSS" | "PMULHUW" | "FSCALE" | "VPEXPANDD" | "BLSI" | "PMINUW" | "REPNE_CMPSW" | "MOVSW" | "ADDSUBPS" | "VMINPS" | "BLSR" | "UMWAIT" | "POPA" | "VMULSD" | "VFNMSUB132SS" | "JNZ" | "PDEP" | "VPTESTMD" | "VCOMPRESSPS" | "VRCPPS" | "UMONITOR" | "RDPKRU" | "PALIGNR" | "VMFUNC" | "VCVTPS2UDQ" | "EMMS" | "VPINSRQ" | "SETNL" | "KANDNQ" | "VPSUBD" | "VPMOVSXWQ" | "VCVTSD2SS" | "KTESTD" | "CMOVP" | "FADD" | "VUNPCKLPD" | "PMULLD" | "PAVGB" | "PMADDUBSW" | "VTESTPS" | "POPFD" | "REP_OUTSW" | "VFRCZSS" | "SGDT" | "VPHADDUBQ" | "VPBLENDVB" | "JNP" | "VPBROADCASTB" | "VRSQRT28SD" | "PMULHRW" | "FXSAVE64" | "MOVDQ2Q" | "IMUL" | "COMISD" | "VEXTRACTF128" | "VINSERTI128" | "LGDT" | "DEC" | "KXORQ" | "VPSLLD" | "PSHUFW" | "SHUFPD" | "UD1" | "CMOVO" | "VBROADCASTF64X2" | "PHSUBD" | "KNOTB" | "MOVSD_XMM" | "UCOMISD" | "VCVTTPD2DQ" | "PABSW" | "FADDP" | "PFMIN" | "SIDT" | "VHADDPS" | "VFMSUB231PS" | "VPABSQ" | "VPSCATTERDD" | "VPMASKMOVQ" | "VPSHLDD" | "AESDEC" | "VPRORQ" | "VPMOVUSQB" | "VPORQ" | "VROUNDPS" | "VCVTSI2SD" | "KXNORD" | "REPNE_SCASD" | "FCOMP" | "LES" | "VFMADDSUBPS" | "PFSUB" | "REPE_CMPSB" | "VPUNPCKLWD" | "VPOPCNTB" | "PREFETCHWT1" | "CMP" | "FYL2X" | "UD0" | "VPMINUB" | "VPSLLVD" | "STR" | "PHMINPOSUW" | "FPREM" | "STOSD" | "ENDBR32" | "SMSW" | "BLENDVPD" | "VBROADCASTI32X4" | "PUNPCKLQDQ" | "VMOVUPD" | "VFMSUB132SS" | "PSRLD" | "BLSIC" | "AESDECLAST" | "VPMAXUD" | "VROUNDSD" | "VPSRAVD" | "VRSQRT28PD" | "PTEST" | "VFNMADDPS" | "VPMOVZXBW" | "VCOMPRESSPD" | "HADDPS" | "PEXTRD" | "VFNMADDPD" | "MONITOR" | "VCMPPD" | "VPBROADCASTMB2Q" | "PUNPCKHQDQ" | "UNPCKLPD" | "FXAM" | "VFMADDSUB132PS" | "CVTPS2PI" | "TEST" | "PUNPCKHBW" | "VPSRLVQ" | "VPMOVUSWB" | "HSUBPS" | "VMOVDQU16" | "ENDBR64" | "MINPS" | "VSCATTERPF0DPD" | "VMOVNTDQ" | "ADOX" | "VPRORD" | "PCMPGTB" | "CVTSS2SI" | "VFNMADD231PS" | "FISUBR" | "FXCH" | "SYSCALL_AMD" | "PMINUD" | "VSCATTERDPD" | "CVTPI2PD" | "XADD" | "VMCALL" | "PCMPEQD" | "PUNPCKLWD" | "VFMSUBADDPD" | "VPSHLDQ" | "VMOVSD" | "VPERMI2W" | "CQO" | "MOVNTPS" | "VPABSD" | "VPBROADCASTW" | "VPSLLVQ" | "SUBSS" | "VPEXTRW_C5" | "VPINSRW" | "LGS" | "OR_LOCK" | "FSTPNCE" | "JNL" | "INC_LOCK" | "VPSHLB" | "VPHADDBQ" | "BLCS" | "F2XM1" | "AAA" | "VPUNPCKLDQ" | "VPSIGND" | "MOVUPS" | "ADCX" | "REPE_CMPSD" | "ANDNPD" | "JP" | "ROR" | "VPERMW" | "BSR" | "VPRORVD" | "ROUNDPD" | "CMPXCHG" | "VGATHERQPD" | "VCVTTPS2QQ" | "VPTESTNMQ" | "CMOVNZ" | "VPMULTISHIFTQB" | "PADDD" | "FUCOMP" | "JZ" | "VFMSUBADD213PS" | "FPTAN" | "DEC_LOCK" | "VBROADCASTSD" | "PUSHFD" | "BNDSTX" | "INVVPID" | "WRUSSQ" | "PBLENDW" | "VPCMPISTRM" | "VFRCZSD" | "VSCATTERDPS" | "REP_STOSW" | "MINSS" | "DAS" | "VHSUBPS" | "VUCOMISS" | "VPSUBSW" | "VRSQRT14PD" | "VPEXTRQ" | "VPMOVZXWQ" | "VPSRAVQ" | "VSUBSS" | "VFMADD132PD" | "V4FNMADDPS" | "AAD" | "SHR" | "PMOVZXBD" | "VPABSB" | "SUBSD" | "VPADDUSW" | "REPNE_SCASQ" | "VPORD" | "XGETBV" | "DIV" | "FLDL2T" | "FDIVP" | "REP_STOSD" | "VPMOVZXBD" | "PFRCPIT2" | "VPBLENDW" | "VCVTUQQ2PS" | "PSUBSW" | "XSAVE64" | "VPMADCSSWD" | "KANDB" | "VPSIGNB" | "VPCOMPRESSB" | "REP_STOSB" | "REP_LODSQ" | "SUB_LOCK" | "VMOVUPS" | "SYSCALL" | "VPROLD" | "BLCI" | "VPROTW" | "JO" | "VPALIGNR" | "VPMOVSXBW" | "VPMOVB2M" | "SCASB" | "VREDUCEPD" | "VPXORQ" | "PMOVZXWD" | "PMULLW" | "VPCMPEQD" | "VINSERTI64X4" | "SYSRET_AMD" | "VFNMSUB132SD" | "FNSTCW" | "VSCATTERPF1DPD" | "VFNMADD231PD" | "INVLPG" | "VPMACSWD" | "VEXTRACTPS" | "VPSHLDVW" | "HLT" | "VPROTD" | "VADDSS" | "LODSB" | "CDQ" | "VPERMIL2PD" | "HSUBPD" | "VPSHLDW" | "VSHUFPS" | "VEXTRACTF32X4" | "VMULPS" | "LOOPE" | "VPMOVSQD" | "VEXTRACTI32X4" | "VPCOMB" | "VMAXPS" | "JECXZ" | "VBROADCASTF64X4" | "PMADDWD" | "KMOVB" | "VRSQRTSS" | "VFNMADD132SD" | "PUSHAD" | "VPEXPANDQ" | "PCMPEQQ" | "CVTSD2SI" | "MOVLPD" | "VPTESTNMD" | "AESIMC" | "VMOVDQU8" | "VRNDSCALESD" | "VCVTPS2QQ" | "MOVAPD" | "XABORT" | "JNB" | "MOVDIRI" | "VPLZCNTD" | "VMOVQ" | "VRSQRT28SS" | "FTST" | "VPSRAQ" | "XSETBV" | "VFMADDSD" | "INVLPGA" | "PANDN" | "MOVLHPS" | "VCVTPS2PH" | "KORW" | "VPABSW" | "VMPTRST" | "PACKUSDW" | "PSUBW" | "PSUBSB" | "VPMAXSB" | "VPSLLDQ" | "FDIV" | "VBLENDMPD" | "VPMACSSWW" | "VAESENC" | "CMPSD" | "VPHADDWQ" | "MOVSS" | "VEXTRACTF32X8" | "MOVNTI" | "AAS" | "PSRLW" | "VSCALEFSS" | "PEXTRW" | "SQRTSS" | "PUNPCKHWD" | "VPERMD" | "VPCOMUD" | "VPMADCSWD" | "MASKMOVDQU" | "KUNPCKBW" | "SETBE" | "CVTTPD2PI" | "VMOVMSKPS" | "PMOVSXWD" | "VPADDQ" | "VFNMADD132PS" | "PSLLW" | "REP_INSD" | "KXORB" | "VCVTPD2PS" | "INCSSPQ" | "VPSHLW" | "KORTESTQ" | "PACKSSDW" | "VPCMPD" | "IRET" | "VPMOVUSDB" | "REP_LODSW" | "VCVTTPD2QQ" | "VPERMIL2PS" | "VINSERTF128" | "VPMINSQ" | "VPCOMUW" | "PSHUFD" | "SETNP" | "STD" | "VPOPCNTD" | "PI2FW" | "FIADD" | "MOVDDUP" | "SETSSBSY" | "PSRLQ" | "MAXPS" | "CVTSI2SS" | "KTESTB" | "LSL" | "VSUBPS" | "VSQRTPS" | "SCASD" | "FIDIVR" | "CMOVS" | "VPBROADCASTD" | "PCMPESTRM" | "SETP" | "VPERMILPS" | "BEXTR" | "VCVTPS2DQ" | "VPCOMPRESSQ" | "MOV" | "VCMPSS" | "PMULUDQ" | "VANDPS" | "TZCNT" | "VFNMSUBPS" | "VFMADDSUB213PD" | "KMOVD" | "SAHF" | "VPERMT2B" | "REP_MOVSD" | "VCVTPD2QQ" | "INVPCID" | "VGATHERDPD" | "VFMSUBADDPS" | "FIMUL" | "VBLENDPD" | "ROUNDSS" | "VMOVHLPS" | "VPINSRB" | "VFMADDSUB231PS" | "PCMPISTRI" | "VFNMSUB231PD" | "PHSUBSW" | "RCR" | "KMOVW" | "VPDPBUSD" | "XTEST" | "INTO" | "BNDMOV" | "MONITORX" | "PF2IW" | "PMINUB" | "VPGATHERQQ" | "VSCATTERQPS" | "VPBROADCASTQ" | "VPAND" | "FEMMS" | "VCVTSI2SS" | "FRNDINT" | "SALC" | "PXOR" | "VPHADDWD" | "JS" | "CLDEMOTE" | "VFMSUB231PD" | "VCVTTPS2UDQ" | "VGF2P8MULB" | "PMULHRSW" | "VPERMI2Q" | "VSCATTERPF0DPS" | "VPEXTRD" | "CLI" | "MOVDQU" | "VFNMADD132PD" | "CALL_NEAR" | "FFREE" | "PFPNACC" | "PMOVSXBD" | "VFMSUBSD" | "AND" | "PINSRB" | "VEXP2PD" | "FICOM" | "VPCMPGTQ" | "VPINSRD" | "VPDPBUSDS" | "SYSRET" | "VGETEXPSS" | "BOUND" | "ARPL" | "CMOVB" | "VPUNPCKLQDQ" | "VRSQRT14SS" | "VCVTTPS2UQQ" | "VPMOVQ2M" | "CRC32" | "MINPD" | "VFNMSUB231SS" | "INVEPT" | "VEXTRACTI64X2" | "VGETMANTSD" | "VERR" | "BT" | "SETNBE" | "FCOMIP" | "VPACKUSWB" | "OR" | "WRFSBASE" | "VPSRLQ" | "VROUNDPD" | "MOVHPS" | "VPROTQ" | "BEXTR_XOP" | "OUT" | "VPHADDBD" | "CVTPD2PS" | "SHA1RNDS4" | "VPMACSSDQH" | "VPROLQ" | "VPSUBUSB" | "FCOS" | "VMPSADBW" | "KUNPCKWD" | "VMREAD" | "PREFETCHT2" | "VFMADDSS" | "VPSHUFHW" | "VRCP14SD" | "VP4DPWSSDS" | "CLFLUSH" | "FCMOVNB" | "VFMSUB213SS" | "VSQRTSS" | "FISUB" | "CVTTSS2SI" | "VINSERTF32X8" | "VBROADCASTI32X8" | "VPPERM" | "SETS" | "VROUNDSS" | "VPMOVSXBD" | "INT3" | "ENTER" | "PSRAD" | "VPMOVSXBQ" | "JBE" | "JNBE" | "VFIXUPIMMPS" | "XSAVES64" | "VRANGESS" | "VFNMADD231SD" | "VPHADDSW" | "VPERM2F128" | "FCHS" | "VMOVHPD" | "VP4DPWSSD" | "REP_LODSB" | "VMOVNTDQA" | "VPERMB" | "VGETEXPPD" | "VBLENDVPS" | "SHA1MSG1" | "PUSH" | "VDBPSADBW" | "VCVTPS2UQQ" | "VINSERTF64X2" | "ROUNDSD" | "VPSHUFLW" | "PMINSD" | "MOVHPD" | "PCLMULQDQ" | "VPSCATTERDQ" | "CVTDQ2PS" | "VPMASKMOVD" | "PMOVSXDQ" | "VPSHLQ" | "PMAXUW" | "VPACKSSDW" | "V4FNMADDSS" | "VMOVMSKPD" | "KXNORW" | "VFNMADDSS" | "VFMSUBPD" | "VCVTTPD2UQQ" | "FBSTP" | "REPNE_CMPSD" | "ADD" | "CMPSS" | "VPANDN" | "VPMOVQW" | "VPCMPQ" | "VFNMADD231SS" | "VPANDND" | "PMULDQ" | "VPCMPUW" | "PSUBUSB" | "VPSRLVW" | "VPGATHERQD" | "VPERMQ" | "LDDQU" | "CLD" | "BTS" | "VPMOVSQW" | "PUNPCKHDQ" | "FSTP" | "DIVSS" | "VPMULLD" | "STOSW" | "CLWB" | "MULPS" | "PINSRD" | "PADDSB" | "VPSLLQ" | "VMAXSS" | "VFMSUB132SD" | "PINSRQ" | "VPSHLDVQ" | "ADDPD" | "LWPINS" | "FCMOVE" | "LTR" | "VRNDSCALEPD" | "VPADDW" | "XSAVEOPT64" | "LWPVAL" | "VRCP28SD" | "VSCATTERPF1QPD" | "VEXPANDPD" | "SHA256MSG2" | "VPMACSDQH" | "VPTERNLOGD" | "VMOVDQA64" | "VAESDEC" | "VRCP28PD" | "ROL" | "PMAXUB" | "RSQRTSS" | "VCVTQQ2PS" | "VPMOVM2D" | "VMOVSHDUP" | "KADDB" | "XRSTOR" | "VPMAXUB" | "VCVTTSD2USI" | "VRCP28PS" | "VPEXPANDW" | "VFMSUBSS" | "VERW" | "JRCXZ" | "VPANDQ" | "VGATHERPF1DPS" | "REPNE_CMPSQ" | "BLCMSK" | "VANDNPD" | "KORTESTD" | "CMPXCHG_LOCK" | "SETNS" | "SAR" | "VFMSUB213SD" | "KSHIFTRW" | "VINSERTI64X2" | "FINCSTP" | "PI2FD" | "NEG_LOCK" | "MOVZX" | "BSWAP" | "VPERMT2PS" | "PSRAW" | "SAVEPREVSSP" | "SHA1NEXTE" | "MOVSQ" | "XCHG" | "ENCLS" | "VPTERNLOGQ" | "JNO" | "ANDNPS" | "FSUBP" | "VFMADD213SS" | "CMPSQ" | "VDPPS" | "FSUBR" | "REPNE_SCASB" | "VPHSUBWD" | "DIVPS" | "LLDT" | "XSAVEOPT" | "CLAC" | "PMOVSXBQ" | "FUCOMIP" | "DIVPD" | "VPHSUBW" | "VMOVD" | "POPCNT" | "CVTTPS2DQ" | "VBROADCASTI32X2" | "FMULP" | "FCMOVNBE" | "VPERMPD" | "VPSLLW" | "VSHUFPD" | "VPHSUBD" | "VPSUBUSW" | "NOT_LOCK" | "VGATHERQPS" | "VPERMPS" | "VREDUCESD" | "REP_STOSQ" | "FNSTSW" | "VEXTRACTI128" | "PAND" | "VCVTDQ2PS" | "VMINPD" | "VGF2P8AFFINEINVQB" | "VFNMSUBSD" | "ADDSD" | "BLENDPD" | "VPERMI2D" | "VFMSUBADD132PD" | "VFNMADD213PD" | "REPE_CMPSW" | "FYL2XP1" | "CMOVNS" | "VPCLMULQDQ" | "VCVTSS2USI" | "VMOVHPS" | "CWD" | "SUBPS" | "CMOVNBE" | "VGETEXPSD" | "WBINVD" | "VFNMSUB213PS" | "COMISS" | "PMINSB" | "VPMOVSXDQ" | "VORPD" | "FCMOVU" | "SLWPCB" | "MOVNTQ" | "VPMINUW" | "KTESTW" | "VPSHAD" | "VMOVDQU" | "VFMSUB132PD" | "PSHUFLW" | "VPSRLD" | "SARX" | "RDRAND" | "VUNPCKHPS" | "MAXPD" | "VPUNPCKHQDQ" | "IN" | "VMOVAPD" | "JL" | "PCMPEQW" | "FUCOMPP" | "FISTTP" | "JMP_FAR" | "VGATHERPF0DPD" | "VPMULHRSW" | "VFPCLASSPD" | "VPCMPGTW" | "VBLENDVPD" | "PADDUSB" | "REP_MOVSW" | "VPCMPEQW" | "VMASKMOVDQU" | "VFMADDSUBPD" | "PFADD" | "PCONFIG" | "VPERMT2W" | "PREFETCHT1" | "VINSERTI32X8" | "CMOVL" | "UCOMISS" | "PSRLDQ" | "CMPSW" | "PSIGNW" | "VADDPD" | "CMC" | "VPCONFLICTD" | "FCMOVBE" | "STMXCSR" | "KSHIFTRD" | "WBNOINVD" | "LDMXCSR" | "VPMADD52LUQ" | "PADDB" | "VRCP28SS" | "INT1" | "PUNPCKLDQ" | "RSM" | "MOVSX" | "WRPKRU" | "SETNO" | "VFMSUBADD132PS" | "VPCMPEQB" | "CVTTPS2PI" | "VPADDSB" | "VORPS" | "FPREM1" | "VPOPCNTQ" | "VMINSS" | "VCVTDQ2PD" | "VFPCLASSSS" | "VFNMADD213SS" | "VPMACSSDQL" | "SHLX" | "VPEXPANDB" | "VZEROUPPER" | "VMOVNTPD" | "SCASW" | "VFMADDPD" | "PEXT" | "XADD_LOCK" | "PFCMPGT" | "CMOVZ" | "FLDLN2" | "BLCIC" | "ORPS" | "NOT" | "CMPPD" | "VCVTPS2PD" | "BTS_LOCK" | "NOP" | "REPE_SCASW" | "VPHSUBBW" | "RDSEED" | "VPTEST" | "FICOMP" | "VGATHERPF1QPD" | "VBROADCASTI64X2" | "PSADBW" | "SHA256RNDS2" | "VMMCALL" | "VRSQRT14PS" | "PHADDW" | "SHRX" | "KADDW" | "SFENCE" | "LOOP" | "HADDPD" | "PMOVSXWQ" | "SHUFPS" | "PACKSSWB" | "INSD" | "VCVTTPS2DQ" | "CVTSS2SD" | "VPSUBB" | "VFMSUB231SS" | "FCOMI" | "PSIGNB" | "VFNMSUB213PD" | "LAR" | "FLD1" | "VFIXUPIMMSD" | "VPBLENDMB" | "VPMOVMSKB" | "VFMADDSUB132PD" | "CWDE" | "FUCOMI" | "VFMSUB213PS" | "VMULPD" | "VBROADCASTI128" | "VEXTRACTF64X2" | "MOVD" | "VALIGND" | "VCVTUSI2SD" | "VAESKEYGENASSIST" | "IRETQ" | "RDMSR" | "VRSQRTPS" | "VPCOMUB" | "VAESIMC" | "VPSRAD" | "PUSHA" | "VRCPSS" | "VMASKMOVPS" | "PABSD" | "PMOVZXDQ" | "UD2" | "CMOVNL" | "VRCP14SS" | "VGATHERPF1QPS" | "CBW" | "EXTRACTPS" | "XORPD" | "VMRESUME" | "VRANGEPD" | "VPHADDW" | "GF2P8AFFINEINVQB" | "VFMADD213SD" | "VREDUCEPS" | "BLENDVPS" | "VPMACSDQL" | "VMOVNTPS" | "VGF2P8AFFINEQB" | "MOVBE" | "MOVQ2DQ" | "CMPSD_XMM" | "SBB_LOCK" | "RDFSBASE" | "PCMPESTRI" | "WRSSD" | "VPMOVWB" | "VBROADCASTF32X2" | "INSERTPS" | "REP_INSW" | "PUNPCKLBW" | "VSCALEFPS" | "VPCMOV" | "PAVGUSB" | "VDIVPD" | "VPSCATTERQD" | "T1MSKC" | "PCMPEQB" | "VPSHRDVD" | "RSTORSSP" | "VANDNPS" | "VCOMISS" | "VCVTTSS2SI" | "OUTSB" | "CMPPS" | "MULPD" | "VINSERTF32X4" | "VMAXSD" | "XRSTOR64" | "VFIXUPIMMSS" | "LOOPNE" | "VPUNPCKHBW" | "FDISI8087_NOP" | "KORD" | "VPSIGNW" | "VPHADDUBD" | "VXORPS" | "VPCMPISTRI" | "VPSHUFB" | "CMPSB" | "RCPPS" | "VPAVGW" | "ADC" | "UNPCKHPS" | "VLDDQU" | "VFMADD132SD" | "VGETEXPPS" | "KORTESTW" | "REPE_CMPSQ" | "VMWRITE" | "PSUBD" | "VMXOFF" | "WRGSBASE" | "REPE_SCASB" | "JNS" | "PFCMPGE" | "VPUNPCKHDQ" | "VFMADD231PS" | "FNCLEX" | "VMCLEAR" | "FUCOM" | "VPMINUD" | "ORPD" | "INSW" | "MOVAPS" | "VFNMSUB213SS" | "BNDLDX" | "FLDPI" | "FDIVR" | "VPERM2I128" | "VPERMT2D" | "MWAIT" | "LDS" | "VPMAXSW" | "VPBLENDMQ" | "VPMAXUQ" | "UNPCKHPD" | "VCVTSD2SI" | "RDGSBASE" | "CMOVNLE" | "FCMOVNE" | "VPSHRDVW" | "KANDNW" | "FILD" | "JCXZ" | "VCVTQQ2PD" | "INCSSPD" | "INSERTQ" | "VCVTPD2UDQ" | "RDTSC" | "PFCMPEQ" | "VPMINSD" | "MFENCE" | "VADDSUBPD" | "SHL" | "FNSTENV" | "VCVTSS2SD" | "REP_OUTSD" | "MINSD" | "BTC_LOCK" | "VFNMSUB231PS" | "VBROADCASTF32X8" | "PMOVMSKB" | "PEXTRW_SSE4" | "VBROADCASTI64X4" | "PFMUL" | "VCVTUQQ2PD" | "VSHUFF64X2" | "LEAVE" | "VGATHERDPS" | "CLGI" | "FNINIT" | "VPHADDD" | "VPMOVDW" | "CDQE" | "SETNLE" | "DIVSD" | "VREDUCESS" | "LIDT" | "VGETMANTSS" | "FST" | "VPSHRDQ" | "CMOVNO" | "CVTPI2PS" | "VRSQRT28PS" | "VFMSUBADD213PD" | "XOR_LOCK" | "INC" | "VPROTB" | "VPTESTMB" | "VPMULHUW" | "CMPXCHG8B_LOCK" | "GF2P8AFFINEQB" | "RCPSS" | "VPMOVD2M" | "PMAXUD" | "VMINSD" | "XSAVEC" | "VPMINSW" | "REP_INSB" | "VPMACSSDD" | "VPSUBQ" | "FCMOVB" | "VSCATTERPF1QPS" | "VPSHLDVD" | "FENI8087_NOP" | "VPBLENDMW" | "VMOVSS" | "PFSQRT" | "KANDND" | "MULSD" | "MOVNTDQ" | "PUSHF" | "BNDCN" | "VPCOMUQ" | "VCOMISD" | "VMXON" | "INSB" | "STOSQ" | "VMOVDQU32" | "PBLENDVB" | "XRSTORS64" | "BTC" | "VFMADDSUB231PD" | "BNDCU" | "POPAD" | "PMAXSB" | "AESENCLAST" | "VMOVDQA" | "VPCMPW" | "KANDD" | "VPMOVSXWD" | "VMOVDQU64" | "FBLD" | "VPERMI2B" | "VHADDPD" | "VPHADDUDQ" | "V4FMADDSS" | "LODSQ" | "VGATHERPF0DPS" | "AND_LOCK" | "SUBPD" | "SLDT" | "SQRTPS" | "VPERMT2Q" | "VPADDB" | "VPMOVQB" | "STGI" | "PMOVSXBW" | "VFMADD231SD" | "VEXP2PS" | "VRNDSCALEPS" | "VPUNPCKHWD" | "FLDL2E" | "PFACC" | "PSLLDQ" | "VSQRTSD" | "FRSTOR" | "ADC_LOCK" | "VPRORVQ" | "LFENCE" | "VRCP14PD" | "VCVTSS2SI" | "INVD" | "KSHIFTRQ" | "VMASKMOVPD" | "VSUBSD" | "CVTPD2PI" | "BLENDPS" | "VFNMSUB231SD" | "KNOTQ" | "VPSRAVW" | "CVTSD2SS" | "LZCNT" | "VGETMANTPS" | "VPMACSSWD" | "PABSB" | "PTWRITE" | "VPANDD" | "VPCMPGTB" | "VPCMPESTRM" | "VPTESTNMW" | "BTR_LOCK" | "VSHUFI64X2" | "INT" | "MAXSS" | "EXTRQ" | "OUTSW" | "VINSERTPS" | "PADDSW" | "MOVDQA" | "VPSHRDW" | "VPMADDUBSW" | "IRETD" | "SKINIT" | "LODSD" | "VPMAXSQ" | "VSCALEFPD" | "VMPTRLD" | "MOVNTPD" | "VPGATHERDQ" | "VAESDECLAST" | "VSHUFF32X4" | "VRANGEPS" | "VPCOMPRESSW" | "VPCONFLICTQ" | "JNLE" | "VPEXTRW" | "PADDUSW" | "VFNMSUB132PD" | "PFRSQIT1" | "VADDPS" | "VFRCZPS" | "VPSUBSB" | "BNDCL" | "SYSENTER" | "SQRTSD" | "PINSRW" | "AESENC" | "KMOVQ" | "VCMPSD" | "VFMSUBADD231PD" | "REPE_SCASQ" | "BNDMK" | "VMOVLHPS" | "VPCMPESTRI" | "CMPXCHG16B" | "VBROADCASTF128" | "VBLENDPS" | "VPSHRDVQ" | "CLFLUSHOPT" | "VSCALEFSD" | "VPACKUSDW" | "RCL" | "PMOVZXBQ" | "TPAUSE" | "ROUNDPS" | "FIST" | "VBROADCASTF32X4" | "KXNORQ" | "ADDSS" | "BLCFILL" | "VPSHAB" | "VCMPPS" | "ANDPS" | "VPSHRDD" | "ENCLV" | "VPEXTRB" | "PREFETCHNTA" | "FSUB" | "VFNMSUB132PS" | "XBEGIN" | "PFRCP" | "KSHIFTLW" | "MOVMSKPS" | "CLRSSBSY" | "POP" | "MUL" | "VAESENCLAST" | "WRUSSD" | "VGETMANTPD" | "STAC" | "XSAVE" | "UNPCKLPS" | "ANDN" | "XRSTORS" | "VPMOVSWB" | "FXTRACT" | "VPHSUBSW" | "PMAXSW" | "FNOP" | "SYSEXIT" | "CMOVBE" | "VPMADDWD" | "CVTPS2DQ" | "VADDSUBPS" | "CMOVNP" | "VANDPD" | "FLD" | "VCVTUDQ2PD" | "SUB" | "PREFETCHW" | "VFMADD231PD" | "KXORD" | "VZEROALL" | "VPHADDUBW" | "FIDIV" | "VFNMSUBPD" | "PEXTRB" | "PREFETCH_RESERVED" | "PFSUBR" | "PAVGW" | "VPERMI2PS" | "VPSRLW" | "PREFETCH_EXCLUSIVE" | "BSF" | "VBLENDMPS" | "VPERMI2PD" | "VDIVSD" | "KADDQ" | "VPSHLD" | "VPCMPUB" | "VMOVLPD" | "VFMADD132PS" | "VHSUBPD" | "VMSAVE" | "VPTESTMW" | "VEXPANDPS" | "VPCMPB" | "LLWPCB" | "KSHIFTLB" | "XSAVEC64" | "PSUBQ" | "MOVHLPS" | "FSQRT" | "VFMSUB213PD" | "VPCMPEQQ" | "CMOVNB" | "VPHSUBDQ" | "PMAXSD" | "PMOVZXBW" | "VPCMPGTD" | "VDIVSS" | "VXORPD" | "MOVNTSD" | "BLSMSK" | "VPTESTMQ" | "VPLZCNTQ" | "VPERMT2PD" | "VDIVPS" | "VPMACSDD" | "VMRUN" | "ADD_LOCK" | "VPMOVSQB" | "VFRCZPD" | "KXORW" | "XSAVES" | "RDSSPD" | "VPMINUQ" | "VEXTRACTI32X8" | "VPCOMPRESSD" | "VALIGNQ" | "VCVTUDQ2PS" | "FISTP" | "MOVSXD" | "VPCOMD" | "VSCATTERQPD" // UNAME: rule <REG0> _ => REG_ST0 </REG0> <MEM0> _ => 1 </MEM0> @@ -129993,487 +129993,922 @@ rule <MEM0> _ => 1 </MEM0> requires I1 =/=Int 3 -syntax K ::= "REMOVE_SEGMENT" -rule <SEG0> _ => REG_INVALID </SEG0> -<k> REMOVE_SEGMENT => . ... </k> -<MODE> 0 </MODE> +syntax K ::= "BRANCH_HINT" +rule <k> BRANCH_HINT => . ... </k> +<HINT> 0 </HINT> -rule <SEG0> _ => REG_INVALID </SEG0> -<k> REMOVE_SEGMENT => . ... </k> -<MODE> 1 </MODE> +rule <HINT> 1 => 3 </HINT> +<k> BRANCH_HINT => . ... </k> -rule <SEG0> _ => REG_INVALID </SEG0> -<k> REMOVE_SEGMENT => . ... </k> -<MODE> 2 </MODE> +rule <HINT> 2 => 4 </HINT> +<k> BRANCH_HINT => . ... </k> -syntax K ::= "BRANCH_HINT" -rule <k> BRANCH_HINT => . ... </k> -<HINT> 0 </HINT> +syntax K ::= "DR_R" +rule <OUTREG> _ => REG_DR0 </OUTREG> +<k> DR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <HINT> 1 => 3 </HINT> -<k> BRANCH_HINT => . ... </k> +rule <OUTREG> _ => REG_DR1 </OUTREG> +<k> DR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <HINT> 2 => 4 </HINT> -<k> BRANCH_HINT => . ... </k> +rule <OUTREG> _ => REG_DR2 </OUTREG> +<k> DR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -syntax K ::= "ArAX" -rule <OUTREG> _ => REG_AX </OUTREG> -<k> ArAX => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_DR3 </OUTREG> +<k> DR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> ArAX => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_DR4 </OUTREG> +<k> DR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_RAX </OUTREG> -<k> ArAX => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_DR5 </OUTREG> +<k> DR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> -syntax K ::= "ArBX" -rule <OUTREG> _ => REG_BX </OUTREG> -<k> ArBX => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_DR6 </OUTREG> +<k> DR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> ArBX => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_DR7 </OUTREG> +<k> DR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <OUTREG> _ => REG_RBX </OUTREG> -<k> ArBX => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> DR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -syntax K ::= "ArCX" -rule <OUTREG> _ => REG_CX </OUTREG> -<k> ArCX => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> DR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> ArCX => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> DR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_RCX </OUTREG> -<k> ArCX => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> DR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -syntax K ::= "ArDX" -rule <OUTREG> _ => REG_DX </OUTREG> -<k> ArDX => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> DR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> ArDX => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> DR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_RDX </OUTREG> -<k> ArDX => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> DR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -syntax K ::= "ArSI" -rule <OUTREG> _ => REG_SI </OUTREG> -<k> ArSI => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> DR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> ArSI => . ... </k> -<EASZ> 2 </EASZ> +syntax K ::= "UISA_VSIB_INDEX_YMM" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <OUTREG> _ => REG_RSI </OUTREG> -<k> ArSI => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -syntax K ::= "ArDI" -rule <OUTREG> _ => REG_DI </OUTREG> -<k> ArDI => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> ArDI => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <OUTREG> _ => REG_RDI </OUTREG> -<k> ArDI => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> -syntax K ::= "ArSP" -rule <OUTREG> _ => REG_SP </OUTREG> -<k> ArSP => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> ArSP => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <OUTREG> _ => REG_RSP </OUTREG> -<k> ArSP => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 7 </SIBINDEX> -syntax K ::= "ArBP" -rule <OUTREG> _ => REG_BP </OUTREG> -<k> ArBP => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_YMM8 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> ArBP => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_YMM9 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <OUTREG> _ => REG_RBP </OUTREG> -<k> ArBP => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM10 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> -syntax K ::= "SrSP" -rule <OUTREG> _ => REG_SP </OUTREG> -<k> SrSP => . ... </k> -<SMODE> 0 </SMODE> +rule <OUTREG> _ => REG_YMM11 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> SrSP => . ... </k> -<SMODE> 1 </SMODE> +rule <OUTREG> _ => REG_YMM12 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <OUTREG> _ => REG_RSP </OUTREG> -<k> SrSP => . ... </k> -<SMODE> 2 </SMODE> +rule <OUTREG> _ => REG_YMM13 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> -syntax K ::= "SrBP" -rule <OUTREG> _ => REG_BP </OUTREG> -<k> SrBP => . ... </k> -<SMODE> 0 </SMODE> +rule <OUTREG> _ => REG_YMM14 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> SrBP => . ... </k> -<SMODE> 1 </SMODE> +rule <OUTREG> _ => REG_YMM15 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <OUTREG> _ => REG_RBP </OUTREG> -<k> SrBP => . ... </k> -<SMODE> 2 </SMODE> +rule <OUTREG> _ => REG_YMM16 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -syntax K ::= "Ar8" -rule <OUTREG> _ => REG_R8W </OUTREG> -<k> Ar8 => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_YMM17 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <OUTREG> _ => REG_R8D </OUTREG> -<k> Ar8 => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_YMM18 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <OUTREG> _ => REG_R8 </OUTREG> -<k> Ar8 => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM19 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -syntax K ::= "Ar9" -rule <OUTREG> _ => REG_R9W </OUTREG> -<k> Ar9 => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_YMM20 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <OUTREG> _ => REG_R9D </OUTREG> -<k> Ar9 => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_YMM21 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <OUTREG> _ => REG_R9 </OUTREG> -<k> Ar9 => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM22 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> -syntax K ::= "Ar10" -rule <OUTREG> _ => REG_R10W </OUTREG> -<k> Ar10 => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_YMM23 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <OUTREG> _ => REG_R10D </OUTREG> -<k> Ar10 => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_YMM24 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <OUTREG> _ => REG_R10 </OUTREG> -<k> Ar10 => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM25 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> -syntax K ::= "Ar11" -rule <OUTREG> _ => REG_R11W </OUTREG> -<k> Ar11 => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_YMM26 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <OUTREG> _ => REG_R11D </OUTREG> -<k> Ar11 => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_YMM27 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <OUTREG> _ => REG_R11 </OUTREG> -<k> Ar11 => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM28 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> -syntax K ::= "Ar12" -rule <OUTREG> _ => REG_R12W </OUTREG> -<k> Ar12 => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_YMM29 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <OUTREG> _ => REG_R12D </OUTREG> -<k> Ar12 => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_YMM30 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <OUTREG> _ => REG_R12 </OUTREG> -<k> Ar12 => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM31 </OUTREG> +<k> UISA_VSIB_INDEX_YMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> -syntax K ::= "Ar13" -rule <OUTREG> _ => REG_R13W </OUTREG> -<k> Ar13 => . ... </k> -<EASZ> 1 </EASZ> +syntax K ::= "ZMM_R3" +rule <k> ZMM_R3 => ZMM_R3_32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_R13D </OUTREG> -<k> Ar13 => . ... </k> -<EASZ> 2 </EASZ> +rule <k> ZMM_R3 => ZMM_R3_32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_R13 </OUTREG> -<k> Ar13 => . ... </k> -<EASZ> 3 </EASZ> +rule <k> ZMM_R3 => ZMM_R3_64 ... </k> +<MODE> 2 </MODE> -syntax K ::= "Ar14" -rule <OUTREG> _ => REG_R14W </OUTREG> -<k> Ar14 => . ... </k> -<EASZ> 1 </EASZ> +syntax K ::= "XMM_N3_64" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_R14D </OUTREG> -<k> Ar14 => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_R14 </OUTREG> -<k> Ar14 => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -syntax K ::= "Ar15" -rule <OUTREG> _ => REG_R15W </OUTREG> -<k> Ar15 => . ... </k> -<EASZ> 1 </EASZ> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_R15D </OUTREG> -<k> Ar15 => . ... </k> -<EASZ> 2 </EASZ> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <OUTREG> _ => REG_R15 </OUTREG> -<k> Ar15 => . ... </k> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -syntax K ::= "rIP" -rule <OUTREG> _ => REG_EIP </OUTREG> -<k> rIP => . ... </k> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM8 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM9 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM10 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM11 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM12 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM13 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM14 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM15 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM16 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM17 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM18 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM19 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM20 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM21 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM22 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM23 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM24 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM25 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM26 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM27 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM28 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM29 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM30 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> + + + +rule <OUTREG> _ => REG_XMM31 </OUTREG> +<k> XMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> + + + +syntax K ::= "NELEM_TUPLE1" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1 => . ... </k> +<VL> 0 </VL> + + + +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1 => . ... </k> +<VL> 1 </VL> + + + +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1 => . ... </k> +<VL> 2 </VL> + + + +syntax K ::= "FINAL_ESEG1" +rule <OUTREG> _ => REG_ES </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_ESEG1 => . ... </k> <MODE> 0 </MODE> -rule <OUTREG> _ => REG_EIP </OUTREG> -<k> rIP => . ... </k> +rule <OUTREG> _ => REG_ES </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_ESEG1 => . ... </k> <MODE> 1 </MODE> -rule <OUTREG> _ => REG_RIP </OUTREG> -<k> rIP => . ... </k> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_ESEG1 => . ... </k> <MODE> 2 </MODE> -syntax K ::= "rIPa" -rule <OUTREG> _ => REG_EIP </OUTREG> -<k> rIPa => . ... </k> -<EASZ> 2 </EASZ> +syntax K ::= "OVERRIDE_SEG0" +rule <k> OVERRIDE_SEG0 => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_RIP </OUTREG> -<k> rIPa => . ... </k> -<EASZ> 3 </EASZ> +rule <k> OVERRIDE_SEG0 => . ... </k> +<MODE> 1 </MODE> -syntax K ::= "OeAX" -rule <OUTREG> _ => REG_AX </OUTREG> -<k> OeAX => . ... </k> -<EOSZ> 1 </EOSZ> +rule <k> OVERRIDE_SEG0 => . ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> OeAX => . ... </k> -<EOSZ> 2 </EOSZ> +syntax K ::= "NELEM_TUPLE4" +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_TUPLE4 => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> OeAX => . ... </k> -<EOSZ> 3 </EOSZ> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_TUPLE4 => . ... </k> +<VL> 1 </VL> -syntax K ::= "OrAX" -rule <OUTREG> _ => REG_AX </OUTREG> -<k> OrAX => . ... </k> -<EOSZ> 1 </EOSZ> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_TUPLE4 => . ... </k> +<VL> 2 </VL> -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> OrAX => . ... </k> -<EOSZ> 2 </EOSZ> +syntax K ::= "NELEM_GPR_WRITER_STORE" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_STORE => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_RAX </OUTREG> -<k> OrAX => . ... </k> -<EOSZ> 3 </EOSZ> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_STORE => . ... </k> +<VL> 1 </VL> -syntax K ::= "OrDX" -rule <OUTREG> _ => REG_DX </OUTREG> -<k> OrDX => . ... </k> -<EOSZ> 1 </EOSZ> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_STORE => . ... </k> +<VL> 2 </VL> -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> OrDX => . ... </k> -<EOSZ> 2 </EOSZ> +syntax K ::= "VMODRM_XMM" +rule <k> VMODRM_XMM => VSIB_XMM ... </k> +<MOD> 0 </MOD> -rule <OUTREG> _ => REG_RDX </OUTREG> -<k> OrDX => . ... </k> -<EOSZ> 3 </EOSZ> +rule <k> VMODRM_XMM => VSIB_XMM ~> MEMDISP8 ... </k> +<MOD> 1 </MOD> -syntax K ::= "OrSP" -rule <OUTREG> _ => REG_SP </OUTREG> -<k> OrSP => . ... </k> +rule <k> VMODRM_XMM => VSIB_XMM ~> MEMDISP32 ... </k> +<MOD> 2 </MOD> + + + +syntax K ::= "XMM_B3_32" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_B3_32 => . ... </k> +<RM> 0 </RM> + + + +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_B3_32 => . ... </k> +<RM> 1 </RM> + + + +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_B3_32 => . ... </k> +<RM> 2 </RM> + + + +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_B3_32 => . ... </k> +<RM> 3 </RM> + + + +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_B3_32 => . ... </k> +<RM> 4 </RM> + + + +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_B3_32 => . ... </k> +<RM> 5 </RM> + + + +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_B3_32 => . ... </k> +<RM> 6 </RM> + + + +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_B3_32 => . ... </k> +<RM> 7 </RM> + + + +syntax K ::= "MASK_R" +rule <OUTREG> _ => REG_K0 </OUTREG> +<k> MASK_R => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 0 </REG> + + + +rule <OUTREG> _ => REG_K1 </OUTREG> +<k> MASK_R => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 1 </REG> + + + +rule <OUTREG> _ => REG_K2 </OUTREG> +<k> MASK_R => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 2 </REG> + + + +rule <OUTREG> _ => REG_K3 </OUTREG> +<k> MASK_R => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 3 </REG> + + + +rule <OUTREG> _ => REG_K4 </OUTREG> +<k> MASK_R => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 4 </REG> + + + +rule <OUTREG> _ => REG_K5 </OUTREG> +<k> MASK_R => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 5 </REG> + + + +rule <OUTREG> _ => REG_K6 </OUTREG> +<k> MASK_R => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 6 </REG> + + + +rule <OUTREG> _ => REG_K7 </OUTREG> +<k> MASK_R => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 7 </REG> + + + +syntax K ::= "XMM_N3" +rule <k> XMM_N3 => XMM_N3_32 ... </k> +<MODE> 0 </MODE> + + + +rule <k> XMM_N3 => XMM_N3_32 ... </k> +<MODE> 1 </MODE> + + + +rule <k> XMM_N3 => XMM_N3_64 ... </k> +<MODE> 2 </MODE> + + + +syntax K ::= "BRDISPz" +rule <BRDISPWIDTH> _ => 16 </BRDISPWIDTH> +<k> BRDISPz => . ... </k> <EOSZ> 1 </EOSZ> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> OrSP => . ... </k> +rule <BRDISPWIDTH> _ => 32 </BRDISPWIDTH> +<k> BRDISPz => . ... </k> <EOSZ> 2 </EOSZ> -rule <OUTREG> _ => REG_RSP </OUTREG> -<k> OrSP => . ... </k> +rule <BRDISPWIDTH> _ => 32 </BRDISPWIDTH> +<k> BRDISPz => . ... </k> <EOSZ> 3 </EOSZ> @@ -130497,3011 +130932,3197 @@ rule <OUTREG> _ => REG_RBP </OUTREG> -syntax K ::= "rFLAGS" -rule <OUTREG> _ => REG_FLAGS </OUTREG> -<k> rFLAGS => . ... </k> -<MODE> 0 </MODE> +syntax K ::= "FORCE64" +rule <EOSZ> _ => 3 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> FORCE64 => . ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_EFLAGS </OUTREG> -<k> rFLAGS => . ... </k> -<MODE> 1 </MODE> +rule <k> FORCE64 => . ... </k> + [owise] +syntax K ::= "SAE" +rule <SAE> _ => 1 </SAE> +<k> SAE => . ... </k> +<BCRC> 1 </BCRC> -rule <OUTREG> _ => REG_RFLAGS </OUTREG> -<k> rFLAGS => . ... </k> -<MODE> 2 </MODE> +rule <k> SAE => DecoderError ... </k> +<BCRC> 0 </BCRC> -syntax K ::= "MMX_R" -rule <OUTREG> _ => REG_MMX0 </OUTREG> -<k> MMX_R => . ... </k> -<REG> 0 </REG> +syntax K ::= "Ar14" +rule <OUTREG> _ => REG_R14W </OUTREG> +<k> Ar14 => . ... </k> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_MMX1 </OUTREG> -<k> MMX_R => . ... </k> -<REG> 1 </REG> +rule <OUTREG> _ => REG_R14D </OUTREG> +<k> Ar14 => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_MMX2 </OUTREG> -<k> MMX_R => . ... </k> -<REG> 2 </REG> +rule <OUTREG> _ => REG_R14 </OUTREG> +<k> Ar14 => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_MMX3 </OUTREG> -<k> MMX_R => . ... </k> -<REG> 3 </REG> +syntax K ::= "GPRv_SB" +rule <k> GPRv_SB => GPR64_SB ... </k> +<EOSZ> 3 </EOSZ> -rule <OUTREG> _ => REG_MMX4 </OUTREG> -<k> MMX_R => . ... </k> -<REG> 4 </REG> +rule <k> GPRv_SB => GPR32_SB ... </k> +<EOSZ> 2 </EOSZ> -rule <OUTREG> _ => REG_MMX5 </OUTREG> -<k> MMX_R => . ... </k> -<REG> 5 </REG> +rule <k> GPRv_SB => GPR16_SB ... </k> +<EOSZ> 1 </EOSZ> -rule <OUTREG> _ => REG_MMX6 </OUTREG> -<k> MMX_R => . ... </k> -<REG> 6 </REG> +syntax K ::= "UISA_VMODRM_ZMM" +rule <k> UISA_VMODRM_ZMM => UISA_VSIB_ZMM ... </k> +<MOD> 0 </MOD> -rule <OUTREG> _ => REG_MMX7 </OUTREG> -<k> MMX_R => . ... </k> -<REG> 7 </REG> +rule <k> UISA_VMODRM_ZMM => UISA_VSIB_ZMM ~> MEMDISP8 ... </k> +<MOD> 1 </MOD> -syntax K ::= "MMX_B" -rule <OUTREG> _ => REG_MMX0 </OUTREG> -<k> MMX_B => . ... </k> -<RM> 0 </RM> +rule <k> UISA_VMODRM_ZMM => UISA_VSIB_ZMM ~> MEMDISP32 ... </k> +<MOD> 2 </MOD> -rule <OUTREG> _ => REG_MMX1 </OUTREG> -<k> MMX_B => . ... </k> -<RM> 1 </RM> +syntax K ::= "ZMM_R3_64" +rule <OUTREG> _ => REG_ZMM0 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <OUTREG> _ => REG_MMX2 </OUTREG> -<k> MMX_B => . ... </k> -<RM> 2 </RM> +rule <OUTREG> _ => REG_ZMM1 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_MMX3 </OUTREG> -<k> MMX_B => . ... </k> -<RM> 3 </RM> +rule <OUTREG> _ => REG_ZMM2 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_MMX4 </OUTREG> -<k> MMX_B => . ... </k> -<RM> 4 </RM> +rule <OUTREG> _ => REG_ZMM3 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_MMX5 </OUTREG> -<k> MMX_B => . ... </k> -<RM> 5 </RM> +rule <OUTREG> _ => REG_ZMM4 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_MMX6 </OUTREG> -<k> MMX_B => . ... </k> -<RM> 6 </RM> +rule <OUTREG> _ => REG_ZMM5 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_MMX7 </OUTREG> -<k> MMX_B => . ... </k> -<RM> 7 </RM> +rule <OUTREG> _ => REG_ZMM6 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 6 </REG> -syntax K ::= "GPRv_R" -rule <k> GPRv_R => GPR64_R ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_ZMM7 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 7 </REG> + -rule <k> GPRv_R => GPR32_R ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_ZMM8 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <k> GPRv_R => GPR16_R ... </k> -<EOSZ> 1 </EOSZ> + +rule <OUTREG> _ => REG_ZMM9 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 1 </REG> -syntax K ::= "GPRv_SB" -rule <k> GPRv_SB => GPR64_SB ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_ZMM10 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <k> GPRv_SB => GPR32_SB ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_ZMM11 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <k> GPRv_SB => GPR16_SB ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_ZMM12 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 4 </REG> -syntax K ::= "GPRz_R" -rule <k> GPRz_R => GPR32_R ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_ZMM13 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <k> GPRz_R => GPR32_R ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_ZMM14 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <k> GPRz_R => GPR16_R ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_ZMM15 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 7 </REG> -syntax K ::= "GPRv_B" -rule <k> GPRv_B => GPR64_B ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_ZMM16 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <k> GPRv_B => GPR32_B ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_ZMM17 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <k> GPRv_B => GPR16_B ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_ZMM18 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 2 </REG> -syntax K ::= "GPRz_B" -rule <k> GPRz_B => GPR32_B ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_ZMM19 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <k> GPRz_B => GPR32_B ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_ZMM20 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <k> GPRz_B => GPR16_B ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_ZMM21 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 5 </REG> -syntax K ::= "GPRy_B" -rule <k> GPRy_B => GPR64_B ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_ZMM22 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <k> GPRy_B => GPR32_B ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_ZMM23 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <k> GPRy_B => GPR32_B ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_ZMM24 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 0 </REG> -syntax K ::= "GPRy_R" -rule <k> GPRy_R => GPR64_R ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_ZMM25 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <k> GPRy_R => GPR32_R ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_ZMM26 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <k> GPRy_R => GPR32_R ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_ZMM27 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 3 </REG> -syntax K ::= "GPR64_R" -rule <OUTREG> _ => REG_RAX </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_ZMM28 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 4 </REG> + + + +rule <OUTREG> _ => REG_ZMM29 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 5 </REG> + + + +rule <OUTREG> _ => REG_ZMM30 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 6 </REG> + + + +rule <OUTREG> _ => REG_ZMM31 </OUTREG> +<k> ZMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 7 </REG> + + + +syntax K ::= "XMM_R3_64" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 0 </REXR> <REG> 0 </REG> -rule <OUTREG> _ => REG_RCX </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 0 </REXR> <REG> 1 </REG> -rule <OUTREG> _ => REG_RDX </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 0 </REXR> <REG> 2 </REG> -rule <OUTREG> _ => REG_RBX </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 0 </REXR> <REG> 3 </REG> -rule <OUTREG> _ => REG_RSP </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 0 </REXR> <REG> 4 </REG> -rule <OUTREG> _ => REG_RBP </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 0 </REXR> <REG> 5 </REG> -rule <OUTREG> _ => REG_RSI </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 0 </REXR> <REG> 6 </REG> -rule <OUTREG> _ => REG_RDI </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 0 </REXR> <REG> 7 </REG> -rule <OUTREG> _ => REG_R8 </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM8 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 1 </REXR> <REG> 0 </REG> -rule <OUTREG> _ => REG_R9 </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM9 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 1 </REXR> <REG> 1 </REG> -rule <OUTREG> _ => REG_R10 </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM10 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 1 </REXR> <REG> 2 </REG> -rule <OUTREG> _ => REG_R11 </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM11 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 1 </REXR> <REG> 3 </REG> -rule <OUTREG> _ => REG_R12 </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM12 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 1 </REXR> <REG> 4 </REG> -rule <OUTREG> _ => REG_R13 </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM13 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 1 </REXR> <REG> 5 </REG> -rule <OUTREG> _ => REG_R14 </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM14 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 1 </REXR> <REG> 6 </REG> -rule <OUTREG> _ => REG_R15 </OUTREG> -<k> GPR64_R => . ... </k> +rule <OUTREG> _ => REG_XMM15 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> <REXR> 1 </REXR> <REG> 7 </REG> -syntax K ::= "GPR64_B" -rule <OUTREG> _ => REG_RAX </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 0 </REXB> -<RM> 0 </RM> +rule <OUTREG> _ => REG_XMM16 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <OUTREG> _ => REG_RCX </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 0 </REXB> -<RM> 1 </RM> +rule <OUTREG> _ => REG_XMM17 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_RDX </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 0 </REXB> -<RM> 2 </RM> +rule <OUTREG> _ => REG_XMM18 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_RBX </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 0 </REXB> -<RM> 3 </RM> +rule <OUTREG> _ => REG_XMM19 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_RSP </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 0 </REXB> -<RM> 4 </RM> +rule <OUTREG> _ => REG_XMM20 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_RBP </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 0 </REXB> -<RM> 5 </RM> +rule <OUTREG> _ => REG_XMM21 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_RSI </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 0 </REXB> -<RM> 6 </RM> +rule <OUTREG> _ => REG_XMM22 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <OUTREG> _ => REG_RDI </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 0 </REXB> -<RM> 7 </RM> +rule <OUTREG> _ => REG_XMM23 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <OUTREG> _ => REG_R8 </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 1 </REXB> -<RM> 0 </RM> +rule <OUTREG> _ => REG_XMM24 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <OUTREG> _ => REG_R9 </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 1 </REXB> -<RM> 1 </RM> +rule <OUTREG> _ => REG_XMM25 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_R10 </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 1 </REXB> -<RM> 2 </RM> +rule <OUTREG> _ => REG_XMM26 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_R11 </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 1 </REXB> -<RM> 3 </RM> +rule <OUTREG> _ => REG_XMM27 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_R12 </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 1 </REXB> -<RM> 4 </RM> +rule <OUTREG> _ => REG_XMM28 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_R13 </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 1 </REXB> -<RM> 5 </RM> +rule <OUTREG> _ => REG_XMM29 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_R14 </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 1 </REXB> -<RM> 6 </RM> +rule <OUTREG> _ => REG_XMM30 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <OUTREG> _ => REG_R15 </OUTREG> -<k> GPR64_B => . ... </k> -<REXB> 1 </REXB> -<RM> 7 </RM> +rule <OUTREG> _ => REG_XMM31 </OUTREG> +<k> XMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 7 </REG> -syntax K ::= "GPR64_SB" -rule <OUTREG> _ => REG_RAX </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 0 </SRM> +syntax K ::= "MODRM32" +rule <BASE0> _ => REG_EAX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_RCX </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 1 </SRM> +rule <BASE0> _ => REG_ECX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_RDX </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 2 </SRM> +rule <BASE0> _ => REG_EDX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_RBX </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 3 </SRM> +rule <BASE0> _ => REG_EBX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_RSP </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 4 </SRM> +rule <k> MODRM32 => SIB ... </k> +<MOD> 0 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_RBP </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 5 </SRM> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_RSI </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 6 </SRM> +rule <BASE0> _ => REG_ESI </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_RDI </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 7 </SRM> +rule <BASE0> _ => REG_EDI </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R8 </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 0 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_EAX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R9 </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 1 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_ECX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R10 </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 2 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_EDX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_R11 </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 3 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_EBX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_R12 </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 4 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM32 => SIB ... </k> +<MOD> 1 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_R13 </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 5 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_EBP </BASE0> +<k> MODRM32 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_R14 </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 6 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_ESI </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R15 </OUTREG> -<k> GPR64_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 7 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_EDI </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 7 </RM> -syntax K ::= "GPR64_X" -rule <OUTREG> _ => REG_RAX </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<BASE0> _ => REG_EAX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_RCX </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<BASE0> _ => REG_ECX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_RDX </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<BASE0> _ => REG_EDX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_RBX </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<BASE0> _ => REG_EBX </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM32 => SIB ... </k> +<MOD> 2 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_RBP </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<BASE0> _ => REG_EBP </BASE0> +<k> MODRM32 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_RSI </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<BASE0> _ => REG_ESI </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_RDI </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<BASE0> _ => REG_EDI </BASE0> +<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R8 </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> +syntax K ::= "ArDI" +rule <OUTREG> _ => REG_DI </OUTREG> +<k> ArDI => . ... </k> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_R9 </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> ArDI => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_R10 </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_RDI </OUTREG> +<k> ArDI => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_R11 </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +syntax K ::= "ArDX" +rule <OUTREG> _ => REG_DX </OUTREG> +<k> ArDX => . ... </k> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_R12 </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> ArDX => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_R13 </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_RDX </OUTREG> +<k> ArDX => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_R14 </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +syntax K ::= "MASK_B" +rule <OUTREG> _ => REG_K0 </OUTREG> +<k> MASK_B => . ... </k> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R15 </OUTREG> -<k> GPR64_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_K1 </OUTREG> +<k> MASK_B => . ... </k> +<RM> 1 </RM> -syntax K ::= "GPR32_R" -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <OUTREG> _ => REG_K2 </OUTREG> +<k> MASK_B => . ... </k> +<RM> 2 </RM> -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_K3 </OUTREG> +<k> MASK_B => . ... </k> +<RM> 3 </RM> -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_K4 </OUTREG> +<k> MASK_B => . ... </k> +<RM> 4 </RM> -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_K5 </OUTREG> +<k> MASK_B => . ... </k> +<RM> 5 </RM> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_K6 </OUTREG> +<k> MASK_B => . ... </k> +<RM> 6 </RM> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_K7 </OUTREG> +<k> MASK_B => . ... </k> +<RM> 7 </RM> -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> +syntax K ::= "NELEM_TUPLE1_WORD" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1_WORD => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1_WORD => . ... </k> +<VL> 1 </VL> -rule <OUTREG> _ => REG_R8D </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1_WORD => . ... </k> +<VL> 2 </VL> -rule <OUTREG> _ => REG_R9D </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +syntax K ::= "MODRM64alt32" +rule <k> MODRM64alt32 => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 0 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R10D </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <k> MODRM64alt32 => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 0 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R11D </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <k> MODRM64alt32 => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 0 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R12D </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <k> MODRM64alt32 => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 0 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R13D </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <k> MODRM64alt32 => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 0 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_R14D </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <k> MODRM64alt32 => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 0 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_R15D </OUTREG> -<k> GPR32_R => . ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <k> MODRM64alt32 => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 0 </MOD> +<RM> 3 </RM> -syntax K ::= "GPR32_B" -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> GPR32_B => . ... </k> -<REXB> 0 </REXB> -<RM> 0 </RM> +rule <k> MODRM64alt32 => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 0 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> GPR32_B => . ... </k> +rule <k> MODRM64alt32 => SIB ... </k> <REXB> 0 </REXB> -<RM> 1 </RM> +<MOD> 0 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> GPR32_B => . ... </k> -<REXB> 0 </REXB> -<RM> 2 </RM> +rule <k> MODRM64alt32 => SIB ... </k> +<REXB> 1 </REXB> +<MOD> 0 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> GPR32_B => . ... </k> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> MODRM64alt32 => rIPa ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 0 </REXB> -<RM> 3 </RM> +<MOD> 0 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> GPR32_B => . ... </k> -<REXB> 0 </REXB> -<RM> 4 </RM> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => rIPa ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 0 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> GPR32_B => . ... </k> +rule <k> MODRM64alt32 => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 0 </REXB> -<RM> 5 </RM> +<MOD> 0 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> GPR32_B => . ... </k> -<REXB> 0 </REXB> +rule <k> MODRM64alt32 => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 0 </MOD> <RM> 6 </RM> -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> GPR32_B => . ... </k> +rule <k> MODRM64alt32 => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 0 </REXB> +<MOD> 0 </MOD> <RM> 7 </RM> -rule <OUTREG> _ => REG_R8D </OUTREG> -<k> GPR32_B => . ... </k> +rule <k> MODRM64alt32 => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 1 </REXB> -<RM> 0 </RM> +<MOD> 0 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R9D </OUTREG> -<k> GPR32_B => . ... </k> -<REXB> 1 </REXB> -<RM> 1 </RM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 1 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R10D </OUTREG> -<k> GPR32_B => . ... </k> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 1 </REXB> -<RM> 2 </RM> +<MOD> 1 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R11D </OUTREG> -<k> GPR32_B => . ... </k> -<REXB> 1 </REXB> -<RM> 3 </RM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 1 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R12D </OUTREG> -<k> GPR32_B => . ... </k> -<REXB> 1 </REXB> -<RM> 4 </RM> - - - -rule <OUTREG> _ => REG_R13D </OUTREG> -<k> GPR32_B => . ... </k> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 1 </REXB> -<RM> 5 </RM> +<MOD> 1 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R14D </OUTREG> -<k> GPR32_B => . ... </k> -<REXB> 1 </REXB> -<RM> 6 </RM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 1 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_R15D </OUTREG> -<k> GPR32_B => . ... </k> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 1 </REXB> -<RM> 7 </RM> - - - -syntax K ::= "GPR32_SB" -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> GPR32_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 0 </SRM> +<MOD> 1 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> GPR32_SB => . ... </k> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 0 </REXB> -<SRM> 1 </SRM> +<MOD> 1 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> GPR32_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 2 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 1 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> GPR32_SB => . ... </k> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => SIB ... </k> <REXB> 0 </REXB> -<SRM> 3 </SRM> +<MOD> 1 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> GPR32_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 4 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => SIB ... </k> +<REXB> 1 </REXB> +<MOD> 1 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> GPR32_SB => . ... </k> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> <REXB> 0 </REXB> -<SRM> 5 </SRM> +<MOD> 1 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> GPR32_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 6 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 1 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> GPR32_SB => . ... </k> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 0 </REXB> -<SRM> 7 </SRM> - - - -rule <OUTREG> _ => REG_R8D </OUTREG> -<k> GPR32_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 0 </SRM> +<MOD> 1 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R9D </OUTREG> -<k> GPR32_SB => . ... </k> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 1 </REXB> -<SRM> 1 </SRM> +<MOD> 1 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R10D </OUTREG> -<k> GPR32_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 2 </SRM> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 1 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R11D </OUTREG> -<k> GPR32_SB => . ... </k> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 1 </REXB> -<SRM> 3 </SRM> +<MOD> 1 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R12D </OUTREG> -<k> GPR32_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 4 </SRM> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 2 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R13D </OUTREG> -<k> GPR32_SB => . ... </k> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 1 </REXB> -<SRM> 5 </SRM> +<MOD> 2 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R14D </OUTREG> -<k> GPR32_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 6 </SRM> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 2 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R15D </OUTREG> -<k> GPR32_SB => . ... </k> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> <REXB> 1 </REXB> -<SRM> 7 </SRM> - - - -syntax K ::= "GPR32_X" -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> - - - -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +<MOD> 2 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 2 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 2 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 2 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 2 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => SIB ... </k> +<REXB> 0 </REXB> +<MOD> 2 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => SIB ... </k> +<REXB> 1 </REXB> +<MOD> 2 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_R8D </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 2 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_R9D </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 2 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_R10D </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 2 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R11D </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 2 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R12D </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<MOD> 2 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R13D </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<k> MODRM64alt32 => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<MOD> 2 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R14D </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +syntax K ::= "GPRv_B" +rule <k> GPRv_B => GPR64_B ... </k> +<EOSZ> 3 </EOSZ> -rule <OUTREG> _ => REG_R15D </OUTREG> -<k> GPR32_X => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <k> GPRv_B => GPR32_B ... </k> +<EOSZ> 2 </EOSZ> -syntax K ::= "GPR16_R" -rule <OUTREG> _ => REG_AX </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <k> GPRv_B => GPR16_B ... </k> +<EOSZ> 1 </EOSZ> -rule <OUTREG> _ => REG_CX </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 0 </REXR> -<REG> 1 </REG> +syntax K ::= "MEMDISP" +rule <DISPWIDTH> _ => 0 </DISPWIDTH> +<k> MEMDISP => . ... </k> +<NEEDMEMDISP> 0 </NEEDMEMDISP> -rule <OUTREG> _ => REG_DX </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <DISPWIDTH> _ => 8 </DISPWIDTH> +<k> MEMDISP => . ... </k> +<NEEDMEMDISP> 8 </NEEDMEMDISP> -rule <OUTREG> _ => REG_BX </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <DISPWIDTH> _ => 16 </DISPWIDTH> +<k> MEMDISP => . ... </k> +<NEEDMEMDISP> 16 </NEEDMEMDISP> -rule <OUTREG> _ => REG_SP </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <DISPWIDTH> _ => 32 </DISPWIDTH> +<k> MEMDISP => . ... </k> +<NEEDMEMDISP> 32 </NEEDMEMDISP> -rule <OUTREG> _ => REG_BP </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> +syntax K ::= "VSIB_INDEX_XMM" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <OUTREG> _ => REG_SI </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <OUTREG> _ => REG_DI </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <OUTREG> _ => REG_R8W </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <OUTREG> _ => REG_R9W </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <OUTREG> _ => REG_R10W </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <OUTREG> _ => REG_R11W </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <OUTREG> _ => REG_R12W </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <OUTREG> _ => REG_R13W </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_XMM8 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <OUTREG> _ => REG_R14W </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_XMM9 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <OUTREG> _ => REG_R15W </OUTREG> -<k> GPR16_R => . ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_XMM10 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> -syntax K ::= "GPR16_B" -rule <OUTREG> _ => REG_AX </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 0 </REXB> -<RM> 0 </RM> +rule <OUTREG> _ => REG_XMM11 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <OUTREG> _ => REG_CX </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 0 </REXB> -<RM> 1 </RM> +rule <OUTREG> _ => REG_XMM12 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <OUTREG> _ => REG_DX </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 0 </REXB> -<RM> 2 </RM> +rule <OUTREG> _ => REG_XMM13 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <OUTREG> _ => REG_BX </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 0 </REXB> -<RM> 3 </RM> +rule <OUTREG> _ => REG_XMM14 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <OUTREG> _ => REG_SP </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 0 </REXB> -<RM> 4 </RM> +rule <OUTREG> _ => REG_XMM15 </OUTREG> +<k> VSIB_INDEX_XMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <OUTREG> _ => REG_BP </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 0 </REXB> -<RM> 5 </RM> +syntax K ::= "MEMDISP8" +rule <DISPWIDTH> _ => 8 </DISPWIDTH> +<k> MEMDISP8 => . ... </k> -rule <OUTREG> _ => REG_SI </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 0 </REXB> -<RM> 6 </RM> +syntax K ::= "YMM_R3" +rule <k> YMM_R3 => YMM_R3_32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_DI </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 0 </REXB> -<RM> 7 </RM> +rule <k> YMM_R3 => YMM_R3_32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_R8W </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 1 </REXB> -<RM> 0 </RM> +rule <k> YMM_R3 => YMM_R3_64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_R9W </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 1 </REXB> -<RM> 1 </RM> +syntax K ::= "FINAL_SSEG_MODE64" +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> FINAL_SSEG_MODE64 => . ... </k> +<SEGOVD> 0 </SEGOVD> -rule <OUTREG> _ => REG_R10W </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 1 </REXB> -<RM> 2 </RM> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_MODE64 => . ... </k> +<SEGOVD> 1 </SEGOVD> -rule <OUTREG> _ => REG_R11W </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 1 </REXB> -<RM> 3 </RM> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_MODE64 => . ... </k> +<SEGOVD> 2 </SEGOVD> -rule <OUTREG> _ => REG_R12W </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 1 </REXB> -<RM> 4 </RM> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_MODE64 => . ... </k> +<SEGOVD> 3 </SEGOVD> -rule <OUTREG> _ => REG_R13W </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 1 </REXB> -<RM> 5 </RM> +rule <OUTREG> _ => REG_FS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_MODE64 => . ... </k> +<SEGOVD> 4 </SEGOVD> -rule <OUTREG> _ => REG_R14W </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 1 </REXB> -<RM> 6 </RM> +rule <OUTREG> _ => REG_GS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_MODE64 => . ... </k> +<SEGOVD> 5 </SEGOVD> -rule <OUTREG> _ => REG_R15W </OUTREG> -<k> GPR16_B => . ... </k> -<REXB> 1 </REXB> -<RM> 7 </RM> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_MODE64 => . ... </k> +<SEGOVD> 6 </SEGOVD> -syntax K ::= "GPR16_SB" -rule <OUTREG> _ => REG_AX </OUTREG> -<k> GPR16_SB => . ... </k> +syntax K ::= "GPR64_SB" +rule <OUTREG> _ => REG_RAX </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 0 </REXB> <SRM> 0 </SRM> -rule <OUTREG> _ => REG_CX </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_RCX </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 0 </REXB> <SRM> 1 </SRM> -rule <OUTREG> _ => REG_DX </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_RDX </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 0 </REXB> <SRM> 2 </SRM> -rule <OUTREG> _ => REG_BX </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_RBX </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 0 </REXB> <SRM> 3 </SRM> -rule <OUTREG> _ => REG_SP </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_RSP </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 0 </REXB> <SRM> 4 </SRM> -rule <OUTREG> _ => REG_BP </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_RBP </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 0 </REXB> <SRM> 5 </SRM> -rule <OUTREG> _ => REG_SI </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_RSI </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 0 </REXB> <SRM> 6 </SRM> -rule <OUTREG> _ => REG_DI </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_RDI </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 0 </REXB> <SRM> 7 </SRM> -rule <OUTREG> _ => REG_R8W </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_R8 </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 1 </REXB> <SRM> 0 </SRM> -rule <OUTREG> _ => REG_R9W </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_R9 </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 1 </REXB> <SRM> 1 </SRM> -rule <OUTREG> _ => REG_R10W </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_R10 </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 1 </REXB> <SRM> 2 </SRM> -rule <OUTREG> _ => REG_R11W </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_R11 </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 1 </REXB> <SRM> 3 </SRM> -rule <OUTREG> _ => REG_R12W </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_R12 </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 1 </REXB> <SRM> 4 </SRM> -rule <OUTREG> _ => REG_R13W </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_R13 </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 1 </REXB> <SRM> 5 </SRM> -rule <OUTREG> _ => REG_R14W </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_R14 </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 1 </REXB> <SRM> 6 </SRM> -rule <OUTREG> _ => REG_R15W </OUTREG> -<k> GPR16_SB => . ... </k> +rule <OUTREG> _ => REG_R15 </OUTREG> +<k> GPR64_SB => . ... </k> <REXB> 1 </REXB> <SRM> 7 </SRM> -syntax K ::= "CR_R" -rule <OUTREG> _ => REG_CR0 </OUTREG> -<k> CR_R => . ... </k> -<REXR> 0 </REXR> +syntax K ::= "NELEM_GPR_READER_SUBDWORD" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_READER_SUBDWORD => . ... </k> +<VL> 0 </VL> + + + +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_READER_SUBDWORD => . ... </k> +<VL> 1 </VL> + + + +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_READER_SUBDWORD => . ... </k> +<VL> 2 </VL> + + + +syntax K ::= "Ar8" +rule <OUTREG> _ => REG_R8W </OUTREG> +<k> Ar8 => . ... </k> +<EASZ> 1 </EASZ> + + + +rule <OUTREG> _ => REG_R8D </OUTREG> +<k> Ar8 => . ... </k> +<EASZ> 2 </EASZ> + + + +rule <OUTREG> _ => REG_R8 </OUTREG> +<k> Ar8 => . ... </k> +<EASZ> 3 </EASZ> + + + +syntax K ::= "YMM_R_32" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_R_32 => . ... </k> <REG> 0 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> CR_R => . ... </k> -<REXR> 0 </REXR> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_R_32 => . ... </k> <REG> 1 </REG> -rule <OUTREG> _ => REG_CR2 </OUTREG> -<k> CR_R => . ... </k> -<REXR> 0 </REXR> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_R_32 => . ... </k> <REG> 2 </REG> -rule <OUTREG> _ => REG_CR3 </OUTREG> -<k> CR_R => . ... </k> -<REXR> 0 </REXR> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_R_32 => . ... </k> <REG> 3 </REG> -rule <OUTREG> _ => REG_CR4 </OUTREG> -<k> CR_R => . ... </k> -<REXR> 0 </REXR> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_R_32 => . ... </k> <REG> 4 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 0 </REXR> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_R_32 => . ... </k> <REG> 5 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 0 </REXR> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_R_32 => . ... </k> <REG> 6 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 0 </REXR> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_R_32 => . ... </k> <REG> 7 </REG> -rule <OUTREG> _ => REG_CR8 </OUTREG> -<k> CR_R => . ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +syntax K ::= "NELEM_MOVDDUP" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_MOVDDUP => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_MOVDDUP => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_MOVDDUP => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +syntax K ::= "VMODRM_YMM" +rule <k> VMODRM_YMM => VSIB_YMM ... </k> +<MOD> 0 </MOD> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <k> VMODRM_YMM => VSIB_YMM ~> MEMDISP8 ... </k> +<MOD> 1 </MOD> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <k> VMODRM_YMM => VSIB_YMM ~> MEMDISP32 ... </k> +<MOD> 2 </MOD> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +syntax K ::= "NELEM_TUPLE1_4X" +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_TUPLE1_4X => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_R => . ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_TUPLE1_4X => . ... </k> +<VL> 1 </VL> -syntax K ::= "CR_B" -rule <OUTREG> _ => REG_CR0 </OUTREG> -<k> CR_B => . ... </k> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_TUPLE1_4X => . ... </k> +<VL> 2 </VL> + + + +syntax K ::= "BND_B_CHECK" +rule <k> BND_B_CHECK => . ... </k> <REXB> 0 </REXB> <RM> 0 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => . ... </k> <REXB> 0 </REXB> <RM> 1 </RM> -rule <OUTREG> _ => REG_CR2 </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => . ... </k> <REXB> 0 </REXB> <RM> 2 </RM> -rule <OUTREG> _ => REG_CR3 </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => . ... </k> <REXB> 0 </REXB> <RM> 3 </RM> -rule <OUTREG> _ => REG_CR4 </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 0 </REXB> <RM> 4 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 0 </REXB> <RM> 5 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 0 </REXB> <RM> 6 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 0 </REXB> <RM> 7 </RM> -rule <OUTREG> _ => REG_CR8 </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 1 </REXB> <RM> 0 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 1 </REXB> <RM> 1 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 1 </REXB> <RM> 2 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 1 </REXB> <RM> 3 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 1 </REXB> <RM> 4 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 1 </REXB> <RM> 5 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 1 </REXB> <RM> 6 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> CR_B => . ... </k> +rule <k> BND_B_CHECK => DecoderError ... </k> <REXB> 1 </REXB> <RM> 7 </RM> -syntax K ::= "DR_R" -rule <OUTREG> _ => REG_DR0 </OUTREG> -<k> DR_R => . ... </k> +syntax K ::= "XMM_B3" +rule <k> XMM_B3 => XMM_B3_32 ... </k> +<MODE> 0 </MODE> + + + +rule <k> XMM_B3 => XMM_B3_32 ... </k> +<MODE> 1 </MODE> + + + +rule <k> XMM_B3 => XMM_B3_64 ... </k> +<MODE> 2 </MODE> + + + +syntax K ::= "ESIZE_2_BITS" +rule <ELEMENTSIZE> _ => 2 </ELEMENTSIZE> +<k> ESIZE_2_BITS => . ... </k> +<REX> 0 </REX> + + + +syntax K ::= "GPR64_R" +rule <OUTREG> _ => REG_RAX </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 0 </REXR> <REG> 0 </REG> -rule <OUTREG> _ => REG_DR1 </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_RCX </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 0 </REXR> <REG> 1 </REG> -rule <OUTREG> _ => REG_DR2 </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_RDX </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 0 </REXR> <REG> 2 </REG> -rule <OUTREG> _ => REG_DR3 </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_RBX </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 0 </REXR> <REG> 3 </REG> -rule <OUTREG> _ => REG_DR4 </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_RSP </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 0 </REXR> <REG> 4 </REG> -rule <OUTREG> _ => REG_DR5 </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_RBP </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 0 </REXR> <REG> 5 </REG> -rule <OUTREG> _ => REG_DR6 </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_RSI </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 0 </REXR> <REG> 6 </REG> -rule <OUTREG> _ => REG_DR7 </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_RDI </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 0 </REXR> <REG> 7 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_R8 </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 1 </REXR> <REG> 0 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_R9 </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 1 </REXR> <REG> 1 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_R10 </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 1 </REXR> <REG> 2 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_R11 </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 1 </REXR> <REG> 3 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_R12 </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 1 </REXR> <REG> 4 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_R13 </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 1 </REXR> <REG> 5 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_R14 </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 1 </REXR> <REG> 6 </REG> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> DR_R => . ... </k> +rule <OUTREG> _ => REG_R15 </OUTREG> +<k> GPR64_R => . ... </k> <REXR> 1 </REXR> <REG> 7 </REG> -syntax K ::= "X87" -rule <OUTREG> _ => REG_ST0 </OUTREG> -<k> X87 => . ... </k> -<RM> 0 </RM> - - - -rule <OUTREG> _ => REG_ST1 </OUTREG> -<k> X87 => . ... </k> -<RM> 1 </RM> +syntax K ::= "DF64" +rule <k> DF64 => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_ST2 </OUTREG> -<k> X87 => . ... </k> -<RM> 2 </RM> +rule <k> DF64 => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_ST3 </OUTREG> -<k> X87 => . ... </k> -<RM> 3 </RM> +rule <EOSZ> _ => 1 </EOSZ> +<DF64> _ => 1 </DF64> +<k> DF64 => . ... </k> +<MODE> 2 </MODE> +<OSZ> 1 </OSZ> +<REXW> 0 </REXW> -rule <OUTREG> _ => REG_ST4 </OUTREG> -<k> X87 => . ... </k> -<RM> 4 </RM> +rule <EOSZ> _ => 3 </EOSZ> +<DF64> _ => 1 </DF64> +<k> DF64 => . ... </k> +<MODE> 2 </MODE> +<OSZ> 0 </OSZ> +<REXW> 0 </REXW> -rule <OUTREG> _ => REG_ST5 </OUTREG> -<k> X87 => . ... </k> -<RM> 5 </RM> +rule <EOSZ> _ => 3 </EOSZ> +<DF64> _ => 1 </DF64> +<k> DF64 => . ... </k> +<MODE> 2 </MODE> +<OSZ> 1 </OSZ> +<REXW> 1 </REXW> -rule <OUTREG> _ => REG_ST6 </OUTREG> -<k> X87 => . ... </k> -<RM> 6 </RM> +rule <EOSZ> _ => 3 </EOSZ> +<DF64> _ => 1 </DF64> +<k> DF64 => . ... </k> +<MODE> 2 </MODE> +<OSZ> 0 </OSZ> +<REXW> 1 </REXW> -rule <OUTREG> _ => REG_ST7 </OUTREG> -<k> X87 => . ... </k> -<RM> 7 </RM> +syntax K ::= "FINAL_DSEG1_MODE64" +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> FINAL_DSEG1_MODE64 => . ... </k> +<SEGOVD> 0 </SEGOVD> -syntax K ::= "SEG" -rule <OUTREG> _ => REG_ES </OUTREG> -<k> SEG => . ... </k> -<REG> 0 </REG> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_MODE64 => . ... </k> +<SEGOVD> 1 </SEGOVD> -rule <OUTREG> _ => REG_CS </OUTREG> -<k> SEG => . ... </k> -<REG> 1 </REG> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_MODE64 => . ... </k> +<SEGOVD> 2 </SEGOVD> -rule <OUTREG> _ => REG_SS </OUTREG> -<k> SEG => . ... </k> -<REG> 2 </REG> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_MODE64 => . ... </k> +<SEGOVD> 3 </SEGOVD> -rule <OUTREG> _ => REG_DS </OUTREG> -<k> SEG => . ... </k> -<REG> 3 </REG> +rule <OUTREG> _ => REG_FS </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_MODE64 => . ... </k> +<SEGOVD> 4 </SEGOVD> -rule <OUTREG> _ => REG_FS </OUTREG> -<k> SEG => . ... </k> -<REG> 4 </REG> +rule <OUTREG> _ => REG_GS </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_MODE64 => . ... </k> +<SEGOVD> 5 </SEGOVD> -rule <OUTREG> _ => REG_GS </OUTREG> -<k> SEG => . ... </k> -<REG> 5 </REG> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_MODE64 => . ... </k> +<SEGOVD> 6 </SEGOVD> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> SEG => . ... </k> -<REG> 6 </REG> +syntax K ::= "GPR8_SB" +rule <OUTREG> _ => REG_AL </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 0 </SRM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> SEG => . ... </k> -<REG> 7 </REG> +rule <OUTREG> _ => REG_CL </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 1 </SRM> -syntax K ::= "SEG_MOV" -rule <OUTREG> _ => REG_ES </OUTREG> -<k> SEG_MOV => . ... </k> -<REG> 0 </REG> +rule <OUTREG> _ => REG_DL </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 2 </SRM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> SEG_MOV => . ... </k> -<REG> 1 </REG> - - - -rule <OUTREG> _ => REG_SS </OUTREG> -<k> SEG_MOV => . ... </k> -<REG> 2 </REG> - - - -rule <OUTREG> _ => REG_DS </OUTREG> -<k> SEG_MOV => . ... </k> -<REG> 3 </REG> - - - -rule <OUTREG> _ => REG_FS </OUTREG> -<k> SEG_MOV => . ... </k> -<REG> 4 </REG> - - - -rule <OUTREG> _ => REG_GS </OUTREG> -<k> SEG_MOV => . ... </k> -<REG> 5 </REG> - - - -rule <OUTREG> _ => REG_ERROR </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> SEG_MOV => . ... </k> -<REG> 6 </REG> - - - -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> SEG_MOV => . ... </k> -<REG> 7 </REG> - - - -syntax K ::= "FINAL_DSEG" -rule <k> FINAL_DSEG => FINAL_DSEG_NOT64 ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_BL </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 3 </SRM> -rule <k> FINAL_DSEG => FINAL_DSEG_NOT64 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_AH </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 4 </SRM> +<REX> 0 </REX> -rule <k> FINAL_DSEG => FINAL_DSEG_MODE64 ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_CH </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 5 </SRM> +<REX> 0 </REX> -syntax K ::= "FINAL_DSEG_NOT64" -rule <OUTREG> _ => REG_CS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_NOT64 => . ... </k> -<SEGOVD> 1 </SEGOVD> +rule <OUTREG> _ => REG_DH </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 6 </SRM> +<REX> 0 </REX> -rule <OUTREG> _ => REG_ES </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_NOT64 => . ... </k> -<SEGOVD> 3 </SEGOVD> +rule <OUTREG> _ => REG_BH </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 7 </SRM> +<REX> 0 </REX> -rule <OUTREG> _ => REG_FS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_NOT64 => . ... </k> -<SEGOVD> 4 </SEGOVD> +rule <OUTREG> _ => REG_SPL </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 4 </SRM> +<REX> 1 </REX> -rule <OUTREG> _ => REG_GS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_NOT64 => . ... </k> -<SEGOVD> 5 </SEGOVD> +rule <OUTREG> _ => REG_BPL </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 5 </SRM> +<REX> 1 </REX> -rule <OUTREG> _ => REG_SS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_NOT64 => . ... </k> -<SEGOVD> 6 </SEGOVD> +rule <OUTREG> _ => REG_SIL </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 6 </SRM> +<REX> 1 </REX> -syntax K ::= "FINAL_DSEG_MODE64" -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> FINAL_DSEG_MODE64 => . ... </k> -<SEGOVD> 0 </SEGOVD> +rule <OUTREG> _ => REG_DIL </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 7 </SRM> +<REX> 1 </REX> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_MODE64 => . ... </k> -<SEGOVD> 1 </SEGOVD> +rule <OUTREG> _ => REG_R8B </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 0 </SRM> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_MODE64 => . ... </k> -<SEGOVD> 2 </SEGOVD> +rule <OUTREG> _ => REG_R9B </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 1 </SRM> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_MODE64 => . ... </k> -<SEGOVD> 3 </SEGOVD> +rule <OUTREG> _ => REG_R10B </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 2 </SRM> -rule <OUTREG> _ => REG_FS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_MODE64 => . ... </k> -<SEGOVD> 4 </SEGOVD> +rule <OUTREG> _ => REG_R11B </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 3 </SRM> -rule <OUTREG> _ => REG_GS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_MODE64 => . ... </k> -<SEGOVD> 5 </SEGOVD> +rule <OUTREG> _ => REG_R12B </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 4 </SRM> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_DSEG_MODE64 => . ... </k> -<SEGOVD> 6 </SEGOVD> +rule <OUTREG> _ => REG_R13B </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 5 </SRM> -syntax K ::= "FINAL_DSEG1" -rule <k> FINAL_DSEG1 => FINAL_DSEG1_NOT64 ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_R14B </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 6 </SRM> -rule <k> FINAL_DSEG1 => FINAL_DSEG1_NOT64 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_R15B </OUTREG> +<k> GPR8_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 7 </SRM> -rule <k> FINAL_DSEG1 => FINAL_DSEG1_MODE64 ... </k> +syntax K ::= "GPRm_R" +rule <k> GPRm_R => GPR64_R ... </k> <MODE> 2 </MODE> -syntax K ::= "FINAL_DSEG1_NOT64" -rule <OUTREG> _ => REG_CS </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_NOT64 => . ... </k> -<SEGOVD> 1 </SEGOVD> +rule <k> GPRm_R => GPR32_R ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_ES </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_NOT64 => . ... </k> -<SEGOVD> 3 </SEGOVD> +rule <k> GPRm_R => GPR32_R ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_FS </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_NOT64 => . ... </k> -<SEGOVD> 4 </SEGOVD> +syntax K ::= "UISA_VSIB_ZMM" +rule <SCALE> _ => 1 </SCALE> +<k> UISA_VSIB_ZMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_ZMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> -rule <OUTREG> _ => REG_GS </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_NOT64 => . ... </k> -<SEGOVD> 5 </SEGOVD> +rule <SCALE> _ => 2 </SCALE> +<k> UISA_VSIB_ZMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_ZMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> -rule <OUTREG> _ => REG_SS </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_NOT64 => . ... </k> -<SEGOVD> 6 </SEGOVD> +rule <SCALE> _ => 4 </SCALE> +<k> UISA_VSIB_ZMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_ZMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> -syntax K ::= "FINAL_DSEG1_MODE64" -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> FINAL_DSEG1_MODE64 => . ... </k> -<SEGOVD> 0 </SEGOVD> +rule <SCALE> _ => 8 </SCALE> +<k> UISA_VSIB_ZMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_ZMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_MODE64 => . ... </k> -<SEGOVD> 1 </SEGOVD> +syntax K ::= "GPRz_B" +rule <k> GPRz_B => GPR32_B ... </k> +<EOSZ> 3 </EOSZ> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_MODE64 => . ... </k> -<SEGOVD> 2 </SEGOVD> +rule <k> GPRz_B => GPR32_B ... </k> +<EOSZ> 2 </EOSZ> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_MODE64 => . ... </k> -<SEGOVD> 3 </SEGOVD> +rule <k> GPRz_B => GPR16_B ... </k> +<EOSZ> 1 </EOSZ> -rule <OUTREG> _ => REG_FS </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_MODE64 => . ... </k> -<SEGOVD> 4 </SEGOVD> +syntax K ::= "ArSI" +rule <OUTREG> _ => REG_SI </OUTREG> +<k> ArSI => . ... </k> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_GS </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_MODE64 => . ... </k> -<SEGOVD> 5 </SEGOVD> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> ArSI => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_DSEG1_MODE64 => . ... </k> -<SEGOVD> 6 </SEGOVD> +rule <OUTREG> _ => REG_RSI </OUTREG> +<k> ArSI => . ... </k> +<EASZ> 3 </EASZ> -syntax K ::= "FINAL_ESEG" -rule <OUTREG> _ => REG_ES </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_ESEG => . ... </k> -<MODE> 0 </MODE> +syntax K ::= "GPRz_R" +rule <k> GPRz_R => GPR32_R ... </k> +<EOSZ> 3 </EOSZ> -rule <OUTREG> _ => REG_ES </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_ESEG => . ... </k> -<MODE> 1 </MODE> +rule <k> GPRz_R => GPR32_R ... </k> +<EOSZ> 2 </EOSZ> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_ESEG => . ... </k> -<MODE> 2 </MODE> +rule <k> GPRz_R => GPR16_R ... </k> +<EOSZ> 1 </EOSZ> -syntax K ::= "FINAL_ESEG1" -rule <OUTREG> _ => REG_ES </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_ESEG1 => . ... </k> -<MODE> 0 </MODE> +syntax K ::= "GPR32_B" +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 0 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_ES </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_ESEG1 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 0 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_ESEG1 => . ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 0 </REXB> +<RM> 2 </RM> -syntax K ::= "FINAL_SSEG1" -rule <OUTREG> _ => REG_SS </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_SSEG1 => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_SS </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_SSEG1 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 0 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> -<k> FINAL_SSEG1 => . ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 0 </REXB> +<RM> 5 </RM> -syntax K ::= "FINAL_SSEG0" -rule <OUTREG> _ => REG_SS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG0 => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_SS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG0 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 0 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG0 => . ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_R8D </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 1 </REXB> +<RM> 0 </RM> -syntax K ::= "FINAL_SSEG" -rule <k> FINAL_SSEG => FINAL_SSEG_NOT64 ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_R9D </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <k> FINAL_SSEG => FINAL_SSEG_NOT64 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_R10D </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <k> FINAL_SSEG => FINAL_SSEG_MODE64 ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_R11D </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 1 </REXB> +<RM> 3 </RM> -syntax K ::= "FINAL_SSEG_NOT64" -rule <OUTREG> _ => REG_CS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_NOT64 => . ... </k> -<SEGOVD> 1 </SEGOVD> +rule <OUTREG> _ => REG_R12D </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 1 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_DS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_NOT64 => . ... </k> -<SEGOVD> 2 </SEGOVD> +rule <OUTREG> _ => REG_R13D </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 1 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_ES </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_NOT64 => . ... </k> -<SEGOVD> 3 </SEGOVD> +rule <OUTREG> _ => REG_R14D </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 1 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_FS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_NOT64 => . ... </k> -<SEGOVD> 4 </SEGOVD> +rule <OUTREG> _ => REG_R15D </OUTREG> +<k> GPR32_B => . ... </k> +<REXB> 1 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_GS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_NOT64 => . ... </k> -<SEGOVD> 5 </SEGOVD> +syntax K ::= "NELEM_TUPLE1_SUBDWORD" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1_SUBDWORD => . ... </k> +<VL> 0 </VL> -syntax K ::= "FINAL_SSEG_MODE64" -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> FINAL_SSEG_MODE64 => . ... </k> -<SEGOVD> 0 </SEGOVD> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1_SUBDWORD => . ... </k> +<VL> 1 </VL> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_MODE64 => . ... </k> -<SEGOVD> 1 </SEGOVD> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1_SUBDWORD => . ... </k> +<VL> 2 </VL> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_MODE64 => . ... </k> -<SEGOVD> 2 </SEGOVD> +syntax K ::= "NELEM_GPR_WRITER_LDOP" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_LDOP => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_MODE64 => . ... </k> -<SEGOVD> 3 </SEGOVD> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_LDOP => . ... </k> +<VL> 1 </VL> -rule <OUTREG> _ => REG_FS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_MODE64 => . ... </k> -<SEGOVD> 4 </SEGOVD> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_LDOP => . ... </k> +<VL> 2 </VL> -rule <OUTREG> _ => REG_GS </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_MODE64 => . ... </k> -<SEGOVD> 5 </SEGOVD> +syntax K ::= "NELEM_TUPLE1_BYTE" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1_BYTE => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_INVALID </OUTREG> -<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> -<k> FINAL_SSEG_MODE64 => . ... </k> -<SEGOVD> 6 </SEGOVD> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1_BYTE => . ... </k> +<VL> 1 </VL> -syntax K ::= "GPR8_R" -rule <OUTREG> _ => REG_AL </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_TUPLE1_BYTE => . ... </k> +<VL> 2 </VL> -rule <OUTREG> _ => REG_CL </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 1 </REG> +syntax K ::= "ArBP" +rule <OUTREG> _ => REG_BP </OUTREG> +<k> ArBP => . ... </k> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_DL </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> ArBP => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_BL </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_RBP </OUTREG> +<k> ArBP => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_AH </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> -<REX> 0 </REX> +syntax K ::= "XMM_B3_64" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_CH </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> -<REX> 0 </REX> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_DH </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> -<REX> 0 </REX> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_BH </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> -<REX> 0 </REX> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_SPL </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> -<REX> 1 </REX> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_BPL </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> -<REX> 1 </REX> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_SIL </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> -<REX> 1 </REX> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_DIL </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> -<REX> 1 </REX> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R8B </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <OUTREG> _ => REG_XMM8 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R9B </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_XMM9 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R10B </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_XMM10 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_R11B </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_XMM11 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_R12B </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_XMM12 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_R13B </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_XMM13 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_R14B </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_XMM14 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R15B </OUTREG> -<k> GPR8_R => . ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_XMM15 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 7 </RM> -syntax K ::= "GPR8_B" -rule <OUTREG> _ => REG_AL </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM16 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 0 </RM> -rule <OUTREG> _ => REG_CL </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM17 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 1 </RM> -rule <OUTREG> _ => REG_DL </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM18 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 2 </RM> -rule <OUTREG> _ => REG_BL </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM19 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 3 </RM> -rule <OUTREG> _ => REG_AH </OUTREG> -<k> GPR8_B => . ... </k> -<REXB> 0 </REXB> -<RM> 4 </RM> -<REX> 0 </REX> - - - -rule <OUTREG> _ => REG_CH </OUTREG> -<k> GPR8_B => . ... </k> -<REXB> 0 </REXB> -<RM> 5 </RM> -<REX> 0 </REX> - - - -rule <OUTREG> _ => REG_DH </OUTREG> -<k> GPR8_B => . ... </k> -<REXB> 0 </REXB> -<RM> 6 </RM> -<REX> 0 </REX> - - - -rule <OUTREG> _ => REG_BH </OUTREG> -<k> GPR8_B => . ... </k> -<REXB> 0 </REXB> -<RM> 7 </RM> -<REX> 0 </REX> - - - -rule <OUTREG> _ => REG_SPL </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM20 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 4 </RM> -<REX> 1 </REX> -rule <OUTREG> _ => REG_BPL </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM21 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 5 </RM> -<REX> 1 </REX> -rule <OUTREG> _ => REG_SIL </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM22 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 6 </RM> -<REX> 1 </REX> -rule <OUTREG> _ => REG_DIL </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM23 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 7 </RM> -<REX> 1 </REX> -rule <OUTREG> _ => REG_R8B </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM24 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 0 </RM> -rule <OUTREG> _ => REG_R9B </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM25 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 1 </RM> -rule <OUTREG> _ => REG_R10B </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM26 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 2 </RM> -rule <OUTREG> _ => REG_R11B </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM27 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 3 </RM> -rule <OUTREG> _ => REG_R12B </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM28 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 4 </RM> -rule <OUTREG> _ => REG_R13B </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM29 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 5 </RM> -rule <OUTREG> _ => REG_R14B </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM30 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 6 </RM> -rule <OUTREG> _ => REG_R15B </OUTREG> -<k> GPR8_B => . ... </k> +rule <OUTREG> _ => REG_XMM31 </OUTREG> +<k> XMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 7 </RM> -syntax K ::= "GPR8_SB" -rule <OUTREG> _ => REG_AL </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 0 </SRM> +syntax K ::= "rFLAGS" +rule <OUTREG> _ => REG_FLAGS </OUTREG> +<k> rFLAGS => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_CL </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 1 </SRM> +rule <OUTREG> _ => REG_EFLAGS </OUTREG> +<k> rFLAGS => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_DL </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 2 </SRM> +rule <OUTREG> _ => REG_RFLAGS </OUTREG> +<k> rFLAGS => . ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_BL </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 3 </SRM> +syntax K ::= "VSIB_INDEX_YMM" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <OUTREG> _ => REG_AH </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 4 </SRM> -<REX> 0 </REX> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <OUTREG> _ => REG_CH </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 5 </SRM> -<REX> 0 </REX> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <OUTREG> _ => REG_DH </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 6 </SRM> -<REX> 0 </REX> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <OUTREG> _ => REG_BH </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 7 </SRM> -<REX> 0 </REX> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <OUTREG> _ => REG_SPL </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 4 </SRM> -<REX> 1 </REX> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <OUTREG> _ => REG_BPL </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 5 </SRM> -<REX> 1 </REX> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <OUTREG> _ => REG_SIL </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 6 </SRM> -<REX> 1 </REX> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <OUTREG> _ => REG_DIL </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 0 </REXB> -<SRM> 7 </SRM> -<REX> 1 </REX> +rule <OUTREG> _ => REG_YMM8 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <OUTREG> _ => REG_R8B </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 0 </SRM> +rule <OUTREG> _ => REG_YMM9 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <OUTREG> _ => REG_R9B </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 1 </SRM> +rule <OUTREG> _ => REG_YMM10 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <OUTREG> _ => REG_R10B </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 2 </SRM> +rule <OUTREG> _ => REG_YMM11 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <OUTREG> _ => REG_R11B </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 3 </SRM> +rule <OUTREG> _ => REG_YMM12 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <OUTREG> _ => REG_R12B </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 4 </SRM> +rule <OUTREG> _ => REG_YMM13 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <OUTREG> _ => REG_R13B </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 5 </SRM> +rule <OUTREG> _ => REG_YMM14 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <OUTREG> _ => REG_R14B </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 6 </SRM> +rule <OUTREG> _ => REG_YMM15 </OUTREG> +<k> VSIB_INDEX_YMM => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <OUTREG> _ => REG_R15B </OUTREG> -<k> GPR8_SB => . ... </k> -<REXB> 1 </REXB> -<SRM> 7 </SRM> +syntax K ::= "OrSP" +rule <OUTREG> _ => REG_SP </OUTREG> +<k> OrSP => . ... </k> +<EOSZ> 1 </EOSZ> -syntax K ::= "OSZ_NONTERM" -rule <EOSZ> _ => 1 </EOSZ> -<k> OSZ_NONTERM => . ... </k> -<MODE> 0 </MODE> -<OSZ> 0 </OSZ> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> OrSP => . ... </k> +<EOSZ> 2 </EOSZ> -rule <EOSZ> _ => 2 </EOSZ> -<k> OSZ_NONTERM => . ... </k> -<MODE> 0 </MODE> -<OSZ> 1 </OSZ> +rule <OUTREG> _ => REG_RSP </OUTREG> +<k> OrSP => . ... </k> +<EOSZ> 3 </EOSZ> -rule <EOSZ> _ => 1 </EOSZ> -<k> OSZ_NONTERM => . ... </k> -<MODE> 1 </MODE> -<OSZ> 1 </OSZ> +syntax K ::= "VGPR32_B" +rule <k> VGPR32_B => VGPR32_B_32 ... </k> +<MODE> 0 </MODE> -rule <EOSZ> _ => 2 </EOSZ> -<k> OSZ_NONTERM => . ... </k> +rule <k> VGPR32_B => VGPR32_B_32 ... </k> <MODE> 1 </MODE> -<OSZ> 0 </OSZ> -rule <EOSZ> _ => 1 </EOSZ> -<k> OSZ_NONTERM => . ... </k> +rule <k> VGPR32_B => VGPR32_B_64 ... </k> <MODE> 2 </MODE> -<OSZ> 1 </OSZ> -<REXW> 0 </REXW> -rule <EOSZ> _ => 2 </EOSZ> -<k> OSZ_NONTERM => . ... </k> -<MODE> 2 </MODE> -<OSZ> 0 </OSZ> -<REXW> 0 </REXW> +syntax K ::= "UISA_VSIB_INDEX_XMM" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <EOSZ> _ => 3 </EOSZ> -<k> OSZ_NONTERM => . ... </k> -<MODE> 2 </MODE> -<OSZ> 1 </OSZ> -<REXW> 1 </REXW> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <EOSZ> _ => 3 </EOSZ> -<k> OSZ_NONTERM => . ... </k> -<MODE> 2 </MODE> -<OSZ> 0 </OSZ> -<REXW> 1 </REXW> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -syntax K ::= "DF64" -rule <k> DF64 => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <k> DF64 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <EOSZ> _ => 1 </EOSZ> -<DF64> _ => 1 </DF64> -<k> DF64 => . ... </k> -<MODE> 2 </MODE> -<OSZ> 1 </OSZ> -<REXW> 0 </REXW> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <EOSZ> _ => 3 </EOSZ> -<DF64> _ => 1 </DF64> -<k> DF64 => . ... </k> -<MODE> 2 </MODE> -<OSZ> 0 </OSZ> -<REXW> 0 </REXW> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <EOSZ> _ => 3 </EOSZ> -<DF64> _ => 1 </DF64> -<k> DF64 => . ... </k> -<MODE> 2 </MODE> -<OSZ> 1 </OSZ> -<REXW> 1 </REXW> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <EOSZ> _ => 3 </EOSZ> -<DF64> _ => 1 </DF64> -<k> DF64 => . ... </k> -<MODE> 2 </MODE> -<OSZ> 0 </OSZ> -<REXW> 1 </REXW> +rule <OUTREG> _ => REG_XMM8 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 0 </SIBINDEX> -syntax K ::= "REFINING66" -rule <EOSZ> _ => 1 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> REFINING66 => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_XMM9 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <EOSZ> _ => 2 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> REFINING66 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_XMM10 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <EOSZ> _ => 2 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> REFINING66 => . ... </k> -<MODE> 2 </MODE> -<REXW> 0 </REXW> +rule <OUTREG> _ => REG_XMM11 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <EOSZ> _ => 3 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> REFINING66 => . ... </k> -<MODE> 2 </MODE> -<REXW> 1 </REXW> +rule <OUTREG> _ => REG_XMM12 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> -syntax K ::= "IGNORE66" -rule <EOSZ> _ => 1 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> IGNORE66 => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_XMM13 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <EOSZ> _ => 2 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> IGNORE66 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_XMM14 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <EOSZ> _ => 2 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> IGNORE66 => . ... </k> -<MODE> 2 </MODE> -<REXW> 0 </REXW> +rule <OUTREG> _ => REG_XMM15 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <EOSZ> _ => 3 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> IGNORE66 => . ... </k> -<MODE> 2 </MODE> -<REXW> 1 </REXW> +rule <OUTREG> _ => REG_XMM16 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -syntax K ::= "IMMUNE66" -rule <EOSZ> _ => 2 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> IMMUNE66 => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_XMM17 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <EOSZ> _ => 2 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> IMMUNE66 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_XMM18 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <EOSZ> _ => 2 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> IMMUNE66 => . ... </k> -<MODE> 2 </MODE> -<REXW> 0 </REXW> +rule <OUTREG> _ => REG_XMM19 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <EOSZ> _ => 3 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> IMMUNE66 => . ... </k> -<MODE> 2 </MODE> -<REXW> 1 </REXW> +rule <OUTREG> _ => REG_XMM20 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM21 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM22 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM23 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 7 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM24 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 0 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM25 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM26 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM27 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM28 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM29 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM30 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> + + + +rule <OUTREG> _ => REG_XMM31 </OUTREG> +<k> UISA_VSIB_INDEX_XMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> + + + +syntax K ::= "UIMMv" +rule <IMMWIDTH> _ => 16 </IMMWIDTH> +<k> UIMMv => . ... </k> +<EOSZ> 1 </EOSZ> + + + +rule <IMMWIDTH> _ => 32 </IMMWIDTH> +<k> UIMMv => . ... </k> +<EOSZ> 2 </EOSZ> + + + +rule <IMMWIDTH> _ => 64 </IMMWIDTH> +<k> UIMMv => . ... </k> +<EOSZ> 3 </EOSZ> @@ -133530,235 +134151,227 @@ rule <EOSZ> _ => 3 </EOSZ> -syntax K ::= "IMMUNE66_LOOP64" -rule <k> IMMUNE66_LOOP64 => . ... </k> -<MODE> 0 </MODE> - - +syntax K ::= "YMM_N3_32" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_N3_32 => . ... </k> +<VEXDEST210> 7 </VEXDEST210> -rule <k> IMMUNE66_LOOP64 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_N3_32 => . ... </k> +<VEXDEST210> 6 </VEXDEST210> -rule <EOSZ> _ => 3 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> IMMUNE66_LOOP64 => . ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_N3_32 => . ... </k> +<VEXDEST210> 5 </VEXDEST210> -syntax K ::= "IMMUNE_REXW" -rule <k> IMMUNE_REXW => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_N3_32 => . ... </k> +<VEXDEST210> 4 </VEXDEST210> -rule <k> IMMUNE_REXW => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_N3_32 => . ... </k> +<VEXDEST210> 3 </VEXDEST210> -rule <EOSZ> _ => 2 </EOSZ> -<k> IMMUNE_REXW => . ... </k> -<MODE> 2 </MODE> -<OSZ> 0 </OSZ> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_N3_32 => . ... </k> +<VEXDEST210> 2 </VEXDEST210> -rule <EOSZ> _ => 2 </EOSZ> -<k> IMMUNE_REXW => . ... </k> -<MODE> 2 </MODE> -<OSZ> 1 </OSZ> -<REXW> 1 </REXW> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_N3_32 => . ... </k> +<VEXDEST210> 1 </VEXDEST210> -rule <EOSZ> _ => 1 </EOSZ> -<k> IMMUNE_REXW => . ... </k> -<MODE> 2 </MODE> -<OSZ> 1 </OSZ> -<REXW> 0 </REXW> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_N3_32 => . ... </k> +<VEXDEST210> 0 </VEXDEST210> -syntax K ::= "FORCE64" -rule <EOSZ> _ => 3 </EOSZ> -<OSZ> _ => 0 </OSZ> -<k> FORCE64 => . ... </k> -<MODE> 2 </MODE> +syntax K ::= "YMM_N_32" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_N_32 => . ... </k> +<VEXDEST210> 7 </VEXDEST210> -rule <k> FORCE64 => . ... </k> - [owise] -syntax K ::= "ASZ_NONTERM" -rule <EASZ> _ => 1 </EASZ> -<k> ASZ_NONTERM => . ... </k> -<MODE> 0 </MODE> -<ASZ> 0 </ASZ> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_N_32 => . ... </k> +<VEXDEST210> 6 </VEXDEST210> -rule <EASZ> _ => 2 </EASZ> -<k> ASZ_NONTERM => . ... </k> -<MODE> 0 </MODE> -<ASZ> 1 </ASZ> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_N_32 => . ... </k> +<VEXDEST210> 5 </VEXDEST210> -rule <EASZ> _ => 2 </EASZ> -<k> ASZ_NONTERM => . ... </k> -<MODE> 1 </MODE> -<ASZ> 0 </ASZ> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_N_32 => . ... </k> +<VEXDEST210> 4 </VEXDEST210> -rule <EASZ> _ => 1 </EASZ> -<k> ASZ_NONTERM => . ... </k> -<MODE> 1 </MODE> -<ASZ> 1 </ASZ> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_N_32 => . ... </k> +<VEXDEST210> 3 </VEXDEST210> -rule <EASZ> _ => 3 </EASZ> -<k> ASZ_NONTERM => . ... </k> -<MODE> 2 </MODE> -<ASZ> 0 </ASZ> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_N_32 => . ... </k> +<VEXDEST210> 2 </VEXDEST210> -rule <EASZ> _ => 2 </EASZ> -<k> ASZ_NONTERM => . ... </k> -<MODE> 2 </MODE> -<ASZ> 1 </ASZ> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_N_32 => . ... </k> +<VEXDEST210> 1 </VEXDEST210> -syntax K ::= "ONE" -rule <IMMWIDTH> _ => 8 </IMMWIDTH> -<UIMM0> _ => 1 </UIMM0> -<k> ONE => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_N_32 => . ... </k> +<VEXDEST210> 0 </VEXDEST210> -rule <IMMWIDTH> _ => 8 </IMMWIDTH> -<UIMM0> _ => 1 </UIMM0> -<k> ONE => . ... </k> -<MODE> 1 </MODE> +syntax K ::= "MASK_N64" +rule <OUTREG> _ => REG_K7 </OUTREG> +<k> MASK_N64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <IMMWIDTH> _ => 8 </IMMWIDTH> -<UIMM0> _ => 1 </UIMM0> -<k> ONE => . ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_K6 </OUTREG> +<k> MASK_N64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -syntax K ::= "UIMMv" -rule <IMMWIDTH> _ => 16 </IMMWIDTH> -<k> UIMMv => . ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_K5 </OUTREG> +<k> MASK_N64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <IMMWIDTH> _ => 32 </IMMWIDTH> -<k> UIMMv => . ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_K4 </OUTREG> +<k> MASK_N64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <IMMWIDTH> _ => 64 </IMMWIDTH> -<k> UIMMv => . ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_K3 </OUTREG> +<k> MASK_N64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -syntax K ::= "SIMMz" -rule <IMMWIDTH> _ => 16 </IMMWIDTH> -<IMM0SIGNED> _ => 1 </IMM0SIGNED> -<k> SIMMz => . ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_K2 </OUTREG> +<k> MASK_N64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <IMMWIDTH> _ => 32 </IMMWIDTH> -<IMM0SIGNED> _ => 1 </IMM0SIGNED> -<k> SIMMz => . ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_K1 </OUTREG> +<k> MASK_N64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <IMMWIDTH> _ => 32 </IMMWIDTH> -<IMM0SIGNED> _ => 1 </IMM0SIGNED> -<k> SIMMz => . ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_K0 </OUTREG> +<k> MASK_N64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -syntax K ::= "SIMM8" -rule <IMMWIDTH> _ => 8 </IMMWIDTH> -<IMM0SIGNED> _ => 1 </IMM0SIGNED> -<k> SIMM8 => . ... </k> +syntax K ::= "IMMUNE66_LOOP64" +rule <k> IMMUNE66_LOOP64 => . ... </k> +<MODE> 0 </MODE> -syntax K ::= "UIMM8" -rule <IMMWIDTH> _ => 8 </IMMWIDTH> -<k> UIMM8 => . ... </k> +rule <k> IMMUNE66_LOOP64 => . ... </k> +<MODE> 1 </MODE> -syntax K ::= "UIMM8_1" -rule <HASIMM1> _ => 1 </HASIMM1> -<k> UIMM8_1 => . ... </k> +rule <EOSZ> _ => 3 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> IMMUNE66_LOOP64 => . ... </k> +<MODE> 2 </MODE> -syntax K ::= "UIMM16" -rule <IMMWIDTH> _ => 16 </IMMWIDTH> -<k> UIMM16 => . ... </k> +syntax K ::= "FINAL_DSEG_MODE64" +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> FINAL_DSEG_MODE64 => . ... </k> +<SEGOVD> 0 </SEGOVD> -syntax K ::= "UIMM32" -rule <IMMWIDTH> _ => 32 </IMMWIDTH> -<k> UIMM32 => . ... </k> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_MODE64 => . ... </k> +<SEGOVD> 1 </SEGOVD> -syntax K ::= "BRDISP8" -rule <BRDISPWIDTH> _ => 8 </BRDISPWIDTH> -<k> BRDISP8 => . ... </k> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_MODE64 => . ... </k> +<SEGOVD> 2 </SEGOVD> -syntax K ::= "BRDISP32" -rule <BRDISPWIDTH> _ => 32 </BRDISPWIDTH> -<k> BRDISP32 => . ... </k> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_MODE64 => . ... </k> +<SEGOVD> 3 </SEGOVD> -syntax K ::= "BRDISPz" -rule <BRDISPWIDTH> _ => 16 </BRDISPWIDTH> -<k> BRDISPz => . ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_FS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_MODE64 => . ... </k> +<SEGOVD> 4 </SEGOVD> -rule <BRDISPWIDTH> _ => 32 </BRDISPWIDTH> -<k> BRDISPz => . ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_GS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_MODE64 => . ... </k> +<SEGOVD> 5 </SEGOVD> -rule <BRDISPWIDTH> _ => 32 </BRDISPWIDTH> -<k> BRDISPz => . ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_MODE64 => . ... </k> +<SEGOVD> 6 </SEGOVD> @@ -133781,4870 +134394,5015 @@ rule <DISPWIDTH> _ => 64 </DISPWIDTH> -syntax K ::= "MEMDISP32" -rule <DISPWIDTH> _ => 32 </DISPWIDTH> -<k> MEMDISP32 => . ... </k> +syntax K ::= "YMM_R3_32" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_R3_32 => . ... </k> +<REG> 0 </REG> -syntax K ::= "MEMDISP16" -rule <DISPWIDTH> _ => 16 </DISPWIDTH> -<k> MEMDISP16 => . ... </k> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_R3_32 => . ... </k> +<REG> 1 </REG> -syntax K ::= "MEMDISP8" -rule <DISPWIDTH> _ => 8 </DISPWIDTH> -<k> MEMDISP8 => . ... </k> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_R3_32 => . ... </k> +<REG> 2 </REG> -syntax K ::= "MEMDISP" -rule <DISPWIDTH> _ => 0 </DISPWIDTH> -<k> MEMDISP => . ... </k> -<NEEDMEMDISP> 0 </NEEDMEMDISP> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_R3_32 => . ... </k> +<REG> 3 </REG> -rule <DISPWIDTH> _ => 8 </DISPWIDTH> -<k> MEMDISP => . ... </k> -<NEEDMEMDISP> 8 </NEEDMEMDISP> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_R3_32 => . ... </k> +<REG> 4 </REG> -rule <DISPWIDTH> _ => 16 </DISPWIDTH> -<k> MEMDISP => . ... </k> -<NEEDMEMDISP> 16 </NEEDMEMDISP> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_R3_32 => . ... </k> +<REG> 5 </REG> -rule <DISPWIDTH> _ => 32 </DISPWIDTH> -<k> MEMDISP => . ... </k> -<NEEDMEMDISP> 32 </NEEDMEMDISP> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_R3_32 => . ... </k> +<REG> 6 </REG> -syntax K ::= "MODRM" -rule <k> MODRM => MODRM64alt32 ~> MEMDISP ... </k> -<MODE> 2 </MODE> -<EASZ> 3 </EASZ> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_R3_32 => . ... </k> +<REG> 7 </REG> -rule <k> MODRM => MODRM64alt32 ~> MEMDISP ... </k> -<MODE> 2 </MODE> -<EASZ> 2 </EASZ> +syntax K ::= "A_GPR_R" +rule <k> A_GPR_R => ArAX ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <k> MODRM => MODRM32 ~> MEMDISP ... </k> -<MODE> 1 </MODE> -<EASZ> 2 </EASZ> +rule <k> A_GPR_R => ArCX ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <k> MODRM => MODRM16 ~> MEMDISP ... </k> -<MODE> 1 </MODE> -<EASZ> 1 </EASZ> +rule <k> A_GPR_R => ArDX ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <k> MODRM => MODRM32 ~> MEMDISP ... </k> -<MODE> 0 </MODE> -<EASZ> 2 </EASZ> +rule <k> A_GPR_R => ArBX ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <k> MODRM => MODRM16 ~> MEMDISP ... </k> -<MODE> 0 </MODE> -<EASZ> 1 </EASZ> +rule <k> A_GPR_R => ArSP ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> -syntax K ::= "MODRM64alt32" -rule <k> MODRM64alt32 => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 0 </MOD> -<RM> 0 </RM> +rule <k> A_GPR_R => ArBP ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <k> MODRM64alt32 => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 0 </MOD> -<RM> 0 </RM> +rule <k> A_GPR_R => ArSI ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <k> MODRM64alt32 => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 0 </MOD> -<RM> 1 </RM> +rule <k> A_GPR_R => ArDI ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <k> MODRM64alt32 => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 0 </MOD> -<RM> 1 </RM> +rule <k> A_GPR_R => Ar8 ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <k> MODRM64alt32 => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 0 </MOD> -<RM> 2 </RM> +rule <k> A_GPR_R => Ar9 ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <k> MODRM64alt32 => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 0 </MOD> -<RM> 2 </RM> +rule <k> A_GPR_R => Ar10 ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <k> MODRM64alt32 => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 0 </MOD> -<RM> 3 </RM> +rule <k> A_GPR_R => Ar11 ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <k> MODRM64alt32 => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 0 </MOD> -<RM> 3 </RM> +rule <k> A_GPR_R => Ar12 ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <k> MODRM64alt32 => SIB ... </k> -<REXB> 0 </REXB> -<MOD> 0 </MOD> -<RM> 4 </RM> +rule <k> A_GPR_R => Ar13 ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <k> MODRM64alt32 => SIB ... </k> -<REXB> 1 </REXB> -<MOD> 0 </MOD> -<RM> 4 </RM> +rule <k> A_GPR_R => Ar14 ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> MODRM64alt32 => rIPa ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 0 </MOD> -<RM> 5 </RM> +rule <k> A_GPR_R => Ar15 ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => rIPa ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 0 </MOD> -<RM> 5 </RM> +syntax K ::= "BND_R_CHECK" +rule <k> BND_R_CHECK => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <k> MODRM64alt32 => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 0 </MOD> -<RM> 6 </RM> +rule <k> BND_R_CHECK => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <k> MODRM64alt32 => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 0 </MOD> -<RM> 6 </RM> +rule <k> BND_R_CHECK => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <k> MODRM64alt32 => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 0 </MOD> -<RM> 7 </RM> +rule <k> BND_R_CHECK => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <k> MODRM64alt32 => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 0 </MOD> -<RM> 7 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 1 </MOD> -<RM> 0 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 1 </MOD> -<RM> 0 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 1 </MOD> -<RM> 1 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 1 </MOD> -<RM> 1 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 1 </MOD> -<RM> 2 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 1 </MOD> -<RM> 2 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 1 </MOD> -<RM> 3 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 1 </MOD> -<RM> 3 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => SIB ... </k> -<REXB> 0 </REXB> -<MOD> 1 </MOD> -<RM> 4 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => SIB ... </k> -<REXB> 1 </REXB> -<MOD> 1 </MOD> -<RM> 4 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 1 </MOD> -<RM> 5 </RM> +rule <k> BND_R_CHECK => DecoderError ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 1 </MOD> -<RM> 5 </RM> +syntax K ::= "XMM_N_64" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 1 </MOD> -<RM> 6 </RM> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 1 </MOD> -<RM> 6 </RM> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 1 </MOD> -<RM> 7 </RM> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 1 </MOD> -<RM> 7 </RM> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 2 </MOD> -<RM> 0 </RM> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 2 </MOD> -<RM> 0 </RM> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 2 </MOD> -<RM> 1 </RM> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 2 </MOD> -<RM> 1 </RM> +rule <OUTREG> _ => REG_XMM8 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 2 </MOD> -<RM> 2 </RM> +rule <OUTREG> _ => REG_XMM9 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 2 </MOD> -<RM> 2 </RM> +rule <OUTREG> _ => REG_XMM10 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 2 </MOD> -<RM> 3 </RM> +rule <OUTREG> _ => REG_XMM11 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 2 </MOD> -<RM> 3 </RM> +rule <OUTREG> _ => REG_XMM12 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => SIB ... </k> -<REXB> 0 </REXB> -<MOD> 2 </MOD> -<RM> 4 </RM> +rule <OUTREG> _ => REG_XMM13 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => SIB ... </k> -<REXB> 1 </REXB> -<MOD> 2 </MOD> -<RM> 4 </RM> +rule <OUTREG> _ => REG_XMM14 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 2 </MOD> -<RM> 5 </RM> +rule <OUTREG> _ => REG_XMM15 </OUTREG> +<k> XMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 2 </MOD> -<RM> 5 </RM> +syntax K ::= "FINAL_DSEG1_NOT64" +rule <OUTREG> _ => REG_CS </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_NOT64 => . ... </k> +<SEGOVD> 1 </SEGOVD> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 2 </MOD> -<RM> 6 </RM> +rule <OUTREG> _ => REG_ES </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_NOT64 => . ... </k> +<SEGOVD> 3 </SEGOVD> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 2 </MOD> -<RM> 6 </RM> +rule <OUTREG> _ => REG_FS </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_NOT64 => . ... </k> +<SEGOVD> 4 </SEGOVD> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<MOD> 2 </MOD> -<RM> 7 </RM> +rule <OUTREG> _ => REG_GS </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_NOT64 => . ... </k> +<SEGOVD> 5 </SEGOVD> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM64alt32 => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<MOD> 2 </MOD> -<RM> 7 </RM> +rule <OUTREG> _ => REG_SS </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 0 </USINGDEFAULTSEGMENT1> +<k> FINAL_DSEG1_NOT64 => . ... </k> +<SEGOVD> 6 </SEGOVD> -syntax K ::= "MODRM32" -rule <BASE0> _ => REG_EAX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +syntax K ::= "XMM_B_32" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_B_32 => . ... </k> <RM> 0 </RM> -rule <BASE0> _ => REG_ECX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_B_32 => . ... </k> <RM> 1 </RM> -rule <BASE0> _ => REG_EDX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_B_32 => . ... </k> <RM> 2 </RM> -rule <BASE0> _ => REG_EBX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_B_32 => . ... </k> <RM> 3 </RM> -rule <k> MODRM32 => SIB ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_B_32 => . ... </k> <RM> 4 </RM> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_B_32 => . ... </k> <RM> 5 </RM> -rule <BASE0> _ => REG_ESI </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_B_32 => . ... </k> <RM> 6 </RM> -rule <BASE0> _ => REG_EDI </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_B_32 => . ... </k> <RM> 7 </RM> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_EAX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> -<RM> 0 </RM> - - - -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_ECX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> -<RM> 1 </RM> +syntax K ::= "Ar15" +rule <OUTREG> _ => REG_R15W </OUTREG> +<k> Ar15 => . ... </k> +<EASZ> 1 </EASZ> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_EDX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> -<RM> 2 </RM> +rule <OUTREG> _ => REG_R15D </OUTREG> +<k> Ar15 => . ... </k> +<EASZ> 2 </EASZ> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_EBX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> -<RM> 3 </RM> +rule <OUTREG> _ => REG_R15 </OUTREG> +<k> Ar15 => . ... </k> +<EASZ> 3 </EASZ> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<k> MODRM32 => SIB ... </k> -<MOD> 1 </MOD> -<RM> 4 </RM> +syntax K ::= "SIMM8" +rule <IMMWIDTH> _ => 8 </IMMWIDTH> +<IMM0SIGNED> _ => 1 </IMM0SIGNED> +<k> SIMM8 => . ... </k> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_EBP </BASE0> -<k> MODRM32 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> -<RM> 5 </RM> +syntax K ::= "OSZ_NONTERM" +rule <EOSZ> _ => 1 </EOSZ> +<k> OSZ_NONTERM => . ... </k> +<MODE> 0 </MODE> +<OSZ> 0 </OSZ> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_ESI </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> -<RM> 6 </RM> +rule <EOSZ> _ => 2 </EOSZ> +<k> OSZ_NONTERM => . ... </k> +<MODE> 0 </MODE> +<OSZ> 1 </OSZ> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_EDI </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> -<RM> 7 </RM> +rule <EOSZ> _ => 1 </EOSZ> +<k> OSZ_NONTERM => . ... </k> +<MODE> 1 </MODE> +<OSZ> 1 </OSZ> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<BASE0> _ => REG_EAX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 0 </RM> +rule <EOSZ> _ => 2 </EOSZ> +<k> OSZ_NONTERM => . ... </k> +<MODE> 1 </MODE> +<OSZ> 0 </OSZ> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<BASE0> _ => REG_ECX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 1 </RM> +rule <EOSZ> _ => 1 </EOSZ> +<k> OSZ_NONTERM => . ... </k> +<MODE> 2 </MODE> +<OSZ> 1 </OSZ> +<REXW> 0 </REXW> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<BASE0> _ => REG_EDX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 2 </RM> +rule <EOSZ> _ => 2 </EOSZ> +<k> OSZ_NONTERM => . ... </k> +<MODE> 2 </MODE> +<OSZ> 0 </OSZ> +<REXW> 0 </REXW> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<BASE0> _ => REG_EBX </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 3 </RM> +rule <EOSZ> _ => 3 </EOSZ> +<k> OSZ_NONTERM => . ... </k> +<MODE> 2 </MODE> +<OSZ> 1 </OSZ> +<REXW> 1 </REXW> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<k> MODRM32 => SIB ... </k> -<MOD> 2 </MOD> -<RM> 4 </RM> +rule <EOSZ> _ => 3 </EOSZ> +<k> OSZ_NONTERM => . ... </k> +<MODE> 2 </MODE> +<OSZ> 0 </OSZ> +<REXW> 1 </REXW> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<BASE0> _ => REG_EBP </BASE0> -<k> MODRM32 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 5 </RM> +syntax K ::= "NELEM_GPR_READER_WORD" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_READER_WORD => . ... </k> +<VL> 0 </VL> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<BASE0> _ => REG_ESI </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 6 </RM> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_READER_WORD => . ... </k> +<VL> 1 </VL> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<BASE0> _ => REG_EDI </BASE0> -<k> MODRM32 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 7 </RM> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_READER_WORD => . ... </k> +<VL> 2 </VL> -syntax K ::= "MODRM16" -rule <BASE0> _ => REG_BX </BASE0> -<INDEX> _ => REG_SI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +syntax K ::= "BND_B" +rule <OUTREG> _ => REG_BND0 </OUTREG> +<k> BND_B => . ... </k> +<REXB> 0 </REXB> <RM> 0 </RM> -rule <BASE0> _ => REG_BX </BASE0> -<INDEX> _ => REG_DI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_BND1 </OUTREG> +<k> BND_B => . ... </k> +<REXB> 0 </REXB> <RM> 1 </RM> -rule <BASE0> _ => REG_BP </BASE0> -<INDEX> _ => REG_SI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_BND2 </OUTREG> +<k> BND_B => . ... </k> +<REXB> 0 </REXB> <RM> 2 </RM> -rule <BASE0> _ => REG_BP </BASE0> -<INDEX> _ => REG_DI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_BND3 </OUTREG> +<k> BND_B => . ... </k> +<REXB> 0 </REXB> <RM> 3 </RM> -rule <BASE0> _ => REG_SI </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> BND_B => . ... </k> +<REXB> 0 </REXB> <RM> 4 </RM> -rule <BASE0> _ => REG_DI </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 0 </REXB> <RM> 5 </RM> -rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> -<BASE0> _ => REG_INVALID </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 0 </REXB> <RM> 6 </RM> -rule <BASE0> _ => REG_BX </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 0 </REXB> <RM> 7 </RM> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_BX </BASE0> -<INDEX> _ => REG_SI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 1 </REXB> <RM> 0 </RM> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_BX </BASE0> -<INDEX> _ => REG_DI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 1 </REXB> <RM> 1 </RM> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_BP </BASE0> -<INDEX> _ => REG_SI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 1 </REXB> <RM> 2 </RM> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_BP </BASE0> -<INDEX> _ => REG_DI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 1 </REXB> <RM> 3 </RM> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_SI </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 1 </REXB> <RM> 4 </RM> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_DI </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 1 </REXB> <RM> 5 </RM> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_BP </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 1 </REXB> <RM> 6 </RM> -rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> -<BASE0> _ => REG_BX </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_B => . ... </k> +<REXB> 1 </REXB> <RM> 7 </RM> -rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> -<BASE0> _ => REG_BX </BASE0> -<INDEX> _ => REG_SI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 0 </RM> +syntax K ::= "ESIZE_4_BITS" +rule <ELEMENTSIZE> _ => 4 </ELEMENTSIZE> +<k> ESIZE_4_BITS => . ... </k> +<REX> 0 </REX> -rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> -<BASE0> _ => REG_BX </BASE0> -<INDEX> _ => REG_DI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 1 </RM> +syntax K ::= "YMM_N" +rule <k> YMM_N => YMM_N_32 ... </k> +<MODE> 0 </MODE> -rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> -<BASE0> _ => REG_BP </BASE0> -<INDEX> _ => REG_SI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 2 </RM> +rule <k> YMM_N => YMM_N_32 ... </k> +<MODE> 1 </MODE> -rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> -<BASE0> _ => REG_BP </BASE0> -<INDEX> _ => REG_DI </INDEX> -<SCALE> _ => 1 </SCALE> -<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 3 </RM> +rule <k> YMM_N => YMM_N_64 ... </k> +<MODE> 2 </MODE> -rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> -<BASE0> _ => REG_SI </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 4 </RM> +syntax K ::= "GPRv_R" +rule <k> GPRv_R => GPR64_R ... </k> +<EOSZ> 3 </EOSZ> -rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> -<BASE0> _ => REG_DI </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 5 </RM> +rule <k> GPRv_R => GPR32_R ... </k> +<EOSZ> 2 </EOSZ> -rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> -<BASE0> _ => REG_BP </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<MOD> 2 </MOD> -<RM> 6 </RM> +rule <k> GPRv_R => GPR16_R ... </k> +<EOSZ> 1 </EOSZ> -rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> -<BASE0> _ => REG_BX </BASE0> -<INDEX> _ => REG_INVALID </INDEX> -<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +syntax K ::= "UISA_VMODRM_XMM" +rule <k> UISA_VMODRM_XMM => UISA_VSIB_XMM ... </k> +<MOD> 0 </MOD> + + + +rule <k> UISA_VMODRM_XMM => UISA_VSIB_XMM ~> MEMDISP8 ... </k> +<MOD> 1 </MOD> + + + +rule <k> UISA_VMODRM_XMM => UISA_VSIB_XMM ~> MEMDISP32 ... </k> <MOD> 2 </MOD> -<RM> 7 </RM> -syntax K ::= "SIB" -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> ArAX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 0 </SIBINDEX> -<REXX> 0 </REXX> +syntax K ::= "XMM_N3_32" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_N3_32 => . ... </k> +<VEXDEST210> 7 </VEXDEST210> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar8 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 0 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_N3_32 => . ... </k> +<VEXDEST210> 6 </VEXDEST210> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> ArCX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 1 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_N3_32 => . ... </k> +<VEXDEST210> 5 </VEXDEST210> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar9 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 1 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_N3_32 => . ... </k> +<VEXDEST210> 4 </VEXDEST210> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> ArDX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 2 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_N3_32 => . ... </k> +<VEXDEST210> 3 </VEXDEST210> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar10 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 2 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_N3_32 => . ... </k> +<VEXDEST210> 2 </VEXDEST210> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> ArBX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 3 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_N3_32 => . ... </k> +<VEXDEST210> 1 </VEXDEST210> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar11 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 3 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_N3_32 => . ... </k> +<VEXDEST210> 0 </VEXDEST210> -rule <INDEX> _ => REG_INVALID </INDEX> -<SCALE> _ => 1 </SCALE> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> SIB => SIB_BASE0 ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 4 </SIBINDEX> +syntax K ::= "GPR64_X" +rule <OUTREG> _ => REG_RAX </OUTREG> +<k> GPR64_X => . ... </k> <REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar12 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 4 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_RCX </OUTREG> +<k> GPR64_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> ArBP ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_RDX </OUTREG> +<k> GPR64_X => . ... </k> <REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar13 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 5 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_RBX </OUTREG> +<k> GPR64_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> ArSI ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<k> GPR64_X => . ... </k> <REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar14 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 6 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_RBP </OUTREG> +<k> GPR64_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> ArDI ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_RSI </OUTREG> +<k> GPR64_X => . ... </k> <REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar15 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> +rule <OUTREG> _ => REG_RDI </OUTREG> +<k> GPR64_X => . ... </k> +<REXX> 0 </REXX> <SIBINDEX> 7 </SIBINDEX> -<REXX> 1 </REXX> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> ArAX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> +rule <OUTREG> _ => REG_R8 </OUTREG> +<k> GPR64_X => . ... </k> +<REXX> 1 </REXX> <SIBINDEX> 0 </SIBINDEX> -<REXX> 0 </REXX> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar8 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 0 </SIBINDEX> +rule <OUTREG> _ => REG_R9 </OUTREG> +<k> GPR64_X => . ... </k> <REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> ArCX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 1 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_R10 </OUTREG> +<k> GPR64_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar9 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 1 </SIBINDEX> +rule <OUTREG> _ => REG_R11 </OUTREG> +<k> GPR64_X => . ... </k> <REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> ArDX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 2 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_R12 </OUTREG> +<k> GPR64_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar10 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_R13 </OUTREG> +<k> GPR64_X => . ... </k> <REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> ArBX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 3 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_R14 </OUTREG> +<k> GPR64_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar11 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_R15 </OUTREG> +<k> GPR64_X => . ... </k> <REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <INDEX> _ => REG_INVALID </INDEX> -<SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 4 </SIBINDEX> -<REXX> 0 </REXX> +syntax K ::= "YMM_B3_32" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_B3_32 => . ... </k> +<RM> 0 </RM> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar12 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 4 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_B3_32 => . ... </k> +<RM> 1 </RM> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> ArBP ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 5 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_B3_32 => . ... </k> +<RM> 2 </RM> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar13 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 5 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_B3_32 => . ... </k> +<RM> 3 </RM> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> ArSI ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 6 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_B3_32 => . ... </k> +<RM> 4 </RM> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar14 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 6 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_B3_32 => . ... </k> +<RM> 5 </RM> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> ArDI ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 7 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_B3_32 => . ... </k> +<RM> 6 </RM> -rule <SCALE> _ => 2 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar15 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> -<SIBINDEX> 7 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_B3_32 => . ... </k> +<RM> 7 </RM> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> ArAX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 0 </SIBINDEX> -<REXX> 0 </REXX> +syntax K ::= "ESIZE_16_BITS" +rule <ELEMENTSIZE> _ => 16 </ELEMENTSIZE> +<k> ESIZE_16_BITS => . ... </k> +<REX> 0 </REX> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar8 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 0 </SIBINDEX> -<REXX> 1 </REXX> +syntax K ::= "ZMM_B3_32" +rule <OUTREG> _ => REG_ZMM0 </OUTREG> +<k> ZMM_B3_32 => . ... </k> +<RM> 0 </RM> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> ArCX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 1 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ZMM1 </OUTREG> +<k> ZMM_B3_32 => . ... </k> +<RM> 1 </RM> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar9 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 1 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ZMM2 </OUTREG> +<k> ZMM_B3_32 => . ... </k> +<RM> 2 </RM> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> ArDX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 2 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ZMM3 </OUTREG> +<k> ZMM_B3_32 => . ... </k> +<RM> 3 </RM> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar10 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 2 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ZMM4 </OUTREG> +<k> ZMM_B3_32 => . ... </k> +<RM> 4 </RM> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> ArBX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 3 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ZMM5 </OUTREG> +<k> ZMM_B3_32 => . ... </k> +<RM> 5 </RM> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar11 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 3 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ZMM6 </OUTREG> +<k> ZMM_B3_32 => . ... </k> +<RM> 6 </RM> -rule <INDEX> _ => REG_INVALID </INDEX> -<SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 4 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM7 </OUTREG> +<k> ZMM_B3_32 => . ... </k> +<RM> 7 </RM> + + + +syntax K ::= "UISA_VSIB_INDEX_ZMM" +rule <OUTREG> _ => REG_ZMM0 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> <REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar12 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 4 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ZMM1 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> ArBP ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM2 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> <REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar13 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 5 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ZMM3 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> ArSI ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM4 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> <REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar14 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 6 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ZMM5 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> ArDI ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM6 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> <REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <SCALE> _ => 4 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar15 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> +rule <OUTREG> _ => REG_ZMM7 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 0 </REXX> <SIBINDEX> 7 </SIBINDEX> -<REXX> 1 </REXX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> ArAX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> +rule <OUTREG> _ => REG_ZMM8 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> <SIBINDEX> 0 </SIBINDEX> -<REXX> 0 </REXX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar8 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 0 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM9 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> <REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> ArCX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 1 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ZMM10 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar9 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 1 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM11 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> <REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> ArDX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 2 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ZMM12 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar10 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM13 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> <REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> ArBX ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 3 </SIBINDEX> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ZMM14 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar11 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM15 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 0 </VEXDEST4> <REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <INDEX> _ => REG_INVALID </INDEX> -<SCALE> _ => 1 </SCALE> -<k> SIB => SIB_BASE0 ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 4 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM16 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> <REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar12 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 4 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ZMM17 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> ArBP ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM18 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> <REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar13 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 5 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ZMM19 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> ArSI ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM20 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> <REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar14 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 6 </SIBINDEX> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ZMM21 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> ArDI ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_ZMM22 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> <REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <SCALE> _ => 8 </SCALE> -<k> SIB => SIB_BASE0 ~> Ar15 ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> +rule <OUTREG> _ => REG_ZMM23 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 0 </REXX> <SIBINDEX> 7 </SIBINDEX> + + + +rule <OUTREG> _ => REG_ZMM24 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> <REXX> 1 </REXX> +<SIBINDEX> 0 </SIBINDEX> -syntax K ::= "SIB_BASE0" -rule <k> SIB_BASE0 => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 0 </SIBBASE> +rule <OUTREG> _ => REG_ZMM25 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <k> SIB_BASE0 => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 0 </SIBBASE> +rule <OUTREG> _ => REG_ZMM26 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <k> SIB_BASE0 => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 1 </SIBBASE> +rule <OUTREG> _ => REG_ZMM27 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <k> SIB_BASE0 => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 1 </SIBBASE> +rule <OUTREG> _ => REG_ZMM28 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <k> SIB_BASE0 => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 2 </SIBBASE> +rule <OUTREG> _ => REG_ZMM29 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <k> SIB_BASE0 => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 2 </SIBBASE> +rule <OUTREG> _ => REG_ZMM30 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <k> SIB_BASE0 => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 3 </SIBBASE> +rule <OUTREG> _ => REG_ZMM31 </OUTREG> +<k> UISA_VSIB_INDEX_ZMM => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <k> SIB_BASE0 => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 3 </SIBBASE> +syntax K ::= "YMM_SE64" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 0 </ESRC> -rule <k> SIB_BASE0 => ArSP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 4 </SIBBASE> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 1 </ESRC> -rule <k> SIB_BASE0 => Ar12 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 4 </SIBBASE> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 2 </ESRC> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<BASE0> _ => REG_INVALID </BASE0> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> SIB_BASE0 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 3 </ESRC> -rule <DISPWIDTH> _ => 8 </DISPWIDTH> -<k> SIB_BASE0 => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 4 </ESRC> -rule <DISPWIDTH> _ => 32 </DISPWIDTH> -<k> SIB_BASE0 => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 2 </MOD> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 5 </ESRC> -rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> -<BASE0> _ => REG_INVALID </BASE0> -<k> SIB_BASE0 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 6 </ESRC> -rule <DISPWIDTH> _ => 8 </DISPWIDTH> -<k> SIB_BASE0 => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 7 </ESRC> -rule <DISPWIDTH> _ => 32 </DISPWIDTH> -<k> SIB_BASE0 => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 2 </MOD> +rule <OUTREG> _ => REG_YMM8 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 8 </ESRC> -rule <k> SIB_BASE0 => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 6 </SIBBASE> +rule <OUTREG> _ => REG_YMM9 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 9 </ESRC> -rule <k> SIB_BASE0 => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 6 </SIBBASE> +rule <OUTREG> _ => REG_YMM10 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 10 </ESRC> -rule <k> SIB_BASE0 => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 7 </SIBBASE> +rule <OUTREG> _ => REG_YMM11 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 11 </ESRC> -rule <k> SIB_BASE0 => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 7 </SIBBASE> +rule <OUTREG> _ => REG_YMM12 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 12 </ESRC> -syntax K ::= "OVERRIDE_SEG0" -rule <k> OVERRIDE_SEG0 => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_YMM13 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 13 </ESRC> -rule <k> OVERRIDE_SEG0 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_YMM14 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 14 </ESRC> -rule <k> OVERRIDE_SEG0 => . ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_YMM15 </OUTREG> +<k> YMM_SE64 => . ... </k> +<ESRC> 15 </ESRC> -syntax K ::= "OVERRIDE_SEG1" -rule <k> OVERRIDE_SEG1 => . ... </k> -<MODE> 0 </MODE> +syntax K ::= "XMM_SE64" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 0 </ESRC> -rule <k> OVERRIDE_SEG1 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 1 </ESRC> -rule <k> OVERRIDE_SEG1 => . ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 2 </ESRC> -syntax K ::= "XMM_R" -rule <k> XMM_R => XMM_R_32 ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 3 </ESRC> -rule <k> XMM_R => XMM_R_32 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 4 </ESRC> -rule <k> XMM_R => XMM_R_64 ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 5 </ESRC> -syntax K ::= "XMM_R_32" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_R_32 => . ... </k> -<REG> 0 </REG> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 6 </ESRC> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_R_32 => . ... </k> -<REG> 1 </REG> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 7 </ESRC> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_R_32 => . ... </k> -<REG> 2 </REG> +rule <OUTREG> _ => REG_XMM8 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 8 </ESRC> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_R_32 => . ... </k> -<REG> 3 </REG> +rule <OUTREG> _ => REG_XMM9 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 9 </ESRC> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_R_32 => . ... </k> -<REG> 4 </REG> +rule <OUTREG> _ => REG_XMM10 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 10 </ESRC> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_R_32 => . ... </k> -<REG> 5 </REG> +rule <OUTREG> _ => REG_XMM11 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 11 </ESRC> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_R_32 => . ... </k> -<REG> 6 </REG> +rule <OUTREG> _ => REG_XMM12 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 12 </ESRC> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_R_32 => . ... </k> -<REG> 7 </REG> +rule <OUTREG> _ => REG_XMM13 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 13 </ESRC> -syntax K ::= "XMM_R_64" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_XMM14 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 14 </ESRC> + + + +rule <OUTREG> _ => REG_XMM15 </OUTREG> +<k> XMM_SE64 => . ... </k> +<ESRC> 15 </ESRC> + + + +syntax K ::= "ZMM_B3" +rule <k> ZMM_B3 => ZMM_B3_32 ... </k> +<MODE> 0 </MODE> + + + +rule <k> ZMM_B3 => ZMM_B3_32 ... </k> +<MODE> 1 </MODE> + + + +rule <k> ZMM_B3 => ZMM_B3_64 ... </k> +<MODE> 2 </MODE> + + + +syntax K ::= "UISA_VSIB_YMM" +rule <SCALE> _ => 1 </SCALE> +<k> UISA_VSIB_YMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> + + + +rule <SCALE> _ => 2 </SCALE> +<k> UISA_VSIB_YMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> + + + +rule <SCALE> _ => 4 </SCALE> +<k> UISA_VSIB_YMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> + + + +rule <SCALE> _ => 8 </SCALE> +<k> UISA_VSIB_YMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> + + + +syntax K ::= "VGPR32_R_64" +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 0 </REXR> <REG> 0 </REG> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 0 </REXR> <REG> 1 </REG> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 0 </REXR> <REG> 2 </REG> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 0 </REXR> <REG> 3 </REG> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 0 </REXR> <REG> 4 </REG> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 0 </REXR> <REG> 5 </REG> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 0 </REXR> <REG> 6 </REG> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 0 </REXR> <REG> 7 </REG> -rule <OUTREG> _ => REG_XMM8 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_R8D </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 1 </REXR> <REG> 0 </REG> -rule <OUTREG> _ => REG_XMM9 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_R9D </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 1 </REXR> <REG> 1 </REG> -rule <OUTREG> _ => REG_XMM10 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_R10D </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 1 </REXR> <REG> 2 </REG> -rule <OUTREG> _ => REG_XMM11 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_R11D </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 1 </REXR> <REG> 3 </REG> -rule <OUTREG> _ => REG_XMM12 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_R12D </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 1 </REXR> <REG> 4 </REG> -rule <OUTREG> _ => REG_XMM13 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_R13D </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 1 </REXR> <REG> 5 </REG> -rule <OUTREG> _ => REG_XMM14 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_R14D </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 1 </REXR> <REG> 6 </REG> -rule <OUTREG> _ => REG_XMM15 </OUTREG> -<k> XMM_R_64 => . ... </k> +rule <OUTREG> _ => REG_R15D </OUTREG> +<k> VGPR32_R_64 => . ... </k> <REXR> 1 </REXR> <REG> 7 </REG> -syntax K ::= "XMM_B" -rule <k> XMM_B => XMM_B_32 ... </k> -<MODE> 0 </MODE> +syntax K ::= "MASK_N32" +rule <OUTREG> _ => REG_K7 </OUTREG> +<k> MASK_N32 => . ... </k> +<VEXDEST210> 0 </VEXDEST210> -rule <k> XMM_B => XMM_B_32 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_K6 </OUTREG> +<k> MASK_N32 => . ... </k> +<VEXDEST210> 1 </VEXDEST210> -rule <k> XMM_B => XMM_B_64 ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_K5 </OUTREG> +<k> MASK_N32 => . ... </k> +<VEXDEST210> 2 </VEXDEST210> -syntax K ::= "XMM_B_32" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_B_32 => . ... </k> -<RM> 0 </RM> +rule <OUTREG> _ => REG_K4 </OUTREG> +<k> MASK_N32 => . ... </k> +<VEXDEST210> 3 </VEXDEST210> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_B_32 => . ... </k> -<RM> 1 </RM> +rule <OUTREG> _ => REG_K3 </OUTREG> +<k> MASK_N32 => . ... </k> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_B_32 => . ... </k> -<RM> 2 </RM> +rule <OUTREG> _ => REG_K2 </OUTREG> +<k> MASK_N32 => . ... </k> +<VEXDEST210> 5 </VEXDEST210> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_B_32 => . ... </k> -<RM> 3 </RM> +rule <OUTREG> _ => REG_K1 </OUTREG> +<k> MASK_N32 => . ... </k> +<VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_B_32 => . ... </k> -<RM> 4 </RM> +rule <OUTREG> _ => REG_K0 </OUTREG> +<k> MASK_N32 => . ... </k> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_B_32 => . ... </k> -<RM> 5 </RM> +syntax K ::= "OrAX" +rule <OUTREG> _ => REG_AX </OUTREG> +<k> OrAX => . ... </k> +<EOSZ> 1 </EOSZ> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_B_32 => . ... </k> -<RM> 6 </RM> +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> OrAX => . ... </k> +<EOSZ> 2 </EOSZ> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_B_32 => . ... </k> -<RM> 7 </RM> +rule <OUTREG> _ => REG_RAX </OUTREG> +<k> OrAX => . ... </k> +<EOSZ> 3 </EOSZ> -syntax K ::= "XMM_B_64" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 0 </RM> +syntax K ::= "SIB" +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> ArAX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 0 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 1 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar8 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 0 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 2 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> ArCX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 1 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 3 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar9 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 1 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 4 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> ArDX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 2 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 5 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar10 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 2 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 6 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> ArBX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 3 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 7 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar11 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 3 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_XMM8 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 0 </RM> +rule <INDEX> _ => REG_INVALID </INDEX> +<SCALE> _ => 1 </SCALE> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> SIB => SIB_BASE0 ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 4 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_XMM9 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 1 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar12 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 4 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_XMM10 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 2 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> ArBP ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 5 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_XMM11 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 3 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar13 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 5 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_XMM12 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 4 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> ArSI ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 6 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_XMM13 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 5 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar14 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 6 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_XMM14 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 6 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> ArDI ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 7 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_XMM15 </OUTREG> -<k> XMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 7 </RM> +rule <SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar15 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> +<SIBINDEX> 7 </SIBINDEX> +<REXX> 1 </REXX> -syntax K ::= "BND_R_CHECK" -rule <k> BND_R_CHECK => . ... </k> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> ArAX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 0 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_R_CHECK => . ... </k> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar8 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 0 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_R_CHECK => . ... </k> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> ArCX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 1 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_R_CHECK => . ... </k> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar9 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 1 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> ArDX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 2 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar10 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 2 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> ArBX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 3 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar11 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 3 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <INDEX> _ => REG_INVALID </INDEX> +<SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 4 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar12 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 4 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> ArBP ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 5 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar13 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 5 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> ArSI ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 6 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar14 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 6 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> ArDI ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 7 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_R_CHECK => DecoderError ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <SCALE> _ => 2 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar15 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> +<SIBINDEX> 7 </SIBINDEX> +<REXX> 1 </REXX> -syntax K ::= "BND_B_CHECK" -rule <k> BND_B_CHECK => . ... </k> -<REXB> 0 </REXB> -<RM> 0 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> ArAX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 0 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_B_CHECK => . ... </k> -<REXB> 0 </REXB> -<RM> 1 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar8 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 0 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_B_CHECK => . ... </k> -<REXB> 0 </REXB> -<RM> 2 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> ArCX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 1 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_B_CHECK => . ... </k> -<REXB> 0 </REXB> -<RM> 3 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar9 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 1 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 0 </REXB> -<RM> 4 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> ArDX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 2 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 0 </REXB> -<RM> 5 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar10 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 2 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 0 </REXB> -<RM> 6 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> ArBX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 3 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 0 </REXB> -<RM> 7 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar11 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 3 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 1 </REXB> -<RM> 0 </RM> +rule <INDEX> _ => REG_INVALID </INDEX> +<SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 4 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 1 </REXB> -<RM> 1 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar12 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 4 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 1 </REXB> -<RM> 2 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> ArBP ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 5 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 1 </REXB> -<RM> 3 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar13 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 5 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 1 </REXB> -<RM> 4 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> ArSI ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 6 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 1 </REXB> -<RM> 5 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar14 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 6 </SIBINDEX> +<REXX> 1 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 1 </REXB> -<RM> 6 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> ArDI ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 7 </SIBINDEX> +<REXX> 0 </REXX> -rule <k> BND_B_CHECK => DecoderError ... </k> -<REXB> 1 </REXB> -<RM> 7 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar15 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> +<SIBINDEX> 7 </SIBINDEX> +<REXX> 1 </REXX> -syntax K ::= "BND_R" -rule <OUTREG> _ => REG_BND0 </OUTREG> -<k> BND_R => . ... </k> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> ArAX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 0 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_BND1 </OUTREG> -<k> BND_R => . ... </k> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar8 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 0 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_BND2 </OUTREG> -<k> BND_R => . ... </k> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> ArCX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 1 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_BND3 </OUTREG> -<k> BND_R => . ... </k> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar9 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 1 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> BND_R => . ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> ArDX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 2 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar10 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 2 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> ArBX ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 3 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar11 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 3 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <INDEX> _ => REG_INVALID </INDEX> +<SCALE> _ => 1 </SCALE> +<k> SIB => SIB_BASE0 ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 4 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar12 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 4 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> ArBP ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 5 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar13 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 5 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> ArSI ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 6 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar14 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 6 </SIBINDEX> +<REXX> 1 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> ArDI ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 7 </SIBINDEX> +<REXX> 0 </REXX> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_R => . ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <SCALE> _ => 8 </SCALE> +<k> SIB => SIB_BASE0 ~> Ar15 ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> +<SIBINDEX> 7 </SIBINDEX> +<REXX> 1 </REXX> -syntax K ::= "BND_B" -rule <OUTREG> _ => REG_BND0 </OUTREG> -<k> BND_B => . ... </k> -<REXB> 0 </REXB> -<RM> 0 </RM> +syntax K ::= "ASZ_NONTERM" +rule <EASZ> _ => 1 </EASZ> +<k> ASZ_NONTERM => . ... </k> +<MODE> 0 </MODE> +<ASZ> 0 </ASZ> -rule <OUTREG> _ => REG_BND1 </OUTREG> -<k> BND_B => . ... </k> -<REXB> 0 </REXB> -<RM> 1 </RM> +rule <EASZ> _ => 2 </EASZ> +<k> ASZ_NONTERM => . ... </k> +<MODE> 0 </MODE> +<ASZ> 1 </ASZ> -rule <OUTREG> _ => REG_BND2 </OUTREG> -<k> BND_B => . ... </k> -<REXB> 0 </REXB> -<RM> 2 </RM> +rule <EASZ> _ => 2 </EASZ> +<k> ASZ_NONTERM => . ... </k> +<MODE> 1 </MODE> +<ASZ> 0 </ASZ> -rule <OUTREG> _ => REG_BND3 </OUTREG> -<k> BND_B => . ... </k> -<REXB> 0 </REXB> -<RM> 3 </RM> +rule <EASZ> _ => 1 </EASZ> +<k> ASZ_NONTERM => . ... </k> +<MODE> 1 </MODE> +<ASZ> 1 </ASZ> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> BND_B => . ... </k> -<REXB> 0 </REXB> -<RM> 4 </RM> +rule <EASZ> _ => 3 </EASZ> +<k> ASZ_NONTERM => . ... </k> +<MODE> 2 </MODE> +<ASZ> 0 </ASZ> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 0 </REXB> -<RM> 5 </RM> +rule <EASZ> _ => 2 </EASZ> +<k> ASZ_NONTERM => . ... </k> +<MODE> 2 </MODE> +<ASZ> 1 </ASZ> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 0 </REXB> -<RM> 6 </RM> +syntax K ::= "REMOVE_SEGMENT" +rule <SEG0> _ => REG_INVALID </SEG0> +<k> REMOVE_SEGMENT => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 0 </REXB> -<RM> 7 </RM> +rule <SEG0> _ => REG_INVALID </SEG0> +<k> REMOVE_SEGMENT => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 1 </REXB> +rule <SEG0> _ => REG_INVALID </SEG0> +<k> REMOVE_SEGMENT => . ... </k> +<MODE> 2 </MODE> + + + +syntax K ::= "VGPR32_B_32" +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> VGPR32_B_32 => . ... </k> <RM> 0 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 1 </REXB> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> VGPR32_B_32 => . ... </k> <RM> 1 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 1 </REXB> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> VGPR32_B_32 => . ... </k> <RM> 2 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 1 </REXB> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> VGPR32_B_32 => . ... </k> <RM> 3 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 1 </REXB> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> VGPR32_B_32 => . ... </k> <RM> 4 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 1 </REXB> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> VGPR32_B_32 => . ... </k> <RM> 5 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 1 </REXB> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> VGPR32_B_32 => . ... </k> <RM> 6 </RM> -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> BND_B => . ... </k> -<REXB> 1 </REXB> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> VGPR32_B_32 => . ... </k> <RM> 7 </RM> -syntax K ::= "A_GPR_R" -rule <k> A_GPR_R => ArAX ... </k> -<REXR> 0 </REXR> -<REG> 0 </REG> - - +syntax K ::= "ArCX" +rule <OUTREG> _ => REG_CX </OUTREG> +<k> ArCX => . ... </k> +<EASZ> 1 </EASZ> -rule <k> A_GPR_R => ArCX ... </k> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> ArCX => . ... </k> +<EASZ> 2 </EASZ> -rule <k> A_GPR_R => ArDX ... </k> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_RCX </OUTREG> +<k> ArCX => . ... </k> +<EASZ> 3 </EASZ> -rule <k> A_GPR_R => ArBX ... </k> -<REXR> 0 </REXR> -<REG> 3 </REG> +syntax K ::= "YMM_B3_64" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 0 </RM> -rule <k> A_GPR_R => ArSP ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 1 </RM> -rule <k> A_GPR_R => ArBP ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 2 </RM> -rule <k> A_GPR_R => ArSI ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <k> A_GPR_R => ArDI ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 4 </RM> -rule <k> A_GPR_R => Ar8 ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 5 </RM> -rule <k> A_GPR_R => Ar9 ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <k> A_GPR_R => Ar10 ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 7 </RM> -rule <k> A_GPR_R => Ar11 ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_YMM8 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 0 </RM> -rule <k> A_GPR_R => Ar12 ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_YMM9 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <k> A_GPR_R => Ar13 ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_YMM10 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <k> A_GPR_R => Ar14 ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_YMM11 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 3 </RM> -rule <k> A_GPR_R => Ar15 ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_YMM12 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 4 </RM> -syntax K ::= "A_GPR_B" -rule <k> A_GPR_B => ArAX ... </k> + + +rule <OUTREG> _ => REG_YMM13 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 5 </RM> + + + +rule <OUTREG> _ => REG_YMM14 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 6 </RM> + + + +rule <OUTREG> _ => REG_YMM15 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 7 </RM> + + + +rule <OUTREG> _ => REG_YMM16 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 0 </RM> -rule <k> A_GPR_B => ArCX ... </k> +rule <OUTREG> _ => REG_YMM17 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 1 </RM> -rule <k> A_GPR_B => ArDX ... </k> +rule <OUTREG> _ => REG_YMM18 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 2 </RM> -rule <k> A_GPR_B => ArBX ... </k> +rule <OUTREG> _ => REG_YMM19 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 3 </RM> -rule <k> A_GPR_B => ArSP ... </k> +rule <OUTREG> _ => REG_YMM20 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 4 </RM> -rule <k> A_GPR_B => ArBP ... </k> +rule <OUTREG> _ => REG_YMM21 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 5 </RM> -rule <k> A_GPR_B => ArSI ... </k> +rule <OUTREG> _ => REG_YMM22 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 6 </RM> -rule <k> A_GPR_B => ArDI ... </k> +rule <OUTREG> _ => REG_YMM23 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 0 </REXB> <RM> 7 </RM> -rule <k> A_GPR_B => Ar8 ... </k> +rule <OUTREG> _ => REG_YMM24 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 0 </RM> -rule <k> A_GPR_B => Ar9 ... </k> +rule <OUTREG> _ => REG_YMM25 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 1 </RM> -rule <k> A_GPR_B => Ar10 ... </k> +rule <OUTREG> _ => REG_YMM26 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 2 </RM> -rule <k> A_GPR_B => Ar11 ... </k> +rule <OUTREG> _ => REG_YMM27 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 3 </RM> -rule <k> A_GPR_B => Ar12 ... </k> +rule <OUTREG> _ => REG_YMM28 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 4 </RM> -rule <k> A_GPR_B => Ar13 ... </k> +rule <OUTREG> _ => REG_YMM29 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 5 </RM> -rule <k> A_GPR_B => Ar14 ... </k> +rule <OUTREG> _ => REG_YMM30 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 6 </RM> -rule <k> A_GPR_B => Ar15 ... </k> +rule <OUTREG> _ => REG_YMM31 </OUTREG> +<k> YMM_B3_64 => . ... </k> +<REXX> 1 </REXX> <REXB> 1 </REXB> <RM> 7 </RM> -syntax K ::= "XMM_SE" -rule <k> XMM_SE => XMM_SE32 ... </k> -<MODE> 0 </MODE> +syntax K ::= "VGPRy_N" +rule <k> VGPRy_N => VGPR32_N ... </k> +<EOSZ> 1 </EOSZ> -rule <k> XMM_SE => XMM_SE32 ... </k> -<MODE> 1 </MODE> +rule <k> VGPRy_N => VGPR32_N ... </k> +<EOSZ> 2 </EOSZ> -rule <k> XMM_SE => XMM_SE64 ... </k> -<MODE> 2 </MODE> +rule <k> VGPRy_N => VGPR64_N ... </k> +<EOSZ> 3 </EOSZ> -syntax K ::= "XMM_SE64" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 0 </ESRC> +syntax K ::= "FINAL_DSEG_NOT64" +rule <OUTREG> _ => REG_CS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_NOT64 => . ... </k> +<SEGOVD> 1 </SEGOVD> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 1 </ESRC> +rule <OUTREG> _ => REG_ES </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_NOT64 => . ... </k> +<SEGOVD> 3 </SEGOVD> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 2 </ESRC> +rule <OUTREG> _ => REG_FS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_NOT64 => . ... </k> +<SEGOVD> 4 </SEGOVD> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 3 </ESRC> +rule <OUTREG> _ => REG_GS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_NOT64 => . ... </k> +<SEGOVD> 5 </SEGOVD> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 4 </ESRC> +rule <OUTREG> _ => REG_SS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_DSEG_NOT64 => . ... </k> +<SEGOVD> 6 </SEGOVD> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 5 </ESRC> +syntax K ::= "UIMM8_1" +rule <HASIMM1> _ => 1 </HASIMM1> +<k> UIMM8_1 => . ... </k> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 6 </ESRC> +syntax K ::= "IMMUNE_REXW" +rule <k> IMMUNE_REXW => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 7 </ESRC> +rule <k> IMMUNE_REXW => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_XMM8 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 8 </ESRC> +rule <EOSZ> _ => 2 </EOSZ> +<k> IMMUNE_REXW => . ... </k> +<MODE> 2 </MODE> +<OSZ> 0 </OSZ> -rule <OUTREG> _ => REG_XMM9 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 9 </ESRC> +rule <EOSZ> _ => 2 </EOSZ> +<k> IMMUNE_REXW => . ... </k> +<MODE> 2 </MODE> +<OSZ> 1 </OSZ> +<REXW> 1 </REXW> -rule <OUTREG> _ => REG_XMM10 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 10 </ESRC> +rule <EOSZ> _ => 1 </EOSZ> +<k> IMMUNE_REXW => . ... </k> +<MODE> 2 </MODE> +<OSZ> 1 </OSZ> +<REXW> 0 </REXW> -rule <OUTREG> _ => REG_XMM11 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 11 </ESRC> +syntax K ::= "YMM_N3_64" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_XMM12 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 12 </ESRC> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_XMM13 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 13 </ESRC> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <OUTREG> _ => REG_XMM14 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 14 </ESRC> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_XMM15 </OUTREG> -<k> XMM_SE64 => . ... </k> -<ESRC> 15 </ESRC> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -syntax K ::= "XMM_SE32" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> XMM_SE32 => . ... </k> -<ESRC> 0 </ESRC> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> XMM_SE32 => . ... </k> -<ESRC> 1 </ESRC> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> XMM_SE32 => . ... </k> -<ESRC> 2 </ESRC> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> XMM_SE32 => . ... </k> -<ESRC> 3 </ESRC> +rule <OUTREG> _ => REG_YMM8 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> XMM_SE32 => . ... </k> -<ESRC> 4 </ESRC> +rule <OUTREG> _ => REG_YMM9 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> XMM_SE32 => . ... </k> -<ESRC> 5 </ESRC> +rule <OUTREG> _ => REG_YMM10 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> XMM_SE32 => . ... </k> -<ESRC> 6 </ESRC> +rule <OUTREG> _ => REG_YMM11 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> XMM_SE32 => . ... </k> -<ESRC> 7 </ESRC> +rule <OUTREG> _ => REG_YMM12 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_SE32 => . ... </k> -<ESRC> 8 </ESRC> +rule <OUTREG> _ => REG_YMM13 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_SE32 => . ... </k> -<ESRC> 9 </ESRC> +rule <OUTREG> _ => REG_YMM14 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_SE32 => . ... </k> -<ESRC> 10 </ESRC> +rule <OUTREG> _ => REG_YMM15 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_SE32 => . ... </k> -<ESRC> 11 </ESRC> +rule <OUTREG> _ => REG_YMM16 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_SE32 => . ... </k> -<ESRC> 12 </ESRC> +rule <OUTREG> _ => REG_YMM17 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_SE32 => . ... </k> -<ESRC> 13 </ESRC> +rule <OUTREG> _ => REG_YMM18 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_SE32 => . ... </k> -<ESRC> 14 </ESRC> +rule <OUTREG> _ => REG_YMM19 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_SE32 => . ... </k> -<ESRC> 15 </ESRC> +rule <OUTREG> _ => REG_YMM20 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -syntax K ::= "YMM_SE" -rule <k> YMM_SE => YMM_SE32 ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_YMM21 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <k> YMM_SE => YMM_SE32 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_YMM22 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <k> YMM_SE => YMM_SE64 ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_YMM23 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -syntax K ::= "YMM_SE64" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 0 </ESRC> +rule <OUTREG> _ => REG_YMM24 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 1 </ESRC> +rule <OUTREG> _ => REG_YMM25 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 2 </ESRC> +rule <OUTREG> _ => REG_YMM26 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 3 </ESRC> +rule <OUTREG> _ => REG_YMM27 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 4 </ESRC> +rule <OUTREG> _ => REG_YMM28 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 5 </ESRC> +rule <OUTREG> _ => REG_YMM29 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 6 </ESRC> +rule <OUTREG> _ => REG_YMM30 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 7 </ESRC> +rule <OUTREG> _ => REG_YMM31 </OUTREG> +<k> YMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <OUTREG> _ => REG_YMM8 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 8 </ESRC> +syntax K ::= "ESIZE_128_BITS" +rule <ELEMENTSIZE> _ => 128 </ELEMENTSIZE> +<k> ESIZE_128_BITS => . ... </k> +<REX> 0 </REX> -rule <OUTREG> _ => REG_YMM9 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 9 </ESRC> +syntax K ::= "MODRM" +rule <k> MODRM => MODRM64alt32 ~> MEMDISP ... </k> +<MODE> 2 </MODE> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_YMM10 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 10 </ESRC> +rule <k> MODRM => MODRM64alt32 ~> MEMDISP ... </k> +<MODE> 2 </MODE> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_YMM11 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 11 </ESRC> +rule <k> MODRM => MODRM32 ~> MEMDISP ... </k> +<MODE> 1 </MODE> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_YMM12 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 12 </ESRC> +rule <k> MODRM => MODRM16 ~> MEMDISP ... </k> +<MODE> 1 </MODE> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_YMM13 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 13 </ESRC> +rule <k> MODRM => MODRM32 ~> MEMDISP ... </k> +<MODE> 0 </MODE> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_YMM14 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 14 </ESRC> +rule <k> MODRM => MODRM16 ~> MEMDISP ... </k> +<MODE> 0 </MODE> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_YMM15 </OUTREG> -<k> YMM_SE64 => . ... </k> -<ESRC> 15 </ESRC> +syntax K ::= "A_GPR_B" +rule <k> A_GPR_B => ArAX ... </k> +<REXB> 0 </REXB> +<RM> 0 </RM> -syntax K ::= "YMM_SE32" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> YMM_SE32 => . ... </k> -<ESRC> 0 </ESRC> +rule <k> A_GPR_B => ArCX ... </k> +<REXB> 0 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> YMM_SE32 => . ... </k> -<ESRC> 1 </ESRC> +rule <k> A_GPR_B => ArDX ... </k> +<REXB> 0 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> YMM_SE32 => . ... </k> -<ESRC> 2 </ESRC> +rule <k> A_GPR_B => ArBX ... </k> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> YMM_SE32 => . ... </k> -<ESRC> 3 </ESRC> +rule <k> A_GPR_B => ArSP ... </k> +<REXB> 0 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> YMM_SE32 => . ... </k> -<ESRC> 4 </ESRC> +rule <k> A_GPR_B => ArBP ... </k> +<REXB> 0 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> YMM_SE32 => . ... </k> -<ESRC> 5 </ESRC> +rule <k> A_GPR_B => ArSI ... </k> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> YMM_SE32 => . ... </k> -<ESRC> 6 </ESRC> +rule <k> A_GPR_B => ArDI ... </k> +<REXB> 0 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> -<k> YMM_SE32 => . ... </k> -<ESRC> 7 </ESRC> +rule <k> A_GPR_B => Ar8 ... </k> +<REXB> 1 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_SE32 => . ... </k> -<ESRC> 8 </ESRC> +rule <k> A_GPR_B => Ar9 ... </k> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_SE32 => . ... </k> -<ESRC> 9 </ESRC> +rule <k> A_GPR_B => Ar10 ... </k> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_SE32 => . ... </k> -<ESRC> 10 </ESRC> +rule <k> A_GPR_B => Ar11 ... </k> +<REXB> 1 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_SE32 => . ... </k> -<ESRC> 11 </ESRC> +rule <k> A_GPR_B => Ar12 ... </k> +<REXB> 1 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_SE32 => . ... </k> -<ESRC> 12 </ESRC> +rule <k> A_GPR_B => Ar13 ... </k> +<REXB> 1 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_SE32 => . ... </k> -<ESRC> 13 </ESRC> +rule <k> A_GPR_B => Ar14 ... </k> +<REXB> 1 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_SE32 => . ... </k> -<ESRC> 14 </ESRC> +rule <k> A_GPR_B => Ar15 ... </k> +<REXB> 1 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_SE32 => . ... </k> -<ESRC> 15 </ESRC> +syntax K ::= "Ar10" +rule <OUTREG> _ => REG_R10W </OUTREG> +<k> Ar10 => . ... </k> +<EASZ> 1 </EASZ> -syntax K ::= "XMM_N" -rule <k> XMM_N => XMM_N_32 ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_R10D </OUTREG> +<k> Ar10 => . ... </k> +<EASZ> 2 </EASZ> -rule <k> XMM_N => XMM_N_32 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_R10 </OUTREG> +<k> Ar10 => . ... </k> +<EASZ> 3 </EASZ> -rule <k> XMM_N => XMM_N_64 ... </k> -<MODE> 2 </MODE> +syntax K ::= "X87" +rule <OUTREG> _ => REG_ST0 </OUTREG> +<k> X87 => . ... </k> +<RM> 0 </RM> -syntax K ::= "XMM_N_32" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_N_32 => . ... </k> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_ST1 </OUTREG> +<k> X87 => . ... </k> +<RM> 1 </RM> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_N_32 => . ... </k> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_ST2 </OUTREG> +<k> X87 => . ... </k> +<RM> 2 </RM> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_N_32 => . ... </k> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_ST3 </OUTREG> +<k> X87 => . ... </k> +<RM> 3 </RM> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_N_32 => . ... </k> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_ST4 </OUTREG> +<k> X87 => . ... </k> +<RM> 4 </RM> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_N_32 => . ... </k> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_ST5 </OUTREG> +<k> X87 => . ... </k> +<RM> 5 </RM> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_N_32 => . ... </k> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_ST6 </OUTREG> +<k> X87 => . ... </k> +<RM> 6 </RM> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_N_32 => . ... </k> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_ST7 </OUTREG> +<k> X87 => . ... </k> +<RM> 7 </RM> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_N_32 => . ... </k> -<VEXDEST210> 0 </VEXDEST210> +syntax K ::= "ArAX" +rule <OUTREG> _ => REG_AX </OUTREG> +<k> ArAX => . ... </k> +<EASZ> 1 </EASZ> -syntax K ::= "XMM_N_64" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> ArAX => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_RAX </OUTREG> +<k> ArAX => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +syntax K ::= "MMX_B" +rule <OUTREG> _ => REG_MMX0 </OUTREG> +<k> MMX_B => . ... </k> +<RM> 0 </RM> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_MMX1 </OUTREG> +<k> MMX_B => . ... </k> +<RM> 1 </RM> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_MMX2 </OUTREG> +<k> MMX_B => . ... </k> +<RM> 2 </RM> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_MMX3 </OUTREG> +<k> MMX_B => . ... </k> +<RM> 3 </RM> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_MMX4 </OUTREG> +<k> MMX_B => . ... </k> +<RM> 4 </RM> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_MMX5 </OUTREG> +<k> MMX_B => . ... </k> +<RM> 5 </RM> -rule <OUTREG> _ => REG_XMM8 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_MMX6 </OUTREG> +<k> MMX_B => . ... </k> +<RM> 6 </RM> -rule <OUTREG> _ => REG_XMM9 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_MMX7 </OUTREG> +<k> MMX_B => . ... </k> +<RM> 7 </RM> -rule <OUTREG> _ => REG_XMM10 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +syntax K ::= "GPR16_SB" +rule <OUTREG> _ => REG_AX </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 0 </SRM> -rule <OUTREG> _ => REG_XMM11 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_CX </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 1 </SRM> -rule <OUTREG> _ => REG_XMM12 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_DX </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 2 </SRM> -rule <OUTREG> _ => REG_XMM13 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_BX </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 3 </SRM> -rule <OUTREG> _ => REG_XMM14 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_SP </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 4 </SRM> -rule <OUTREG> _ => REG_XMM15 </OUTREG> -<k> XMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_BP </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 5 </SRM> -syntax K ::= "YMM_N" -rule <k> YMM_N => YMM_N_32 ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_SI </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 6 </SRM> -rule <k> YMM_N => YMM_N_32 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_DI </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 0 </REXB> +<SRM> 7 </SRM> -rule <k> YMM_N => YMM_N_64 ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_R8W </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 0 </SRM> -syntax K ::= "YMM_N_32" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_N_32 => . ... </k> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_R9W </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 1 </SRM> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_N_32 => . ... </k> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_R10W </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 2 </SRM> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_N_32 => . ... </k> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_R11W </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 3 </SRM> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_N_32 => . ... </k> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_R12W </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 4 </SRM> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_N_32 => . ... </k> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_R13W </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 5 </SRM> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_N_32 => . ... </k> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_R14W </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 6 </SRM> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_N_32 => . ... </k> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_R15W </OUTREG> +<k> GPR16_SB => . ... </k> +<REXB> 1 </REXB> +<SRM> 7 </SRM> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_N_32 => . ... </k> -<VEXDEST210> 0 </VEXDEST210> +syntax K ::= "NELEM_FULL" +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_FULL => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 2 </VL> -syntax K ::= "YMM_N_64" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <NELEM> _ => 1 </NELEM> +<BCAST> _ => 16 </BCAST> +<k> NELEM_FULL => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_FULL => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <NELEM> _ => 1 </NELEM> +<BCAST> _ => 1 </BCAST> +<k> NELEM_FULL => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_FULL => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <NELEM> _ => 1 </NELEM> +<BCAST> _ => 5 </BCAST> +<k> NELEM_FULL => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> - - - -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_FULL => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <NELEM> _ => 1 </NELEM> +<BCAST> _ => 15 </BCAST> +<k> NELEM_FULL => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM8 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_FULL => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM9 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <NELEM> _ => 1 </NELEM> +<BCAST> _ => 3 </BCAST> +<k> NELEM_FULL => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM10 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_FULL => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM11 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <NELEM> _ => 1 </NELEM> +<BCAST> _ => 13 </BCAST> +<k> NELEM_FULL => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM12 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_FULL => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_YMM13 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <NELEM> _ => 1 </NELEM> +<BCAST> _ => 14 </BCAST> +<k> NELEM_FULL => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_YMM14 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_FULL => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_YMM15 </OUTREG> -<k> YMM_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <NELEM> _ => 1 </NELEM> +<BCAST> _ => 10 </BCAST> +<k> NELEM_FULL => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 0 </VL> -syntax K ::= "YMM_R" -rule <k> YMM_R => YMM_R_32 ... </k> -<MODE> 0 </MODE> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_FULL => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 0 </VL> -rule <k> YMM_R => YMM_R_32 ... </k> -<MODE> 1 </MODE> +rule <NELEM> _ => 1 </NELEM> +<BCAST> _ => 11 </BCAST> +<k> NELEM_FULL => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 0 </VL> -rule <k> YMM_R => YMM_R_64 ... </k> -<MODE> 2 </MODE> +syntax K ::= "BRDISP32" +rule <BRDISPWIDTH> _ => 32 </BRDISPWIDTH> +<k> BRDISP32 => . ... </k> -syntax K ::= "YMM_R_32" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_R_32 => . ... </k> -<REG> 0 </REG> +syntax K ::= "NELEM_TUPLE2" +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_TUPLE2 => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_R_32 => . ... </k> -<REG> 1 </REG> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_TUPLE2 => . ... </k> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_R_32 => . ... </k> -<REG> 2 </REG> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_TUPLE2 => . ... </k> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_R_32 => . ... </k> -<REG> 3 </REG> +syntax K ::= "XMM_SE32" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> XMM_SE32 => . ... </k> +<ESRC> 0 </ESRC> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_R_32 => . ... </k> -<REG> 4 </REG> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> XMM_SE32 => . ... </k> +<ESRC> 1 </ESRC> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_R_32 => . ... </k> -<REG> 5 </REG> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> XMM_SE32 => . ... </k> +<ESRC> 2 </ESRC> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_R_32 => . ... </k> -<REG> 6 </REG> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> XMM_SE32 => . ... </k> +<ESRC> 3 </ESRC> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_R_32 => . ... </k> -<REG> 7 </REG> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> XMM_SE32 => . ... </k> +<ESRC> 4 </ESRC> -syntax K ::= "YMM_R_64" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> XMM_SE32 => . ... </k> +<ESRC> 5 </ESRC> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> XMM_SE32 => . ... </k> +<ESRC> 6 </ESRC> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> XMM_SE32 => . ... </k> +<ESRC> 7 </ESRC> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_SE32 => . ... </k> +<ESRC> 8 </ESRC> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_SE32 => . ... </k> +<ESRC> 9 </ESRC> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_SE32 => . ... </k> +<ESRC> 10 </ESRC> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_SE32 => . ... </k> +<ESRC> 11 </ESRC> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_SE32 => . ... </k> +<ESRC> 12 </ESRC> -rule <OUTREG> _ => REG_YMM8 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_SE32 => . ... </k> +<ESRC> 13 </ESRC> -rule <OUTREG> _ => REG_YMM9 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_SE32 => . ... </k> +<ESRC> 14 </ESRC> -rule <OUTREG> _ => REG_YMM10 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_SE32 => . ... </k> +<ESRC> 15 </ESRC> -rule <OUTREG> _ => REG_YMM11 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +syntax K ::= "ESIZE_32_BITS" +rule <ELEMENTSIZE> _ => 32 </ELEMENTSIZE> +<k> ESIZE_32_BITS => . ... </k> +<REX> 0 </REX> -rule <OUTREG> _ => REG_YMM12 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +syntax K ::= "VSIB_BASE" +rule <k> VSIB_BASE => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 0 </SIBBASE> -rule <OUTREG> _ => REG_YMM13 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <k> VSIB_BASE => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 1 </SIBBASE> -rule <OUTREG> _ => REG_YMM14 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <k> VSIB_BASE => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 2 </SIBBASE> -rule <OUTREG> _ => REG_YMM15 </OUTREG> -<k> YMM_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <k> VSIB_BASE => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 3 </SIBBASE> -syntax K ::= "YMM_B" -rule <k> YMM_B => YMM_B_32 ... </k> -<MODE> 0 </MODE> +rule <k> VSIB_BASE => ArSP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 4 </SIBBASE> -rule <k> YMM_B => YMM_B_32 ... </k> -<MODE> 1 </MODE> +rule <BASE0> _ => REG_INVALID </BASE0> +<k> VSIB_BASE => MEMDISP32 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 0 </MOD> -rule <k> YMM_B => YMM_B_64 ... </k> -<MODE> 2 </MODE> +rule <k> VSIB_BASE => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> I1:Int </MOD> +requires I1 =/=Int 0 +rule <k> VSIB_BASE => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 6 </SIBBASE> -syntax K ::= "YMM_B_32" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_B_32 => . ... </k> -<RM> 0 </RM> +rule <k> VSIB_BASE => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 7 </SIBBASE> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_B_32 => . ... </k> -<RM> 1 </RM> +rule <k> VSIB_BASE => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 0 </SIBBASE> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_B_32 => . ... </k> -<RM> 2 </RM> +rule <k> VSIB_BASE => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 1 </SIBBASE> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_B_32 => . ... </k> -<RM> 3 </RM> +rule <k> VSIB_BASE => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 2 </SIBBASE> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_B_32 => . ... </k> -<RM> 4 </RM> +rule <k> VSIB_BASE => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 3 </SIBBASE> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_B_32 => . ... </k> -<RM> 5 </RM> +rule <k> VSIB_BASE => Ar12 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 4 </SIBBASE> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_B_32 => . ... </k> -<RM> 6 </RM> +rule <BASE0> _ => REG_INVALID </BASE0> +<k> VSIB_BASE => MEMDISP32 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 0 </MOD> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_B_32 => . ... </k> -<RM> 7 </RM> +rule <k> VSIB_BASE => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> I1:Int </MOD> +requires I1 =/=Int 0 -syntax K ::= "YMM_B_64" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 0 </RM> +rule <k> VSIB_BASE => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 6 </SIBBASE> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 1 </RM> +rule <k> VSIB_BASE => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 7 </SIBBASE> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 2 </RM> +syntax K ::= "REFINING66" +rule <EOSZ> _ => 1 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> REFINING66 => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 3 </RM> +rule <EOSZ> _ => 2 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> REFINING66 => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 4 </RM> +rule <EOSZ> _ => 2 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> REFINING66 => . ... </k> +<MODE> 2 </MODE> +<REXW> 0 </REXW> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 5 </RM> +rule <EOSZ> _ => 3 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> REFINING66 => . ... </k> +<MODE> 2 </MODE> +<REXW> 1 </REXW> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 6 </RM> +syntax K ::= "YMM_N3" +rule <k> YMM_N3 => YMM_N3_32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 7 </RM> +rule <k> YMM_N3 => YMM_N3_32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_YMM8 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 0 </RM> +rule <k> YMM_N3 => YMM_N3_64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_YMM9 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 1 </RM> +syntax K ::= "rIPa" +rule <OUTREG> _ => REG_EIP </OUTREG> +<k> rIPa => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_YMM10 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 2 </RM> +rule <OUTREG> _ => REG_RIP </OUTREG> +<k> rIPa => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_YMM11 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 3 </RM> +syntax K ::= "Ar12" +rule <OUTREG> _ => REG_R12W </OUTREG> +<k> Ar12 => . ... </k> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_YMM12 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 4 </RM> +rule <OUTREG> _ => REG_R12D </OUTREG> +<k> Ar12 => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_YMM13 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 5 </RM> +rule <OUTREG> _ => REG_R12 </OUTREG> +<k> Ar12 => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_YMM14 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 6 </RM> +syntax K ::= "NELEM_GPR_WRITER_STORE_WORD" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_STORE_WORD => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_YMM15 </OUTREG> -<k> YMM_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 7 </RM> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_STORE_WORD => . ... </k> +<VL> 1 </VL> -syntax K ::= "SE_IMM8" -rule <IMMWIDTH> _ => 8 </IMMWIDTH> -<k> SE_IMM8 => . ... </k> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_STORE_WORD => . ... </k> +<VL> 2 </VL> -syntax K ::= "VMODRM_YMM" -rule <k> VMODRM_YMM => VSIB_YMM ... </k> -<MOD> 0 </MOD> +syntax K ::= "SIMMz" +rule <IMMWIDTH> _ => 16 </IMMWIDTH> +<IMM0SIGNED> _ => 1 </IMM0SIGNED> +<k> SIMMz => . ... </k> +<EOSZ> 1 </EOSZ> -rule <k> VMODRM_YMM => VSIB_YMM ~> MEMDISP8 ... </k> -<MOD> 1 </MOD> +rule <IMMWIDTH> _ => 32 </IMMWIDTH> +<IMM0SIGNED> _ => 1 </IMM0SIGNED> +<k> SIMMz => . ... </k> +<EOSZ> 2 </EOSZ> -rule <k> VMODRM_YMM => VSIB_YMM ~> MEMDISP32 ... </k> -<MOD> 2 </MOD> +rule <IMMWIDTH> _ => 32 </IMMWIDTH> +<IMM0SIGNED> _ => 1 </IMM0SIGNED> +<k> SIMMz => . ... </k> +<EOSZ> 3 </EOSZ> -syntax K ::= "VMODRM_XMM" -rule <k> VMODRM_XMM => VSIB_XMM ... </k> -<MOD> 0 </MOD> +syntax K ::= "ONE" +rule <IMMWIDTH> _ => 8 </IMMWIDTH> +<UIMM0> _ => 1 </UIMM0> +<k> ONE => . ... </k> +<MODE> 0 </MODE> -rule <k> VMODRM_XMM => VSIB_XMM ~> MEMDISP8 ... </k> -<MOD> 1 </MOD> +rule <IMMWIDTH> _ => 8 </IMMWIDTH> +<UIMM0> _ => 1 </UIMM0> +<k> ONE => . ... </k> +<MODE> 1 </MODE> -rule <k> VMODRM_XMM => VSIB_XMM ~> MEMDISP32 ... </k> -<MOD> 2 </MOD> +rule <IMMWIDTH> _ => 8 </IMMWIDTH> +<UIMM0> _ => 1 </UIMM0> +<k> ONE => . ... </k> +<MODE> 2 </MODE> -syntax K ::= "VSIB_YMM" -rule <SCALE> _ => 1 </SCALE> -<k> VSIB_YMM => VSIB_BASE ~> VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> +syntax K ::= "SEG_MOV" +rule <OUTREG> _ => REG_ES </OUTREG> +<k> SEG_MOV => . ... </k> +<REG> 0 </REG> -rule <SCALE> _ => 2 </SCALE> -<k> VSIB_YMM => VSIB_BASE ~> VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> SEG_MOV => . ... </k> +<REG> 1 </REG> -rule <SCALE> _ => 4 </SCALE> -<k> VSIB_YMM => VSIB_BASE ~> VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> +rule <OUTREG> _ => REG_SS </OUTREG> +<k> SEG_MOV => . ... </k> +<REG> 2 </REG> -rule <SCALE> _ => 8 </SCALE> -<k> VSIB_YMM => VSIB_BASE ~> VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> +rule <OUTREG> _ => REG_DS </OUTREG> +<k> SEG_MOV => . ... </k> +<REG> 3 </REG> -syntax K ::= "VSIB_XMM" -rule <SCALE> _ => 1 </SCALE> -<k> VSIB_XMM => VSIB_BASE ~> VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> +rule <OUTREG> _ => REG_FS </OUTREG> +<k> SEG_MOV => . ... </k> +<REG> 4 </REG> -rule <SCALE> _ => 2 </SCALE> -<k> VSIB_XMM => VSIB_BASE ~> VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> +rule <OUTREG> _ => REG_GS </OUTREG> +<k> SEG_MOV => . ... </k> +<REG> 5 </REG> -rule <SCALE> _ => 4 </SCALE> -<k> VSIB_XMM => VSIB_BASE ~> VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> SEG_MOV => . ... </k> +<REG> 6 </REG> -rule <SCALE> _ => 8 </SCALE> -<k> VSIB_XMM => VSIB_BASE ~> VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> SEG_MOV => . ... </k> +<REG> 7 </REG> -syntax K ::= "VSIB_INDEX_YMM" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> +syntax K ::= "BRDISP8" +rule <BRDISPWIDTH> _ => 8 </BRDISPWIDTH> +<k> BRDISP8 => . ... </k> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +syntax K ::= "ArSP" +rule <OUTREG> _ => REG_SP </OUTREG> +<k> ArSP => . ... </k> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> ArSP => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_RSP </OUTREG> +<k> ArSP => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +syntax K ::= "FINAL_SSEG" +rule <k> FINAL_SSEG => FINAL_SSEG_NOT64 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <k> FINAL_SSEG => FINAL_SSEG_NOT64 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <k> FINAL_SSEG => FINAL_SSEG_MODE64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +syntax K ::= "NELEM_SCALAR" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_SCALAR => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_YMM8 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_SCALAR => . ... </k> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM9 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_SCALAR => . ... </k> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM10 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +syntax K ::= "YMM_SE" +rule <k> YMM_SE => YMM_SE32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_YMM11 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <k> YMM_SE => YMM_SE32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_YMM12 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <k> YMM_SE => YMM_SE64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_YMM13 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +syntax K ::= "OrDX" +rule <OUTREG> _ => REG_DX </OUTREG> +<k> OrDX => . ... </k> +<EOSZ> 1 </EOSZ> -rule <OUTREG> _ => REG_YMM14 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> OrDX => . ... </k> +<EOSZ> 2 </EOSZ> -rule <OUTREG> _ => REG_YMM15 </OUTREG> -<k> VSIB_INDEX_YMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_RDX </OUTREG> +<k> OrDX => . ... </k> +<EOSZ> 3 </EOSZ> -syntax K ::= "VSIB_INDEX_XMM" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> +syntax K ::= "MMX_R" +rule <OUTREG> _ => REG_MMX0 </OUTREG> +<k> MMX_R => . ... </k> +<REG> 0 </REG> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <OUTREG> _ => REG_MMX1 </OUTREG> +<k> MMX_R => . ... </k> +<REG> 1 </REG> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_MMX2 </OUTREG> +<k> MMX_R => . ... </k> +<REG> 2 </REG> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_MMX3 </OUTREG> +<k> MMX_R => . ... </k> +<REG> 3 </REG> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <OUTREG> _ => REG_MMX4 </OUTREG> +<k> MMX_R => . ... </k> +<REG> 4 </REG> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_MMX5 </OUTREG> +<k> MMX_R => . ... </k> +<REG> 5 </REG> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_MMX6 </OUTREG> +<k> MMX_R => . ... </k> +<REG> 6 </REG> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_MMX7 </OUTREG> +<k> MMX_R => . ... </k> +<REG> 7 </REG> -rule <OUTREG> _ => REG_XMM8 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> +syntax K ::= "MASK_N" +rule <k> MASK_N => MASK_N64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_XMM9 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <k> MASK_N => MASK_N32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_XMM10 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <k> MASK_N => MASK_N32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_XMM11 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +syntax K ::= "NELEM_GPR_WRITER_STORE_SUBDWORD" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_STORE_SUBDWORD => . ... </k> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM12 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_STORE_SUBDWORD => . ... </k> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM13 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_STORE_SUBDWORD => . ... </k> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM14 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +syntax K ::= "AVX512_ROUND" +rule <ROUNDC> _ => 1 </ROUNDC> +<SAE> _ => 1 </SAE> +<k> AVX512_ROUND => . ... </k> +<LLRC> 0 </LLRC> -rule <OUTREG> _ => REG_XMM15 </OUTREG> -<k> VSIB_INDEX_XMM => . ... </k> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <ROUNDC> _ => 2 </ROUNDC> +<SAE> _ => 1 </SAE> +<k> AVX512_ROUND => . ... </k> +<LLRC> 1 </LLRC> -syntax K ::= "VSIB_BASE" -rule <k> VSIB_BASE => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 0 </SIBBASE> +rule <ROUNDC> _ => 3 </ROUNDC> +<SAE> _ => 1 </SAE> +<k> AVX512_ROUND => . ... </k> +<LLRC> 2 </LLRC> -rule <k> VSIB_BASE => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 1 </SIBBASE> +rule <ROUNDC> _ => 4 </ROUNDC> +<SAE> _ => 1 </SAE> +<k> AVX512_ROUND => . ... </k> +<LLRC> 3 </LLRC> -rule <k> VSIB_BASE => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 2 </SIBBASE> +syntax K ::= "Ar11" +rule <OUTREG> _ => REG_R11W </OUTREG> +<k> Ar11 => . ... </k> +<EASZ> 1 </EASZ> -rule <k> VSIB_BASE => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 3 </SIBBASE> +rule <OUTREG> _ => REG_R11D </OUTREG> +<k> Ar11 => . ... </k> +<EASZ> 2 </EASZ> -rule <k> VSIB_BASE => ArSP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 4 </SIBBASE> +rule <OUTREG> _ => REG_R11 </OUTREG> +<k> Ar11 => . ... </k> +<EASZ> 3 </EASZ> -rule <BASE0> _ => REG_INVALID </BASE0> -<k> VSIB_BASE => MEMDISP32 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 0 </MOD> +syntax K ::= "CR_R" +rule <OUTREG> _ => REG_CR0 </OUTREG> +<k> CR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <k> VSIB_BASE => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> I1:Int </MOD> -requires I1 =/=Int 0 +rule <OUTREG> _ => REG_ERROR </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> CR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <k> VSIB_BASE => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 6 </SIBBASE> +rule <OUTREG> _ => REG_CR2 </OUTREG> +<k> CR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <k> VSIB_BASE => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 7 </SIBBASE> +rule <OUTREG> _ => REG_CR3 </OUTREG> +<k> CR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <k> VSIB_BASE => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 0 </SIBBASE> +rule <OUTREG> _ => REG_CR4 </OUTREG> +<k> CR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <k> VSIB_BASE => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 1 </SIBBASE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <k> VSIB_BASE => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 2 </SIBBASE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <k> VSIB_BASE => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 3 </SIBBASE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <k> VSIB_BASE => Ar12 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 4 </SIBBASE> +rule <OUTREG> _ => REG_CR8 </OUTREG> +<k> CR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <BASE0> _ => REG_INVALID </BASE0> -<k> VSIB_BASE => MEMDISP32 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <k> VSIB_BASE => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> I1:Int </MOD> -requires I1 =/=Int 0 -rule <k> VSIB_BASE => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 6 </SIBBASE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <k> VSIB_BASE => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 7 </SIBBASE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -syntax K ::= "VGPRy_N" -rule <k> VGPRy_N => VGPR32_N ... </k> -<EOSZ> 1 </EOSZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <k> VGPRy_N => VGPR32_N ... </k> -<EOSZ> 2 </EOSZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <k> VGPRy_N => VGPR64_N ... </k> -<EOSZ> 3 </EOSZ> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -syntax K ::= "VGPR32_N" -rule <k> VGPR32_N => VGPR32_N_32 ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_R => . ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <k> VGPR32_N => VGPR32_N_32 ... </k> -<MODE> 1 </MODE> +syntax K ::= "UISA_VSIB_XMM" +rule <SCALE> _ => 1 </SCALE> +<k> UISA_VSIB_XMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> -rule <k> VGPR32_N => VGPR32_N_64 ... </k> -<MODE> 2 </MODE> +rule <SCALE> _ => 2 </SCALE> +<k> UISA_VSIB_XMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> -syntax K ::= "VGPR32_B" -rule <k> VGPR32_B => VGPR32_B_32 ... </k> -<MODE> 0 </MODE> +rule <SCALE> _ => 4 </SCALE> +<k> UISA_VSIB_XMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> -rule <k> VGPR32_B => VGPR32_B_32 ... </k> -<MODE> 1 </MODE> +rule <SCALE> _ => 8 </SCALE> +<k> UISA_VSIB_XMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> -rule <k> VGPR32_B => VGPR32_B_64 ... </k> +syntax K ::= "GPRm_B" +rule <k> GPRm_B => GPR64_B ... </k> <MODE> 2 </MODE> -syntax K ::= "VGPR32_R" -rule <k> VGPR32_R => VGPR32_R_32 ... </k> -<MODE> 0 </MODE> +rule <k> GPRm_B => GPR32_B ... </k> +<MODE> 1 </MODE> -rule <k> VGPR32_R => VGPR32_R_32 ... </k> -<MODE> 1 </MODE> +rule <k> GPRm_B => GPR32_B ... </k> +<MODE> 0 </MODE> -rule <k> VGPR32_R => VGPR32_R_64 ... </k> -<MODE> 2 </MODE> +syntax K ::= "UISA_VMODRM_YMM" +rule <k> UISA_VMODRM_YMM => UISA_VSIB_YMM ... </k> +<MOD> 0 </MOD> -syntax K ::= "VGPR32_N_32" -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> VGPR32_N_32 => . ... </k> -<VEXDEST210> 7 </VEXDEST210> +rule <k> UISA_VMODRM_YMM => UISA_VSIB_YMM ~> MEMDISP8 ... </k> +<MOD> 1 </MOD> -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> VGPR32_N_32 => . ... </k> -<VEXDEST210> 6 </VEXDEST210> +rule <k> UISA_VMODRM_YMM => UISA_VSIB_YMM ~> MEMDISP32 ... </k> +<MOD> 2 </MOD> -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> VGPR32_N_32 => . ... </k> -<VEXDEST210> 5 </VEXDEST210> - - - -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> VGPR32_N_32 => . ... </k> -<VEXDEST210> 4 </VEXDEST210> - - - -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> VGPR32_N_32 => . ... </k> -<VEXDEST210> 3 </VEXDEST210> - - - -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> VGPR32_N_32 => . ... </k> -<VEXDEST210> 2 </VEXDEST210> - - - -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> VGPR32_N_32 => . ... </k> -<VEXDEST210> 1 </VEXDEST210> - - - -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> VGPR32_N_32 => . ... </k> -<VEXDEST210> 0 </VEXDEST210> - - - -syntax K ::= "VGPR32_N_64" -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> - - - -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> - - - -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +syntax K ::= "Ar13" +rule <OUTREG> _ => REG_R13W </OUTREG> +<k> Ar13 => . ... </k> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_R13D </OUTREG> +<k> Ar13 => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_R13 </OUTREG> +<k> Ar13 => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +syntax K ::= "XMM_R" +rule <k> XMM_R => XMM_R_32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <k> XMM_R => XMM_R_32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <k> XMM_R => XMM_R_64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_R8D </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +syntax K ::= "ZMM_B3_64" +rule <OUTREG> _ => REG_ZMM0 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R9D </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM1 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R10D </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM2 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_R11D </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM3 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_R12D </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM4 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_R13D </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM5 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_R14D </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM6 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R15D </OUTREG> -<k> VGPR32_N_64 => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM7 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 0 </REXB> +<RM> 7 </RM> -syntax K ::= "VGPR64_N" -rule <OUTREG> _ => REG_RAX </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM8 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_RCX </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM9 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_RDX </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM10 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_RBX </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM11 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_RSP </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM12 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_RBP </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM13 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_RSI </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM14 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_RDI </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM15 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 0 </REXX> +<REXB> 1 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R8 </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM16 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 0 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R9 </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM17 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 0 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R10 </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM18 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 0 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_R11 </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM19 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_R12 </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM20 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 0 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_R13 </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM21 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 0 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_R14 </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM22 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R15 </OUTREG> -<k> VGPR64_N => . ... </k> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_ZMM23 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 0 </REXB> +<RM> 7 </RM> -syntax K ::= "VGPR32_R_32" -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> VGPR32_R_32 => . ... </k> -<REG> 0 </REG> +rule <OUTREG> _ => REG_ZMM24 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 1 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> VGPR32_R_32 => . ... </k> -<REG> 1 </REG> +rule <OUTREG> _ => REG_ZMM25 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> VGPR32_R_32 => . ... </k> -<REG> 2 </REG> +rule <OUTREG> _ => REG_ZMM26 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> VGPR32_R_32 => . ... </k> -<REG> 3 </REG> +rule <OUTREG> _ => REG_ZMM27 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 1 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> VGPR32_R_32 => . ... </k> -<REG> 4 </REG> +rule <OUTREG> _ => REG_ZMM28 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 1 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> VGPR32_R_32 => . ... </k> -<REG> 5 </REG> +rule <OUTREG> _ => REG_ZMM29 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 1 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> VGPR32_R_32 => . ... </k> -<REG> 6 </REG> +rule <OUTREG> _ => REG_ZMM30 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 1 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> VGPR32_R_32 => . ... </k> -<REG> 7 </REG> +rule <OUTREG> _ => REG_ZMM31 </OUTREG> +<k> ZMM_B3_64 => . ... </k> +<REXX> 1 </REXX> +<REXB> 1 </REXB> +<RM> 7 </RM> -syntax K ::= "VGPR32_R_64" -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 0 </REG> +syntax K ::= "NELEM_MEM128" +rule <ELEMENTSIZE> _ => 64 </ELEMENTSIZE> +<NELEM> _ => 2 </NELEM> +<k> NELEM_MEM128 => . ... </k> +<BCRC> 0 </BCRC> -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <k> NELEM_MEM128 => DecoderError ... </k> +<BCRC> 1 </BCRC> -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 2 </REG> +syntax K ::= "MODRM16" +rule <BASE0> _ => REG_BX </BASE0> +<INDEX> _ => REG_SI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <BASE0> _ => REG_BX </BASE0> +<INDEX> _ => REG_DI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <BASE0> _ => REG_BP </BASE0> +<INDEX> _ => REG_SI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <BASE0> _ => REG_BP </BASE0> +<INDEX> _ => REG_DI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <BASE0> _ => REG_SI </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <BASE0> _ => REG_DI </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_R8D </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> +<BASE0> _ => REG_INVALID </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R9D </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <BASE0> _ => REG_BX </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 0 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R10D </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_BX </BASE0> +<INDEX> _ => REG_SI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_R11D </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_BX </BASE0> +<INDEX> _ => REG_DI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_R12D </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_BP </BASE0> +<INDEX> _ => REG_SI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_R13D </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_BP </BASE0> +<INDEX> _ => REG_DI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_R14D </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_SI </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_R15D </OUTREG> -<k> VGPR32_R_64 => . ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_DI </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 5 </RM> -syntax K ::= "VGPR64_R" -rule <OUTREG> _ => REG_RAX </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_BP </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_RCX </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <NEEDMEMDISP> _ => 8 </NEEDMEMDISP> +<BASE0> _ => REG_BX </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 1 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_RDX </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> +<BASE0> _ => REG_BX </BASE0> +<INDEX> _ => REG_SI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 0 </RM> -rule <OUTREG> _ => REG_RBX </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> +<BASE0> _ => REG_BX </BASE0> +<INDEX> _ => REG_DI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 1 </RM> -rule <OUTREG> _ => REG_RSP </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> +<BASE0> _ => REG_BP </BASE0> +<INDEX> _ => REG_SI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 2 </RM> -rule <OUTREG> _ => REG_RBP </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> +<BASE0> _ => REG_BP </BASE0> +<INDEX> _ => REG_DI </INDEX> +<SCALE> _ => 1 </SCALE> +<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 3 </RM> -rule <OUTREG> _ => REG_RSI </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> +<BASE0> _ => REG_SI </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 4 </RM> -rule <OUTREG> _ => REG_RDI </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> +<BASE0> _ => REG_DI </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 5 </RM> -rule <OUTREG> _ => REG_R8 </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> +<BASE0> _ => REG_BP </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 6 </RM> -rule <OUTREG> _ => REG_R9 </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <NEEDMEMDISP> _ => 16 </NEEDMEMDISP> +<BASE0> _ => REG_BX </BASE0> +<INDEX> _ => REG_INVALID </INDEX> +<k> MODRM16 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<MOD> 2 </MOD> +<RM> 7 </RM> -rule <OUTREG> _ => REG_R10 </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 1 </REXR> -<REG> 2 </REG> +syntax K ::= "XMM_N" +rule <k> XMM_N => XMM_N_32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_R11 </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <k> XMM_N => XMM_N_32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_R12 </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <k> XMM_N => XMM_N_64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_R13 </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 1 </REXR> -<REG> 5 </REG> +syntax K ::= "FINAL_ESEG" +rule <OUTREG> _ => REG_ES </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_ESEG => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_R14 </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_ES </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_ESEG => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_R15 </OUTREG> -<k> VGPR64_R => . ... </k> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_ESEG => . ... </k> +<MODE> 2 </MODE> -syntax K ::= "VGPR32_B_32" +syntax K ::= "VGPR32_N_64" rule <OUTREG> _ => REG_EAX </OUTREG> -<k> VGPR32_B_32 => . ... </k> -<RM> 0 </RM> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> rule <OUTREG> _ => REG_ECX </OUTREG> -<k> VGPR32_B_32 => . ... </k> -<RM> 1 </RM> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> rule <OUTREG> _ => REG_EDX </OUTREG> -<k> VGPR32_B_32 => . ... </k> -<RM> 2 </RM> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> rule <OUTREG> _ => REG_EBX </OUTREG> -<k> VGPR32_B_32 => . ... </k> -<RM> 3 </RM> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> rule <OUTREG> _ => REG_ESP </OUTREG> -<k> VGPR32_B_32 => . ... </k> -<RM> 4 </RM> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> rule <OUTREG> _ => REG_EBP </OUTREG> -<k> VGPR32_B_32 => . ... </k> -<RM> 5 </RM> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> rule <OUTREG> _ => REG_ESI </OUTREG> -<k> VGPR32_B_32 => . ... </k> -<RM> 6 </RM> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> rule <OUTREG> _ => REG_EDI </OUTREG> -<k> VGPR32_B_32 => . ... </k> -<RM> 7 </RM> - - - -syntax K ::= "VGPR32_B_64" -rule <OUTREG> _ => REG_EAX </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 0 </RM> - - - -rule <OUTREG> _ => REG_ECX </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 1 </RM> - - - -rule <OUTREG> _ => REG_EDX </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 2 </RM> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <OUTREG> _ => REG_EBX </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 3 </RM> +rule <OUTREG> _ => REG_R8D </OUTREG> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_ESP </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 4 </RM> +rule <OUTREG> _ => REG_R9D </OUTREG> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_EBP </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 5 </RM> +rule <OUTREG> _ => REG_R10D </OUTREG> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <OUTREG> _ => REG_ESI </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 6 </RM> +rule <OUTREG> _ => REG_R11D </OUTREG> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_EDI </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 0 </REXB> -<RM> 7 </RM> +rule <OUTREG> _ => REG_R12D </OUTREG> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <OUTREG> _ => REG_R8D </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 0 </RM> +rule <OUTREG> _ => REG_R13D </OUTREG> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <OUTREG> _ => REG_R9D </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 1 </RM> +rule <OUTREG> _ => REG_R14D </OUTREG> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <OUTREG> _ => REG_R10D </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 2 </RM> +rule <OUTREG> _ => REG_R15D </OUTREG> +<k> VGPR32_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <OUTREG> _ => REG_R11D </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 3 </RM> +syntax K ::= "ESIZE_8_BITS" +rule <ELEMENTSIZE> _ => 8 </ELEMENTSIZE> +<k> ESIZE_8_BITS => . ... </k> +<REX> 0 </REX> -rule <OUTREG> _ => REG_R12D </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 4 </RM> +syntax K ::= "IGNORE66" +rule <EOSZ> _ => 1 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> IGNORE66 => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_R13D </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 5 </RM> +rule <EOSZ> _ => 2 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> IGNORE66 => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_R14D </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 6 </RM> +rule <EOSZ> _ => 2 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> IGNORE66 => . ... </k> +<MODE> 2 </MODE> +<REXW> 0 </REXW> -rule <OUTREG> _ => REG_R15D </OUTREG> -<k> VGPR32_B_64 => . ... </k> -<REXB> 1 </REXB> -<RM> 7 </RM> +rule <EOSZ> _ => 3 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> IGNORE66 => . ... </k> +<MODE> 2 </MODE> +<REXW> 1 </REXW> @@ -138761,5865 +139519,5107 @@ rule <OUTREG> _ => REG_R15 </OUTREG> -syntax K ::= "NELEM_TUPLE1_4X" -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_TUPLE1_4X => . ... </k> -<VL> 0 </VL> +syntax K ::= "ZMM_R3_32" +rule <OUTREG> _ => REG_ZMM0 </OUTREG> +<k> ZMM_R3_32 => . ... </k> +<REG> 0 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_TUPLE1_4X => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM1 </OUTREG> +<k> ZMM_R3_32 => . ... </k> +<REG> 1 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_TUPLE1_4X => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_ZMM2 </OUTREG> +<k> ZMM_R3_32 => . ... </k> +<REG> 2 </REG> -syntax K ::= "AVX512_ROUND" -rule <ROUNDC> _ => 1 </ROUNDC> -<SAE> _ => 1 </SAE> -<k> AVX512_ROUND => . ... </k> -<LLRC> 0 </LLRC> +rule <OUTREG> _ => REG_ZMM3 </OUTREG> +<k> ZMM_R3_32 => . ... </k> +<REG> 3 </REG> -rule <ROUNDC> _ => 2 </ROUNDC> -<SAE> _ => 1 </SAE> -<k> AVX512_ROUND => . ... </k> -<LLRC> 1 </LLRC> +rule <OUTREG> _ => REG_ZMM4 </OUTREG> +<k> ZMM_R3_32 => . ... </k> +<REG> 4 </REG> -rule <ROUNDC> _ => 3 </ROUNDC> -<SAE> _ => 1 </SAE> -<k> AVX512_ROUND => . ... </k> -<LLRC> 2 </LLRC> +rule <OUTREG> _ => REG_ZMM5 </OUTREG> +<k> ZMM_R3_32 => . ... </k> +<REG> 5 </REG> -rule <ROUNDC> _ => 4 </ROUNDC> -<SAE> _ => 1 </SAE> -<k> AVX512_ROUND => . ... </k> -<LLRC> 3 </LLRC> +rule <OUTREG> _ => REG_ZMM6 </OUTREG> +<k> ZMM_R3_32 => . ... </k> +<REG> 6 </REG> -syntax K ::= "SAE" -rule <SAE> _ => 1 </SAE> -<k> SAE => . ... </k> -<BCRC> 1 </BCRC> +rule <OUTREG> _ => REG_ZMM7 </OUTREG> +<k> ZMM_R3_32 => . ... </k> +<REG> 7 </REG> -rule <k> SAE => DecoderError ... </k> -<BCRC> 0 </BCRC> +syntax K ::= "UIMM8" +rule <IMMWIDTH> _ => 8 </IMMWIDTH> +<k> UIMM8 => . ... </k> -syntax K ::= "ESIZE_128_BITS" -rule <ELEMENTSIZE> _ => 128 </ELEMENTSIZE> -<k> ESIZE_128_BITS => . ... </k> -<REX> 0 </REX> +syntax K ::= "GPR8_R" +rule <OUTREG> _ => REG_AL </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -syntax K ::= "ESIZE_64_BITS" -rule <ELEMENTSIZE> _ => 64 </ELEMENTSIZE> -<k> ESIZE_64_BITS => . ... </k> -<REX> 0 </REX> +rule <OUTREG> _ => REG_CL </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -syntax K ::= "ESIZE_32_BITS" -rule <ELEMENTSIZE> _ => 32 </ELEMENTSIZE> -<k> ESIZE_32_BITS => . ... </k> -<REX> 0 </REX> +rule <OUTREG> _ => REG_DL </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -syntax K ::= "ESIZE_16_BITS" -rule <ELEMENTSIZE> _ => 16 </ELEMENTSIZE> -<k> ESIZE_16_BITS => . ... </k> -<REX> 0 </REX> +rule <OUTREG> _ => REG_BL </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -syntax K ::= "ESIZE_8_BITS" -rule <ELEMENTSIZE> _ => 8 </ELEMENTSIZE> -<k> ESIZE_8_BITS => . ... </k> +rule <OUTREG> _ => REG_AH </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> <REX> 0 </REX> -syntax K ::= "ESIZE_4_BITS" -rule <ELEMENTSIZE> _ => 4 </ELEMENTSIZE> -<k> ESIZE_4_BITS => . ... </k> +rule <OUTREG> _ => REG_CH </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> <REX> 0 </REX> -syntax K ::= "ESIZE_2_BITS" -rule <ELEMENTSIZE> _ => 2 </ELEMENTSIZE> -<k> ESIZE_2_BITS => . ... </k> +rule <OUTREG> _ => REG_DH </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> <REX> 0 </REX> -syntax K ::= "ESIZE_1_BITS" -rule <ELEMENTSIZE> _ => 1 </ELEMENTSIZE> -<k> ESIZE_1_BITS => . ... </k> +rule <OUTREG> _ => REG_BH </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> <REX> 0 </REX> -syntax K ::= "NELEM_MOVDDUP" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_MOVDDUP => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_SPL </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> +<REX> 1 </REX> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_MOVDDUP => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_BPL </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> +<REX> 1 </REX> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_MOVDDUP => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_SIL </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> +<REX> 1 </REX> -syntax K ::= "NELEM_FULLMEM" -rule <NELEM> _ => 512 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_DIL </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> +<REX> 1 </REX> -rule <NELEM> _ => 256 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R8B </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <NELEM> _ => 128 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R9B </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <NELEM> _ => 64 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R10B </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R11B </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R12B </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R13B </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R14B </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R15B </OUTREG> +<k> GPR8_R => . ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 2 </VL> +syntax K ::= "XMM_R3_32" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_R3_32 => . ... </k> +<REG> 0 </REG> -rule <NELEM> _ => 256 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_R3_32 => . ... </k> +<REG> 1 </REG> -rule <NELEM> _ => 128 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_R3_32 => . ... </k> +<REG> 2 </REG> -rule <NELEM> _ => 64 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_R3_32 => . ... </k> +<REG> 3 </REG> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_R3_32 => . ... </k> +<REG> 4 </REG> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_R3_32 => . ... </k> +<REG> 5 </REG> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_R3_32 => . ... </k> +<REG> 6 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_R3_32 => . ... </k> +<REG> 7 </REG> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 1 </VL> +syntax K ::= "NELEM_GPR_WRITER_LDOP_D" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_LDOP_D => . ... </k> +<VL> 0 </VL> rule <NELEM> _ => 1 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> +<k> NELEM_GPR_WRITER_LDOP_D => . ... </k> <VL> 1 </VL> -rule <k> NELEM_FULLMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 1 </VL> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_LDOP_D => . ... </k> +<VL> 2 </VL> -rule <NELEM> _ => 128 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 0 </VL> +syntax K ::= "YMM_N_64" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <NELEM> _ => 64 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_FULLMEM => . ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <k> NELEM_FULLMEM => DecoderError ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM8 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <k> NELEM_FULLMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM9 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -syntax K ::= "NELEM_HALFMEM" -rule <NELEM> _ => 256 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM10 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <NELEM> _ => 128 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM11 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <NELEM> _ => 64 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM12 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM13 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM14 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM15 </OUTREG> +<k> YMM_N_64 => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 2 </VL> +syntax K ::= "NELEM_TUPLE8" +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_TUPLE8 => . ... </k> +<VL> 0 </VL> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 2 </VL> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_TUPLE8 => . ... </k> +<VL> 1 </VL> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_TUPLE8 => . ... </k> <VL> 2 </VL> -rule <k> NELEM_HALFMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 2 </VL> - - +syntax K ::= "GPR32_R" +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <NELEM> _ => 128 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <NELEM> _ => 64 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R8D </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <k> NELEM_HALFMEM => DecoderError ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R9D </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <k> NELEM_HALFMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R10D </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <NELEM> _ => 64 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_R11D </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_R12D </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_R13D </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_R14D </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_R15D </OUTREG> +<k> GPR32_R => . ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 0 </VL> +syntax K ::= "MEMDISP16" +rule <DISPWIDTH> _ => 16 </DISPWIDTH> +<k> MEMDISP16 => . ... </k> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_HALFMEM => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 0 </VL> +syntax K ::= "YMM_B_32" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_B_32 => . ... </k> +<RM> 0 </RM> -rule <k> NELEM_HALFMEM => DecoderError ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_B_32 => . ... </k> +<RM> 1 </RM> -rule <k> NELEM_HALFMEM => DecoderError ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_B_32 => . ... </k> +<RM> 2 </RM> -rule <k> NELEM_HALFMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_B_32 => . ... </k> +<RM> 3 </RM> -syntax K ::= "NELEM_QUARTERMEM" -rule <NELEM> _ => 128 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_B_32 => . ... </k> +<RM> 4 </RM> -rule <NELEM> _ => 64 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_B_32 => . ... </k> +<RM> 5 </RM> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_B_32 => . ... </k> +<RM> 6 </RM> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_B_32 => . ... </k> +<RM> 7 </RM> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 2 </VL> +syntax K ::= "YMM_R_64" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <k> NELEM_QUARTERMEM => DecoderError ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <k> NELEM_QUARTERMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <NELEM> _ => 64 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM8 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM9 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM10 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM11 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM12 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <k> NELEM_QUARTERMEM => DecoderError ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM13 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <k> NELEM_QUARTERMEM => DecoderError ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM14 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <k> NELEM_QUARTERMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_YMM15 </OUTREG> +<k> YMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 0 </VL> +syntax K ::= "UISA_VSIB_BASE" +rule <k> UISA_VSIB_BASE => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 0 </SIBBASE> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 0 </VL> +rule <k> UISA_VSIB_BASE => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 1 </SIBBASE> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 0 </VL> +rule <k> UISA_VSIB_BASE => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 2 </SIBBASE> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 0 </VL> +rule <k> UISA_VSIB_BASE => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 3 </SIBBASE> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 0 </VL> +rule <k> UISA_VSIB_BASE => ArSP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 4 </SIBBASE> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_QUARTERMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 0 </VL> +rule <BASE0> _ => REG_INVALID </BASE0> +<k> UISA_VSIB_BASE => MEMDISP32 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 0 </MOD> -rule <k> NELEM_QUARTERMEM => DecoderError ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 0 </VL> +rule <k> UISA_VSIB_BASE => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> I1:Int </MOD> +requires I1 =/=Int 0 -rule <k> NELEM_QUARTERMEM => DecoderError ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 0 </VL> +rule <k> UISA_VSIB_BASE => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 6 </SIBBASE> -rule <k> NELEM_QUARTERMEM => DecoderError ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 0 </VL> +rule <k> UISA_VSIB_BASE => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 7 </SIBBASE> -rule <k> NELEM_QUARTERMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 0 </VL> +rule <k> UISA_VSIB_BASE => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 0 </SIBBASE> -syntax K ::= "NELEM_EIGHTHMEM" -rule <NELEM> _ => 64 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 2 </VL> +rule <k> UISA_VSIB_BASE => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 1 </SIBBASE> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 2 </VL> +rule <k> UISA_VSIB_BASE => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 2 </SIBBASE> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 2 </VL> +rule <k> UISA_VSIB_BASE => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 3 </SIBBASE> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 2 </VL> +rule <k> UISA_VSIB_BASE => Ar12 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 4 </SIBBASE> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 2 </VL> +rule <BASE0> _ => REG_INVALID </BASE0> +<k> UISA_VSIB_BASE => MEMDISP32 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 0 </MOD> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 2 </VL> +rule <k> UISA_VSIB_BASE => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> I1:Int </MOD> +requires I1 =/=Int 0 -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 2 </VL> +rule <k> UISA_VSIB_BASE => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 6 </SIBBASE> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 2 </VL> +rule <k> UISA_VSIB_BASE => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 7 </SIBBASE> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 2 </VL> +syntax K ::= "ZMM_N3_64" +rule <OUTREG> _ => REG_ZMM0 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_ZMM1 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM2 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM3 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM4 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM5 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM6 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM7 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM8 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM9 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM10 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM11 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 1 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM12 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 2 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM13 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 4 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM14 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 8 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM15 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 0 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_EIGHTHMEM => . ... </k> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM16 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM17 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM18 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 128 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM19 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 256 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM20 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> -<ELEMENTSIZE> 512 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM21 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -syntax K ::= "NELEM_GPR_READER_BYTE" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER_BYTE => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM22 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER_BYTE => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM23 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER_BYTE => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_ZMM24 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -syntax K ::= "NELEM_GPR_READER_WORD" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER_WORD => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM25 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER_WORD => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM26 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER_WORD => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_ZMM27 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -syntax K ::= "NELEM_GPR_WRITER_LDOP_D" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_LDOP_D => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM28 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_LDOP_D => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ZMM29 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_LDOP_D => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_ZMM30 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -syntax K ::= "NELEM_GPR_WRITER_LDOP_Q" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_LDOP_Q => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ZMM31 </OUTREG> +<k> ZMM_N3_64 => . ... </k> +<VEXDEST4> 1 </VEXDEST4> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_LDOP_Q => . ... </k> -<VL> 1 </VL> +syntax K ::= "MASKNOT0" +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> MASKNOT0 => . ... </k> +<MASK> 0 </MASK> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_LDOP_Q => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_K1 </OUTREG> +<k> MASKNOT0 => . ... </k> +<MASK> 1 </MASK> -syntax K ::= "NELEM_GPR_WRITER_STORE_BYTE" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE_BYTE => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_K2 </OUTREG> +<k> MASKNOT0 => . ... </k> +<MASK> 2 </MASK> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE_BYTE => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_K3 </OUTREG> +<k> MASKNOT0 => . ... </k> +<MASK> 3 </MASK> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE_BYTE => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_K4 </OUTREG> +<k> MASKNOT0 => . ... </k> +<MASK> 4 </MASK> -syntax K ::= "NELEM_GPR_WRITER_STORE_WORD" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE_WORD => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_K5 </OUTREG> +<k> MASKNOT0 => . ... </k> +<MASK> 5 </MASK> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE_WORD => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_K6 </OUTREG> +<k> MASKNOT0 => . ... </k> +<MASK> 6 </MASK> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE_WORD => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_K7 </OUTREG> +<k> MASKNOT0 => . ... </k> +<MASK> 7 </MASK> -syntax K ::= "NELEM_TUPLE1_BYTE" +syntax K ::= "NELEM_GPR_READER_BYTE" rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1_BYTE => . ... </k> +<k> NELEM_GPR_READER_BYTE => . ... </k> <VL> 0 </VL> rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1_BYTE => . ... </k> +<k> NELEM_GPR_READER_BYTE => . ... </k> <VL> 1 </VL> rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1_BYTE => . ... </k> +<k> NELEM_GPR_READER_BYTE => . ... </k> <VL> 2 </VL> -syntax K ::= "NELEM_TUPLE1_WORD" +syntax K ::= "NELEM_GPR_WRITER_STORE_BYTE" rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1_WORD => . ... </k> +<k> NELEM_GPR_WRITER_STORE_BYTE => . ... </k> <VL> 0 </VL> rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1_WORD => . ... </k> +<k> NELEM_GPR_WRITER_STORE_BYTE => . ... </k> <VL> 1 </VL> rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1_WORD => . ... </k> +<k> NELEM_GPR_WRITER_STORE_BYTE => . ... </k> <VL> 2 </VL> -syntax K ::= "NELEM_SCALAR" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_SCALAR => . ... </k> -<VL> 0 </VL> +syntax K ::= "GPR16_B" +rule <OUTREG> _ => REG_AX </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 0 </REXB> +<RM> 0 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_SCALAR => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_CX </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 0 </REXB> +<RM> 1 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_SCALAR => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_DX </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 0 </REXB> +<RM> 2 </RM> -syntax K ::= "NELEM_TUPLE1_SUBDWORD" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1_SUBDWORD => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_BX </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1_SUBDWORD => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_SP </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 0 </REXB> +<RM> 4 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1_SUBDWORD => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_BP </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 0 </REXB> +<RM> 5 </RM> -syntax K ::= "NELEM_GPR_READER" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_SI </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_DI </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 0 </REXB> +<RM> 7 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R8W </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 1 </REXB> +<RM> 0 </RM> -syntax K ::= "NELEM_GPR_READER_SUBDWORD" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER_SUBDWORD => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_R9W </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER_SUBDWORD => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R10W </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_READER_SUBDWORD => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R11W </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 1 </REXB> +<RM> 3 </RM> -syntax K ::= "NELEM_GPR_WRITER_LDOP" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_LDOP => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_R12W </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 1 </REXB> +<RM> 4 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_LDOP => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R13W </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 1 </REXB> +<RM> 5 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_LDOP => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R14W </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 1 </REXB> +<RM> 6 </RM> -syntax K ::= "NELEM_GPR_WRITER_STORE" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_R15W </OUTREG> +<k> GPR16_B => . ... </k> +<REXB> 1 </REXB> +<RM> 7 </RM> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE => . ... </k> -<VL> 1 </VL> +syntax K ::= "SrSP" +rule <OUTREG> _ => REG_SP </OUTREG> +<k> SrSP => . ... </k> +<SMODE> 0 </SMODE> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> SrSP => . ... </k> +<SMODE> 1 </SMODE> -syntax K ::= "NELEM_GPR_WRITER_STORE_SUBDWORD" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE_SUBDWORD => . ... </k> -<VL> 0 </VL> +rule <OUTREG> _ => REG_RSP </OUTREG> +<k> SrSP => . ... </k> +<SMODE> 2 </SMODE> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE_SUBDWORD => . ... </k> -<VL> 1 </VL> +syntax K ::= "NELEM_HALF" +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_HALF => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 2 </VL> rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GPR_WRITER_STORE_SUBDWORD => . ... </k> +<BCAST> _ => 3 </BCAST> +<k> NELEM_HALF => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> <VL> 2 </VL> -syntax K ::= "NELEM_TUPLE1" -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1 => . ... </k> -<VL> 0 </VL> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_HALF => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 1 </VL> rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1 => . ... </k> +<BCAST> _ => 10 </BCAST> +<k> NELEM_HALF => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> <VL> 1 </VL> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_TUPLE1 => . ... </k> -<VL> 2 </VL> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_HALF => . ... </k> +<BCRC> 0 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 0 </VL> -syntax K ::= "NELEM_GSCAT" rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GSCAT => . ... </k> +<BCAST> _ => 22 </BCAST> +<k> NELEM_HALF => . ... </k> +<BCRC> 1 </BCRC> +<ELEMENTSIZE> 32 </ELEMENTSIZE> <VL> 0 </VL> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GSCAT => . ... </k> -<VL> 1 </VL> +syntax K ::= "VGPR32_N" +rule <k> VGPR32_N => VGPR32_N_32 ... </k> +<MODE> 0 </MODE> -rule <NELEM> _ => 1 </NELEM> -<k> NELEM_GSCAT => . ... </k> -<VL> 2 </VL> +rule <k> VGPR32_N => VGPR32_N_32 ... </k> +<MODE> 1 </MODE> -syntax K ::= "NELEM_TUPLE2" -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_TUPLE2 => . ... </k> +rule <k> VGPR32_N => VGPR32_N_64 ... </k> +<MODE> 2 </MODE> + + + +syntax K ::= "NELEM_GPR_READER" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_READER => . ... </k> <VL> 0 </VL> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_TUPLE2 => . ... </k> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_READER => . ... </k> <VL> 1 </VL> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_TUPLE2 => . ... </k> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_READER => . ... </k> <VL> 2 </VL> -syntax K ::= "NELEM_TUPLE4" -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_TUPLE4 => . ... </k> -<VL> 0 </VL> - - +syntax K ::= "ZMM_N3" +rule <k> ZMM_N3 => ZMM_N3_32 ... </k> +<MODE> 0 </MODE> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_TUPLE4 => . ... </k> -<VL> 1 </VL> +rule <k> ZMM_N3 => ZMM_N3_32 ... </k> +<MODE> 1 </MODE> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_TUPLE4 => . ... </k> -<VL> 2 </VL> +rule <k> ZMM_N3 => ZMM_N3_64 ... </k> +<MODE> 2 </MODE> -syntax K ::= "NELEM_TUPLE8" -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_TUPLE8 => . ... </k> -<VL> 0 </VL> +syntax K ::= "GPR64_B" +rule <OUTREG> _ => REG_RAX </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 0 </REXB> +<RM> 0 </RM> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_TUPLE8 => . ... </k> -<VL> 1 </VL> +rule <OUTREG> _ => REG_RCX </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 0 </REXB> +<RM> 1 </RM> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_TUPLE8 => . ... </k> -<VL> 2 </VL> +rule <OUTREG> _ => REG_RDX </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 0 </REXB> +<RM> 2 </RM> -syntax K ::= "NELEM_MEM128" -rule <ELEMENTSIZE> _ => 64 </ELEMENTSIZE> -<NELEM> _ => 2 </NELEM> -<k> NELEM_MEM128 => . ... </k> -<BCRC> 0 </BCRC> +rule <OUTREG> _ => REG_RBX </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <k> NELEM_MEM128 => DecoderError ... </k> -<BCRC> 1 </BCRC> +rule <OUTREG> _ => REG_RSP </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 0 </REXB> +<RM> 4 </RM> -syntax K ::= "NELEM_FULL" -rule <NELEM> _ => 32 </NELEM> -<k> NELEM_FULL => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_RBP </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 0 </REXB> +<RM> 5 </RM> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 16 </BCAST> -<k> NELEM_FULL => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_RSI </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_FULL => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_RDI </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 0 </REXB> +<RM> 7 </RM> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 1 </BCAST> -<k> NELEM_FULL => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R8 </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 1 </REXB> +<RM> 0 </RM> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_FULL => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R9 </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 5 </BCAST> -<k> NELEM_FULL => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_R10 </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <NELEM> _ => 16 </NELEM> -<k> NELEM_FULL => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R11 </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 1 </REXB> +<RM> 3 </RM> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 15 </BCAST> -<k> NELEM_FULL => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R12 </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 1 </REXB> +<RM> 4 </RM> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_FULL => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R13 </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 1 </REXB> +<RM> 5 </RM> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 3 </BCAST> -<k> NELEM_FULL => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R14 </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 1 </REXB> +<RM> 6 </RM> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_FULL => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_R15 </OUTREG> +<k> GPR64_B => . ... </k> +<REXB> 1 </REXB> +<RM> 7 </RM> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 13 </BCAST> -<k> NELEM_FULL => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 1 </VL> +syntax K ::= "BND_R" +rule <OUTREG> _ => REG_BND0 </OUTREG> +<k> BND_R => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_FULL => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_BND1 </OUTREG> +<k> BND_R => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 14 </BCAST> -<k> NELEM_FULL => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 16 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_BND2 </OUTREG> +<k> BND_R => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_FULL => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_BND3 </OUTREG> +<k> BND_R => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 10 </BCAST> -<k> NELEM_FULL => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> BND_R => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_FULL => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 11 </BCAST> -<k> NELEM_FULL => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 64 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> -syntax K ::= "NELEM_HALF" -rule <NELEM> _ => 8 </NELEM> -<k> NELEM_HALF => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 3 </BCAST> -<k> NELEM_HALF => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 2 </VL> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <NELEM> _ => 4 </NELEM> -<k> NELEM_HALF => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 10 </BCAST> -<k> NELEM_HALF => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 1 </VL> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <NELEM> _ => 2 </NELEM> -<k> NELEM_HALF => . ... </k> -<BCRC> 0 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <NELEM> _ => 1 </NELEM> -<BCAST> _ => 22 </BCAST> -<k> NELEM_HALF => . ... </k> -<BCRC> 1 </BCRC> -<ELEMENTSIZE> 32 </ELEMENTSIZE> -<VL> 0 </VL> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -syntax K ::= "FIX_ROUND_LEN512" -rule <VL> _ => 2 </VL> -<k> FIX_ROUND_LEN512 => . ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <VL> _ => 2 </VL> -<k> FIX_ROUND_LEN512 => . ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <VL> _ => 2 </VL> -<k> FIX_ROUND_LEN512 => . ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> BND_R => . ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -syntax K ::= "FIX_ROUND_LEN128" -rule <VL> _ => 0 </VL> -<k> FIX_ROUND_LEN128 => . ... </k> -<MODE> 0 </MODE> +syntax K ::= "SE_IMM8" +rule <IMMWIDTH> _ => 8 </IMMWIDTH> +<k> SE_IMM8 => . ... </k> -rule <VL> _ => 0 </VL> -<k> FIX_ROUND_LEN128 => . ... </k> -<MODE> 1 </MODE> +syntax K ::= "ArBX" +rule <OUTREG> _ => REG_BX </OUTREG> +<k> ArBX => . ... </k> +<EASZ> 1 </EASZ> -rule <VL> _ => 0 </VL> -<k> FIX_ROUND_LEN128 => . ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> ArBX => . ... </k> +<EASZ> 2 </EASZ> -syntax K ::= "UISA_VMODRM_ZMM" -rule <k> UISA_VMODRM_ZMM => UISA_VSIB_ZMM ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_RBX </OUTREG> +<k> ArBX => . ... </k> +<EASZ> 3 </EASZ> -rule <k> UISA_VMODRM_ZMM => UISA_VSIB_ZMM ~> MEMDISP8 ... </k> -<MOD> 1 </MOD> +syntax K ::= "FINAL_DSEG" +rule <k> FINAL_DSEG => FINAL_DSEG_NOT64 ... </k> +<MODE> 0 </MODE> -rule <k> UISA_VMODRM_ZMM => UISA_VSIB_ZMM ~> MEMDISP32 ... </k> -<MOD> 2 </MOD> +rule <k> FINAL_DSEG => FINAL_DSEG_NOT64 ... </k> +<MODE> 1 </MODE> -syntax K ::= "UISA_VMODRM_YMM" -rule <k> UISA_VMODRM_YMM => UISA_VSIB_YMM ... </k> -<MOD> 0 </MOD> +rule <k> FINAL_DSEG => FINAL_DSEG_MODE64 ... </k> +<MODE> 2 </MODE> -rule <k> UISA_VMODRM_YMM => UISA_VSIB_YMM ~> MEMDISP8 ... </k> -<MOD> 1 </MOD> +syntax K ::= "VGPR64_R" +rule <OUTREG> _ => REG_RAX </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <k> UISA_VMODRM_YMM => UISA_VSIB_YMM ~> MEMDISP32 ... </k> -<MOD> 2 </MOD> +rule <OUTREG> _ => REG_RCX </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -syntax K ::= "UISA_VMODRM_XMM" -rule <k> UISA_VMODRM_XMM => UISA_VSIB_XMM ... </k> -<MOD> 0 </MOD> +rule <OUTREG> _ => REG_RDX </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <k> UISA_VMODRM_XMM => UISA_VSIB_XMM ~> MEMDISP8 ... </k> -<MOD> 1 </MOD> +rule <OUTREG> _ => REG_RBX </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <k> UISA_VMODRM_XMM => UISA_VSIB_XMM ~> MEMDISP32 ... </k> -<MOD> 2 </MOD> +rule <OUTREG> _ => REG_RSP </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> -syntax K ::= "UISA_VSIB_ZMM" -rule <SCALE> _ => 1 </SCALE> -<k> UISA_VSIB_ZMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_ZMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> +rule <OUTREG> _ => REG_RBP </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <SCALE> _ => 2 </SCALE> -<k> UISA_VSIB_ZMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_ZMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> +rule <OUTREG> _ => REG_RSI </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <SCALE> _ => 4 </SCALE> -<k> UISA_VSIB_ZMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_ZMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> +rule <OUTREG> _ => REG_RDI </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <SCALE> _ => 8 </SCALE> -<k> UISA_VSIB_ZMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_ZMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> +rule <OUTREG> _ => REG_R8 </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -syntax K ::= "UISA_VSIB_YMM" -rule <SCALE> _ => 1 </SCALE> -<k> UISA_VSIB_YMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> +rule <OUTREG> _ => REG_R9 </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <SCALE> _ => 2 </SCALE> -<k> UISA_VSIB_YMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> +rule <OUTREG> _ => REG_R10 </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <SCALE> _ => 4 </SCALE> -<k> UISA_VSIB_YMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> +rule <OUTREG> _ => REG_R11 </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <SCALE> _ => 8 </SCALE> -<k> UISA_VSIB_YMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> +rule <OUTREG> _ => REG_R12 </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -syntax K ::= "UISA_VSIB_XMM" -rule <SCALE> _ => 1 </SCALE> -<k> UISA_VSIB_XMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 0 </SIBSCALE> +rule <OUTREG> _ => REG_R13 </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <SCALE> _ => 2 </SCALE> -<k> UISA_VSIB_XMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 1 </SIBSCALE> +rule <OUTREG> _ => REG_R14 </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <SCALE> _ => 4 </SCALE> -<k> UISA_VSIB_XMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 2 </SIBSCALE> +rule <OUTREG> _ => REG_R15 </OUTREG> +<k> VGPR64_R => . ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <SCALE> _ => 8 </SCALE> -<k> UISA_VSIB_XMM => UISA_VSIB_BASE ~> UISA_VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> -<SIBSCALE> 3 </SIBSCALE> +syntax K ::= "FIX_ROUND_LEN512" +rule <VL> _ => 2 </VL> +<k> FIX_ROUND_LEN512 => . ... </k> +<MODE> 0 </MODE> -syntax K ::= "UISA_VSIB_INDEX_ZMM" -rule <OUTREG> _ => REG_ZMM0 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <VL> _ => 2 </VL> +<k> FIX_ROUND_LEN512 => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_ZMM1 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <VL> _ => 2 </VL> +<k> FIX_ROUND_LEN512 => . ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_ZMM2 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +syntax K ::= "XMM_B" +rule <k> XMM_B => XMM_B_32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_ZMM3 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <k> XMM_B => XMM_B_32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_ZMM4 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <k> XMM_B => XMM_B_64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_ZMM5 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +syntax K ::= "GPRy_B" +rule <k> GPRy_B => GPR64_B ... </k> +<EOSZ> 3 </EOSZ> -rule <OUTREG> _ => REG_ZMM6 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <k> GPRy_B => GPR32_B ... </k> +<EOSZ> 2 </EOSZ> -rule <OUTREG> _ => REG_ZMM7 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <k> GPRy_B => GPR32_B ... </k> +<EOSZ> 1 </EOSZ> -rule <OUTREG> _ => REG_ZMM8 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> +syntax K ::= "YMM_R3_64" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <OUTREG> _ => REG_ZMM9 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_ZMM10 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_ZMM11 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_ZMM12 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_ZMM13 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_ZMM14 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <OUTREG> _ => REG_ZMM15 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <OUTREG> _ => REG_ZMM16 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <OUTREG> _ => REG_YMM8 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <OUTREG> _ => REG_ZMM17 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <OUTREG> _ => REG_YMM9 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_ZMM18 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_YMM10 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_ZMM19 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_YMM11 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_ZMM20 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <OUTREG> _ => REG_YMM12 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_ZMM21 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_YMM13 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_ZMM22 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_YMM14 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <OUTREG> _ => REG_ZMM23 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_YMM15 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 0 </REXRR> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <OUTREG> _ => REG_ZMM24 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <OUTREG> _ => REG_YMM16 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <OUTREG> _ => REG_ZMM25 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <OUTREG> _ => REG_YMM17 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_ZMM26 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_YMM18 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_ZMM27 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_YMM19 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_ZMM28 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <OUTREG> _ => REG_YMM20 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_ZMM29 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_YMM21 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_ZMM30 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_YMM22 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <OUTREG> _ => REG_ZMM31 </OUTREG> -<k> UISA_VSIB_INDEX_ZMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_YMM23 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 0 </REXR> +<REG> 7 </REG> -syntax K ::= "UISA_VSIB_INDEX_YMM" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <OUTREG> _ => REG_YMM24 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <OUTREG> _ => REG_YMM25 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_YMM26 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_YMM27 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <OUTREG> _ => REG_YMM28 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_YMM29 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_YMM30 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <OUTREG> _ => REG_YMM31 </OUTREG> +<k> YMM_R3_64 => . ... </k> +<REXRR> 1 </REXRR> +<REXR> 1 </REXR> +<REG> 7 </REG> -rule <OUTREG> _ => REG_YMM8 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> +syntax K ::= "VSIB_XMM" +rule <SCALE> _ => 1 </SCALE> +<k> VSIB_XMM => VSIB_BASE ~> VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> -rule <OUTREG> _ => REG_YMM9 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <SCALE> _ => 2 </SCALE> +<k> VSIB_XMM => VSIB_BASE ~> VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> -rule <OUTREG> _ => REG_YMM10 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <SCALE> _ => 4 </SCALE> +<k> VSIB_XMM => VSIB_BASE ~> VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> -rule <OUTREG> _ => REG_YMM11 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <SCALE> _ => 8 </SCALE> +<k> VSIB_XMM => VSIB_BASE ~> VSIB_INDEX_XMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> -rule <OUTREG> _ => REG_YMM12 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +syntax K ::= "NELEM_QUARTERMEM" +rule <NELEM> _ => 128 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM13 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <NELEM> _ => 64 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM14 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM15 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM16 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM17 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM18 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM19 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM20 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <k> NELEM_QUARTERMEM => DecoderError ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM21 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <k> NELEM_QUARTERMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM22 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <NELEM> _ => 64 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM23 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM24 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM25 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM26 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM27 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM28 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM29 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <k> NELEM_QUARTERMEM => DecoderError ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM30 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <k> NELEM_QUARTERMEM => DecoderError ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM31 </OUTREG> -<k> UISA_VSIB_INDEX_YMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <k> NELEM_QUARTERMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 1 </VL> -syntax K ::= "UISA_VSIB_INDEX_XMM" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_QUARTERMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <k> NELEM_QUARTERMEM => DecoderError ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <k> NELEM_QUARTERMEM => DecoderError ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM8 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <k> NELEM_QUARTERMEM => DecoderError ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM9 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <k> NELEM_QUARTERMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM10 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +syntax K ::= "ESIZE_64_BITS" +rule <ELEMENTSIZE> _ => 64 </ELEMENTSIZE> +<k> ESIZE_64_BITS => . ... </k> +<REX> 0 </REX> -rule <OUTREG> _ => REG_XMM11 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +syntax K ::= "OeAX" +rule <OUTREG> _ => REG_AX </OUTREG> +<k> OeAX => . ... </k> +<EOSZ> 1 </EOSZ> -rule <OUTREG> _ => REG_XMM12 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> OeAX => . ... </k> +<EOSZ> 2 </EOSZ> -rule <OUTREG> _ => REG_XMM13 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> OeAX => . ... </k> +<EOSZ> 3 </EOSZ> -rule <OUTREG> _ => REG_XMM14 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +syntax K ::= "XMM_R3" +rule <k> XMM_R3 => XMM_R3_32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_XMM15 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +rule <k> XMM_R3 => XMM_R3_32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_XMM16 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 0 </SIBINDEX> +rule <k> XMM_R3 => XMM_R3_64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_XMM17 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 1 </SIBINDEX> +syntax K ::= "SrBP" +rule <OUTREG> _ => REG_BP </OUTREG> +<k> SrBP => . ... </k> +<SMODE> 0 </SMODE> -rule <OUTREG> _ => REG_XMM18 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> SrBP => . ... </k> +<SMODE> 1 </SMODE> -rule <OUTREG> _ => REG_XMM19 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_RBP </OUTREG> +<k> SrBP => . ... </k> +<SMODE> 2 </SMODE> -rule <OUTREG> _ => REG_XMM20 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 4 </SIBINDEX> +syntax K ::= "rIP" +rule <OUTREG> _ => REG_EIP </OUTREG> +<k> rIP => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_XMM21 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <OUTREG> _ => REG_EIP </OUTREG> +<k> rIP => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_XMM22 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <OUTREG> _ => REG_RIP </OUTREG> +<k> rIP => . ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_XMM23 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 0 </REXX> -<SIBINDEX> 7 </SIBINDEX> +syntax K ::= "FINAL_SSEG_NOT64" +rule <OUTREG> _ => REG_CS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_NOT64 => . ... </k> +<SEGOVD> 1 </SEGOVD> -rule <OUTREG> _ => REG_XMM24 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 0 </SIBINDEX> + + +rule <OUTREG> _ => REG_DS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_NOT64 => . ... </k> +<SEGOVD> 2 </SEGOVD> -rule <OUTREG> _ => REG_XMM25 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 1 </SIBINDEX> +rule <OUTREG> _ => REG_ES </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_NOT64 => . ... </k> +<SEGOVD> 3 </SEGOVD> -rule <OUTREG> _ => REG_XMM26 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 2 </SIBINDEX> +rule <OUTREG> _ => REG_FS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_NOT64 => . ... </k> +<SEGOVD> 4 </SEGOVD> -rule <OUTREG> _ => REG_XMM27 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 3 </SIBINDEX> +rule <OUTREG> _ => REG_GS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 0 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG_NOT64 => . ... </k> +<SEGOVD> 5 </SEGOVD> -rule <OUTREG> _ => REG_XMM28 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 4 </SIBINDEX> +syntax K ::= "FIX_ROUND_LEN128" +rule <VL> _ => 0 </VL> +<k> FIX_ROUND_LEN128 => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_XMM29 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 5 </SIBINDEX> +rule <VL> _ => 0 </VL> +<k> FIX_ROUND_LEN128 => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_XMM30 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 6 </SIBINDEX> +rule <VL> _ => 0 </VL> +<k> FIX_ROUND_LEN128 => . ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_XMM31 </OUTREG> -<k> UISA_VSIB_INDEX_XMM => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<REXX> 1 </REXX> -<SIBINDEX> 7 </SIBINDEX> +syntax K ::= "NELEM_GSCAT" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GSCAT => . ... </k> +<VL> 0 </VL> -syntax K ::= "UISA_VSIB_BASE" -rule <k> UISA_VSIB_BASE => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 0 </SIBBASE> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GSCAT => . ... </k> +<VL> 1 </VL> -rule <k> UISA_VSIB_BASE => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 1 </SIBBASE> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GSCAT => . ... </k> +<VL> 2 </VL> -rule <k> UISA_VSIB_BASE => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 0 </REXB> -<SIBBASE> 2 </SIBBASE> +syntax K ::= "MEMDISP32" +rule <DISPWIDTH> _ => 32 </DISPWIDTH> +<k> MEMDISP32 => . ... </k> -rule <k> UISA_VSIB_BASE => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +syntax K ::= "XMM_B_64" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 0 </REXB> -<SIBBASE> 3 </SIBBASE> +<RM> 0 </RM> -rule <k> UISA_VSIB_BASE => ArSP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 0 </REXB> -<SIBBASE> 4 </SIBBASE> +<RM> 1 </RM> -rule <BASE0> _ => REG_INVALID </BASE0> -<k> UISA_VSIB_BASE => MEMDISP32 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 0 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 0 </MOD> +<RM> 2 </RM> -rule <k> UISA_VSIB_BASE => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 0 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> I1:Int </MOD> -requires I1 =/=Int 0 +<RM> 3 </RM> -rule <k> UISA_VSIB_BASE => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> + +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 0 </REXB> -<SIBBASE> 6 </SIBBASE> +<RM> 4 </RM> -rule <k> UISA_VSIB_BASE => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 0 </REXB> -<SIBBASE> 7 </SIBBASE> +<RM> 5 </RM> -rule <k> UISA_VSIB_BASE => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 0 </SIBBASE> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <k> UISA_VSIB_BASE => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> -<REXB> 1 </REXB> -<SIBBASE> 1 </SIBBASE> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 7 </RM> -rule <k> UISA_VSIB_BASE => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM8 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 1 </REXB> -<SIBBASE> 2 </SIBBASE> +<RM> 0 </RM> -rule <k> UISA_VSIB_BASE => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM9 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 1 </REXB> -<SIBBASE> 3 </SIBBASE> +<RM> 1 </RM> -rule <k> UISA_VSIB_BASE => Ar12 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM10 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 1 </REXB> -<SIBBASE> 4 </SIBBASE> +<RM> 2 </RM> -rule <BASE0> _ => REG_INVALID </BASE0> -<k> UISA_VSIB_BASE => MEMDISP32 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM11 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 1 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> 0 </MOD> +<RM> 3 </RM> -rule <k> UISA_VSIB_BASE => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM12 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 1 </REXB> -<SIBBASE> 5 </SIBBASE> -<MOD> I1:Int </MOD> -requires I1 =/=Int 0 +<RM> 4 </RM> -rule <k> UISA_VSIB_BASE => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> + +rule <OUTREG> _ => REG_XMM13 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 1 </REXB> -<SIBBASE> 6 </SIBBASE> +<RM> 5 </RM> -rule <k> UISA_VSIB_BASE => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +rule <OUTREG> _ => REG_XMM14 </OUTREG> +<k> XMM_B_64 => . ... </k> <REXB> 1 </REXB> -<SIBBASE> 7 </SIBBASE> +<RM> 6 </RM> -syntax K ::= "MASK1" -rule <OUTREG> _ => REG_K0 </OUTREG> -<k> MASK1 => . ... </k> -<MASK> 0 </MASK> +rule <OUTREG> _ => REG_XMM15 </OUTREG> +<k> XMM_B_64 => . ... </k> +<REXB> 1 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_K1 </OUTREG> -<k> MASK1 => . ... </k> -<MASK> 1 </MASK> +syntax K ::= "NELEM_FULLMEM" +rule <NELEM> _ => 512 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_K2 </OUTREG> -<k> MASK1 => . ... </k> -<MASK> 2 </MASK> +rule <NELEM> _ => 256 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_K3 </OUTREG> -<k> MASK1 => . ... </k> -<MASK> 3 </MASK> +rule <NELEM> _ => 128 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_K4 </OUTREG> -<k> MASK1 => . ... </k> -<MASK> 4 </MASK> +rule <NELEM> _ => 64 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_K5 </OUTREG> -<k> MASK1 => . ... </k> -<MASK> 5 </MASK> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_K6 </OUTREG> -<k> MASK1 => . ... </k> -<MASK> 6 </MASK> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_K7 </OUTREG> -<k> MASK1 => . ... </k> -<MASK> 7 </MASK> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 2 </VL> -syntax K ::= "MASKNOT0" -rule <OUTREG> _ => REG_ERROR </OUTREG> -<k> MASKNOT0 => . ... </k> -<MASK> 0 </MASK> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_K1 </OUTREG> -<k> MASKNOT0 => . ... </k> -<MASK> 1 </MASK> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_K2 </OUTREG> -<k> MASKNOT0 => . ... </k> -<MASK> 2 </MASK> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_K3 </OUTREG> -<k> MASKNOT0 => . ... </k> -<MASK> 3 </MASK> +rule <NELEM> _ => 256 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_K4 </OUTREG> -<k> MASKNOT0 => . ... </k> -<MASK> 4 </MASK> +rule <NELEM> _ => 128 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_K5 </OUTREG> -<k> MASKNOT0 => . ... </k> -<MASK> 5 </MASK> +rule <NELEM> _ => 64 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_K6 </OUTREG> -<k> MASKNOT0 => . ... </k> -<MASK> 6 </MASK> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_K7 </OUTREG> -<k> MASKNOT0 => . ... </k> -<MASK> 7 </MASK> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 1 </VL> -syntax K ::= "MASK_R" -rule <OUTREG> _ => REG_K0 </OUTREG> -<k> MASK_R => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_K1 </OUTREG> -<k> MASK_R => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_K2 </OUTREG> -<k> MASK_R => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_K3 </OUTREG> -<k> MASK_R => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_K4 </OUTREG> -<k> MASK_R => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <k> NELEM_FULLMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_K5 </OUTREG> -<k> MASK_R => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <NELEM> _ => 128 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_K6 </OUTREG> -<k> MASK_R => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <NELEM> _ => 64 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_K7 </OUTREG> -<k> MASK_R => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 0 </VL> -syntax K ::= "MASK_B" -rule <OUTREG> _ => REG_K0 </OUTREG> -<k> MASK_B => . ... </k> -<RM> 0 </RM> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_K1 </OUTREG> -<k> MASK_B => . ... </k> -<RM> 1 </RM> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_K2 </OUTREG> -<k> MASK_B => . ... </k> -<RM> 2 </RM> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_K3 </OUTREG> -<k> MASK_B => . ... </k> -<RM> 3 </RM> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_K4 </OUTREG> -<k> MASK_B => . ... </k> -<RM> 4 </RM> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_FULLMEM => . ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_K5 </OUTREG> -<k> MASK_B => . ... </k> -<RM> 5 </RM> +rule <k> NELEM_FULLMEM => DecoderError ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_K6 </OUTREG> -<k> MASK_B => . ... </k> -<RM> 6 </RM> +rule <k> NELEM_FULLMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_K7 </OUTREG> -<k> MASK_B => . ... </k> -<RM> 7 </RM> +syntax K ::= "YMM_SE32" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> YMM_SE32 => . ... </k> +<ESRC> 0 </ESRC> -syntax K ::= "MASK_N" -rule <k> MASK_N => MASK_N64 ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> YMM_SE32 => . ... </k> +<ESRC> 1 </ESRC> -rule <k> MASK_N => MASK_N32 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> YMM_SE32 => . ... </k> +<ESRC> 2 </ESRC> -rule <k> MASK_N => MASK_N32 ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> YMM_SE32 => . ... </k> +<ESRC> 3 </ESRC> -syntax K ::= "MASK_N64" -rule <OUTREG> _ => REG_K7 </OUTREG> -<k> MASK_N64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> YMM_SE32 => . ... </k> +<ESRC> 4 </ESRC> -rule <OUTREG> _ => REG_K6 </OUTREG> -<k> MASK_N64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> YMM_SE32 => . ... </k> +<ESRC> 5 </ESRC> -rule <OUTREG> _ => REG_K5 </OUTREG> -<k> MASK_N64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> YMM_SE32 => . ... </k> +<ESRC> 6 </ESRC> -rule <OUTREG> _ => REG_K4 </OUTREG> -<k> MASK_N64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> YMM_SE32 => . ... </k> +<ESRC> 7 </ESRC> -rule <OUTREG> _ => REG_K3 </OUTREG> -<k> MASK_N64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_SE32 => . ... </k> +<ESRC> 8 </ESRC> -rule <OUTREG> _ => REG_K2 </OUTREG> -<k> MASK_N64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_SE32 => . ... </k> +<ESRC> 9 </ESRC> -rule <OUTREG> _ => REG_K1 </OUTREG> -<k> MASK_N64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_SE32 => . ... </k> +<ESRC> 10 </ESRC> -rule <OUTREG> _ => REG_K0 </OUTREG> -<k> MASK_N64 => . ... </k> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_SE32 => . ... </k> +<ESRC> 11 </ESRC> -syntax K ::= "MASK_N32" -rule <OUTREG> _ => REG_K7 </OUTREG> -<k> MASK_N32 => . ... </k> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_SE32 => . ... </k> +<ESRC> 12 </ESRC> -rule <OUTREG> _ => REG_K6 </OUTREG> -<k> MASK_N32 => . ... </k> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_SE32 => . ... </k> +<ESRC> 13 </ESRC> -rule <OUTREG> _ => REG_K5 </OUTREG> -<k> MASK_N32 => . ... </k> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_SE32 => . ... </k> +<ESRC> 14 </ESRC> -rule <OUTREG> _ => REG_K4 </OUTREG> -<k> MASK_N32 => . ... </k> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_SE32 => . ... </k> +<ESRC> 15 </ESRC> -rule <OUTREG> _ => REG_K3 </OUTREG> -<k> MASK_N32 => . ... </k> -<VEXDEST210> 4 </VEXDEST210> +syntax K ::= "UIMM32" +rule <IMMWIDTH> _ => 32 </IMMWIDTH> +<k> UIMM32 => . ... </k> -rule <OUTREG> _ => REG_K2 </OUTREG> -<k> MASK_N32 => . ... </k> -<VEXDEST210> 5 </VEXDEST210> +syntax K ::= "XMM_N_32" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_N_32 => . ... </k> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_K1 </OUTREG> -<k> MASK_N32 => . ... </k> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_N_32 => . ... </k> <VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_K0 </OUTREG> -<k> MASK_N32 => . ... </k> -<VEXDEST210> 7 </VEXDEST210> - - - -syntax K ::= "GPRm_B" -rule <k> GPRm_B => GPR64_B ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_N_32 => . ... </k> +<VEXDEST210> 5 </VEXDEST210> -rule <k> GPRm_B => GPR32_B ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_N_32 => . ... </k> +<VEXDEST210> 4 </VEXDEST210> -rule <k> GPRm_B => GPR32_B ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_N_32 => . ... </k> +<VEXDEST210> 3 </VEXDEST210> -syntax K ::= "GPRm_R" -rule <k> GPRm_R => GPR64_R ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_N_32 => . ... </k> +<VEXDEST210> 2 </VEXDEST210> -rule <k> GPRm_R => GPR32_R ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_N_32 => . ... </k> +<VEXDEST210> 1 </VEXDEST210> -rule <k> GPRm_R => GPR32_R ... </k> -<MODE> 0 </MODE> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_N_32 => . ... </k> +<VEXDEST210> 0 </VEXDEST210> -syntax K ::= "XMM_R3" -rule <k> XMM_R3 => XMM_R3_32 ... </k> +syntax K ::= "VGPR32_R" +rule <k> VGPR32_R => VGPR32_R_32 ... </k> <MODE> 0 </MODE> -rule <k> XMM_R3 => XMM_R3_32 ... </k> +rule <k> VGPR32_R => VGPR32_R_32 ... </k> <MODE> 1 </MODE> -rule <k> XMM_R3 => XMM_R3_64 ... </k> +rule <k> VGPR32_R => VGPR32_R_64 ... </k> <MODE> 2 </MODE> -syntax K ::= "XMM_R3_32" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_R3_32 => . ... </k> -<REG> 0 </REG> - - - -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_R3_32 => . ... </k> -<REG> 1 </REG> - - - -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_R3_32 => . ... </k> -<REG> 2 </REG> +syntax K ::= "NELEM_EIGHTHMEM" +rule <NELEM> _ => 64 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_R3_32 => . ... </k> -<REG> 3 </REG> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_R3_32 => . ... </k> -<REG> 4 </REG> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_R3_32 => . ... </k> -<REG> 5 </REG> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_R3_32 => . ... </k> -<REG> 6 </REG> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_R3_32 => . ... </k> -<REG> 7 </REG> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 2 </VL> -syntax K ::= "XMM_R3_64" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM8 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM9 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM10 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM11 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM12 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM13 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_XMM14 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM15 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM16 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM17 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM18 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_EIGHTHMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM19 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM20 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM21 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM22 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM23 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <k> NELEM_EIGHTHMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_XMM24 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> +syntax K ::= "XMM_R_32" +rule <OUTREG> _ => REG_XMM0 </OUTREG> +<k> XMM_R_32 => . ... </k> <REG> 0 </REG> -rule <OUTREG> _ => REG_XMM25 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> +rule <OUTREG> _ => REG_XMM1 </OUTREG> +<k> XMM_R_32 => . ... </k> <REG> 1 </REG> -rule <OUTREG> _ => REG_XMM26 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> +rule <OUTREG> _ => REG_XMM2 </OUTREG> +<k> XMM_R_32 => . ... </k> <REG> 2 </REG> -rule <OUTREG> _ => REG_XMM27 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> +rule <OUTREG> _ => REG_XMM3 </OUTREG> +<k> XMM_R_32 => . ... </k> <REG> 3 </REG> -rule <OUTREG> _ => REG_XMM28 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> +rule <OUTREG> _ => REG_XMM4 </OUTREG> +<k> XMM_R_32 => . ... </k> <REG> 4 </REG> -rule <OUTREG> _ => REG_XMM29 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> +rule <OUTREG> _ => REG_XMM5 </OUTREG> +<k> XMM_R_32 => . ... </k> <REG> 5 </REG> -rule <OUTREG> _ => REG_XMM30 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> +rule <OUTREG> _ => REG_XMM6 </OUTREG> +<k> XMM_R_32 => . ... </k> <REG> 6 </REG> -rule <OUTREG> _ => REG_XMM31 </OUTREG> -<k> XMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> +rule <OUTREG> _ => REG_XMM7 </OUTREG> +<k> XMM_R_32 => . ... </k> <REG> 7 </REG> -syntax K ::= "YMM_R3" -rule <k> YMM_R3 => YMM_R3_32 ... </k> +syntax K ::= "YMM_B3" +rule <k> YMM_B3 => YMM_B3_32 ... </k> <MODE> 0 </MODE> -rule <k> YMM_R3 => YMM_R3_32 ... </k> +rule <k> YMM_B3 => YMM_B3_32 ... </k> <MODE> 1 </MODE> -rule <k> YMM_R3 => YMM_R3_64 ... </k> +rule <k> YMM_B3 => YMM_B3_64 ... </k> <MODE> 2 </MODE> -syntax K ::= "YMM_R3_32" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_R3_32 => . ... </k> -<REG> 0 </REG> +syntax K ::= "FINAL_SSEG0" +rule <OUTREG> _ => REG_SS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG0 => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_R3_32 => . ... </k> -<REG> 1 </REG> +rule <OUTREG> _ => REG_SS </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG0 => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_R3_32 => . ... </k> -<REG> 2 </REG> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT0> _ => 1 </USINGDEFAULTSEGMENT0> +<k> FINAL_SSEG0 => . ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_R3_32 => . ... </k> -<REG> 3 </REG> +syntax K ::= "XMM_SE" +rule <k> XMM_SE => XMM_SE32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_R3_32 => . ... </k> -<REG> 4 </REG> +rule <k> XMM_SE => XMM_SE32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_R3_32 => . ... </k> -<REG> 5 </REG> +rule <k> XMM_SE => XMM_SE64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_R3_32 => . ... </k> -<REG> 6 </REG> +syntax K ::= "VGPR32_B_64" +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_R3_32 => . ... </k> -<REG> 7 </REG> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 1 </RM> -syntax K ::= "YMM_R3_64" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 0 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_R8D </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 1 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_R9D </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_YMM8 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <OUTREG> _ => REG_R10D </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_YMM9 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_R11D </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 1 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_YMM10 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_R12D </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 1 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_YMM11 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_R13D </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 1 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_YMM12 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_R14D </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 1 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_YMM13 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_R15D </OUTREG> +<k> VGPR32_B_64 => . ... </k> +<REXB> 1 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_YMM14 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 6 </REG> +syntax K ::= "IMMUNE66" +rule <EOSZ> _ => 2 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> IMMUNE66 => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_YMM15 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <EOSZ> _ => 2 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> IMMUNE66 => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_YMM16 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <EOSZ> _ => 2 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> IMMUNE66 => . ... </k> +<MODE> 2 </MODE> +<REXW> 0 </REXW> -rule <OUTREG> _ => REG_YMM17 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <EOSZ> _ => 3 </EOSZ> +<OSZ> _ => 0 </OSZ> +<k> IMMUNE66 => . ... </k> +<MODE> 2 </MODE> +<REXW> 1 </REXW> -rule <OUTREG> _ => REG_YMM18 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 2 </REG> +syntax K ::= "NELEM_HALFMEM" +rule <NELEM> _ => 256 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM19 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <NELEM> _ => 128 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM20 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <NELEM> _ => 64 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM21 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM22 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM23 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM24 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 0 </REG> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM25 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM26 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM27 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <k> NELEM_HALFMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 2 </VL> -rule <OUTREG> _ => REG_YMM28 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <NELEM> _ => 128 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM29 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <NELEM> _ => 64 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM30 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_YMM31 </OUTREG> -<k> YMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 1 </VL> -syntax K ::= "ZMM_R3" -rule <k> ZMM_R3 => ZMM_R3_32 ... </k> -<MODE> 0 </MODE> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 1 </VL> -rule <k> ZMM_R3 => ZMM_R3_32 ... </k> -<MODE> 1 </MODE> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 1 </VL> -rule <k> ZMM_R3 => ZMM_R3_64 ... </k> -<MODE> 2 </MODE> +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 1 </VL> -syntax K ::= "ZMM_R3_32" -rule <OUTREG> _ => REG_ZMM0 </OUTREG> -<k> ZMM_R3_32 => . ... </k> -<REG> 0 </REG> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_ZMM1 </OUTREG> -<k> ZMM_R3_32 => . ... </k> -<REG> 1 </REG> +rule <k> NELEM_HALFMEM => DecoderError ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_ZMM2 </OUTREG> -<k> ZMM_R3_32 => . ... </k> -<REG> 2 </REG> +rule <k> NELEM_HALFMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 1 </VL> -rule <OUTREG> _ => REG_ZMM3 </OUTREG> -<k> ZMM_R3_32 => . ... </k> -<REG> 3 </REG> +rule <NELEM> _ => 64 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 1 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_ZMM4 </OUTREG> -<k> ZMM_R3_32 => . ... </k> -<REG> 4 </REG> +rule <NELEM> _ => 32 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 2 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_ZMM5 </OUTREG> -<k> ZMM_R3_32 => . ... </k> -<REG> 5 </REG> +rule <NELEM> _ => 16 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 4 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_ZMM6 </OUTREG> -<k> ZMM_R3_32 => . ... </k> -<REG> 6 </REG> +rule <NELEM> _ => 8 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 8 </ELEMENTSIZE> +<VL> 0 </VL> -rule <OUTREG> _ => REG_ZMM7 </OUTREG> -<k> ZMM_R3_32 => . ... </k> -<REG> 7 </REG> +rule <NELEM> _ => 4 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 16 </ELEMENTSIZE> +<VL> 0 </VL> -syntax K ::= "ZMM_R3_64" +rule <NELEM> _ => 2 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 32 </ELEMENTSIZE> +<VL> 0 </VL> + + + +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_HALFMEM => . ... </k> +<ELEMENTSIZE> 64 </ELEMENTSIZE> +<VL> 0 </VL> + + + +rule <k> NELEM_HALFMEM => DecoderError ... </k> +<ELEMENTSIZE> 128 </ELEMENTSIZE> +<VL> 0 </VL> + + + +rule <k> NELEM_HALFMEM => DecoderError ... </k> +<ELEMENTSIZE> 256 </ELEMENTSIZE> +<VL> 0 </VL> + + + +rule <k> NELEM_HALFMEM => DecoderError ... </k> +<ELEMENTSIZE> 512 </ELEMENTSIZE> +<VL> 0 </VL> + + + +syntax K ::= "ZMM_N3_32" rule <OUTREG> _ => REG_ZMM0 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 0 </REG> +<k> ZMM_N3_32 => . ... </k> +<VEXDEST210> 7 </VEXDEST210> rule <OUTREG> _ => REG_ZMM1 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 1 </REG> +<k> ZMM_N3_32 => . ... </k> +<VEXDEST210> 6 </VEXDEST210> rule <OUTREG> _ => REG_ZMM2 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 2 </REG> +<k> ZMM_N3_32 => . ... </k> +<VEXDEST210> 5 </VEXDEST210> rule <OUTREG> _ => REG_ZMM3 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 3 </REG> +<k> ZMM_N3_32 => . ... </k> +<VEXDEST210> 4 </VEXDEST210> rule <OUTREG> _ => REG_ZMM4 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 4 </REG> +<k> ZMM_N3_32 => . ... </k> +<VEXDEST210> 3 </VEXDEST210> rule <OUTREG> _ => REG_ZMM5 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 5 </REG> +<k> ZMM_N3_32 => . ... </k> +<VEXDEST210> 2 </VEXDEST210> rule <OUTREG> _ => REG_ZMM6 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 6 </REG> +<k> ZMM_N3_32 => . ... </k> +<VEXDEST210> 1 </VEXDEST210> rule <OUTREG> _ => REG_ZMM7 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 0 </REXR> -<REG> 7 </REG> +<k> ZMM_N3_32 => . ... </k> +<VEXDEST210> 0 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM8 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 0 </REG> +syntax K ::= "VGPR64_N" +rule <OUTREG> _ => REG_RAX </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM9 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_RCX </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM10 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_RDX </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM11 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_RBX </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM12 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_RSP </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM13 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_RBP </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM14 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_RSI </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM15 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 0 </REXRR> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_RDI </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 1 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM16 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 0 </REG> +rule <OUTREG> _ => REG_R8 </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 7 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM17 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 1 </REG> +rule <OUTREG> _ => REG_R9 </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 6 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM18 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 2 </REG> +rule <OUTREG> _ => REG_R10 </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 5 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM19 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 3 </REG> +rule <OUTREG> _ => REG_R11 </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM20 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 4 </REG> +rule <OUTREG> _ => REG_R12 </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 3 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM21 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 5 </REG> +rule <OUTREG> _ => REG_R13 </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 2 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM22 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 6 </REG> +rule <OUTREG> _ => REG_R14 </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 1 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM23 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 0 </REXR> -<REG> 7 </REG> +rule <OUTREG> _ => REG_R15 </OUTREG> +<k> VGPR64_N => . ... </k> +<VEXDEST3> 0 </VEXDEST3> +<VEXDEST210> 0 </VEXDEST210> -rule <OUTREG> _ => REG_ZMM24 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 0 </REG> - - - -rule <OUTREG> _ => REG_ZMM25 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 1 </REG> - - - -rule <OUTREG> _ => REG_ZMM26 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 2 </REG> - - - -rule <OUTREG> _ => REG_ZMM27 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 3 </REG> - - - -rule <OUTREG> _ => REG_ZMM28 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 4 </REG> - - - -rule <OUTREG> _ => REG_ZMM29 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 5 </REG> +syntax K ::= "OVERRIDE_SEG1" +rule <k> OVERRIDE_SEG1 => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_ZMM30 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 6 </REG> +rule <k> OVERRIDE_SEG1 => . ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_ZMM31 </OUTREG> -<k> ZMM_R3_64 => . ... </k> -<REXRR> 1 </REXRR> -<REXR> 1 </REXR> -<REG> 7 </REG> +rule <k> OVERRIDE_SEG1 => . ... </k> +<MODE> 2 </MODE> -syntax K ::= "XMM_B3" -rule <k> XMM_B3 => XMM_B3_32 ... </k> -<MODE> 0 </MODE> +syntax K ::= "VGPR32_N_32" +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> VGPR32_N_32 => . ... </k> +<VEXDEST210> 7 </VEXDEST210> -rule <k> XMM_B3 => XMM_B3_32 ... </k> -<MODE> 1 </MODE> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> VGPR32_N_32 => . ... </k> +<VEXDEST210> 6 </VEXDEST210> -rule <k> XMM_B3 => XMM_B3_64 ... </k> -<MODE> 2 </MODE> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> VGPR32_N_32 => . ... </k> +<VEXDEST210> 5 </VEXDEST210> -syntax K ::= "XMM_B3_32" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_B3_32 => . ... </k> -<RM> 0 </RM> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> VGPR32_N_32 => . ... </k> +<VEXDEST210> 4 </VEXDEST210> -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_B3_32 => . ... </k> -<RM> 1 </RM> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> VGPR32_N_32 => . ... </k> +<VEXDEST210> 3 </VEXDEST210> -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_B3_32 => . ... </k> -<RM> 2 </RM> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> VGPR32_N_32 => . ... </k> +<VEXDEST210> 2 </VEXDEST210> -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_B3_32 => . ... </k> -<RM> 3 </RM> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> VGPR32_N_32 => . ... </k> +<VEXDEST210> 1 </VEXDEST210> -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_B3_32 => . ... </k> -<RM> 4 </RM> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> VGPR32_N_32 => . ... </k> +<VEXDEST210> 0 </VEXDEST210> -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_B3_32 => . ... </k> -<RM> 5 </RM> +syntax K ::= "FINAL_DSEG1" +rule <k> FINAL_DSEG1 => FINAL_DSEG1_NOT64 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_B3_32 => . ... </k> -<RM> 6 </RM> +rule <k> FINAL_DSEG1 => FINAL_DSEG1_NOT64 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_B3_32 => . ... </k> -<RM> 7 </RM> +rule <k> FINAL_DSEG1 => FINAL_DSEG1_MODE64 ... </k> +<MODE> 2 </MODE> -syntax K ::= "XMM_B3_64" +syntax K ::= "XMM_R_64" rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 0 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 1 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 2 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 3 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 4 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 5 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 6 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 7 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> rule <OUTREG> _ => REG_XMM8 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 0 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> rule <OUTREG> _ => REG_XMM9 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 1 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> rule <OUTREG> _ => REG_XMM10 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 2 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> rule <OUTREG> _ => REG_XMM11 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 3 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> rule <OUTREG> _ => REG_XMM12 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 4 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> rule <OUTREG> _ => REG_XMM13 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 5 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> rule <OUTREG> _ => REG_XMM14 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 6 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> rule <OUTREG> _ => REG_XMM15 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 7 </RM> - - - -rule <OUTREG> _ => REG_XMM16 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 0 </REXB> -<RM> 0 </RM> - - - -rule <OUTREG> _ => REG_XMM17 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 0 </REXB> -<RM> 1 </RM> - - - -rule <OUTREG> _ => REG_XMM18 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 0 </REXB> -<RM> 2 </RM> - - - -rule <OUTREG> _ => REG_XMM19 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 0 </REXB> -<RM> 3 </RM> - - - -rule <OUTREG> _ => REG_XMM20 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 0 </REXB> -<RM> 4 </RM> - - - -rule <OUTREG> _ => REG_XMM21 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 0 </REXB> -<RM> 5 </RM> - - - -rule <OUTREG> _ => REG_XMM22 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 0 </REXB> -<RM> 6 </RM> - - - -rule <OUTREG> _ => REG_XMM23 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 0 </REXB> -<RM> 7 </RM> - - - -rule <OUTREG> _ => REG_XMM24 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 1 </REXB> -<RM> 0 </RM> - - - -rule <OUTREG> _ => REG_XMM25 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 1 </REXB> -<RM> 1 </RM> - - - -rule <OUTREG> _ => REG_XMM26 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 1 </REXB> -<RM> 2 </RM> - - - -rule <OUTREG> _ => REG_XMM27 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 1 </REXB> -<RM> 3 </RM> - - - -rule <OUTREG> _ => REG_XMM28 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 1 </REXB> -<RM> 4 </RM> - - - -rule <OUTREG> _ => REG_XMM29 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 1 </REXB> -<RM> 5 </RM> - - - -rule <OUTREG> _ => REG_XMM30 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 1 </REXB> -<RM> 6 </RM> - - - -rule <OUTREG> _ => REG_XMM31 </OUTREG> -<k> XMM_B3_64 => . ... </k> -<REXX> 1 </REXX> -<REXB> 1 </REXB> -<RM> 7 </RM> +<k> XMM_R_64 => . ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> -syntax K ::= "YMM_B3" -rule <k> YMM_B3 => YMM_B3_32 ... </k> +syntax K ::= "YMM_R" +rule <k> YMM_R => YMM_R_32 ... </k> <MODE> 0 </MODE> -rule <k> YMM_B3 => YMM_B3_32 ... </k> +rule <k> YMM_R => YMM_R_32 ... </k> <MODE> 1 </MODE> -rule <k> YMM_B3 => YMM_B3_64 ... </k> +rule <k> YMM_R => YMM_R_64 ... </k> <MODE> 2 </MODE> -syntax K ::= "YMM_B3_32" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_B3_32 => . ... </k> -<RM> 0 </RM> - - - -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_B3_32 => . ... </k> -<RM> 1 </RM> - - - -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_B3_32 => . ... </k> -<RM> 2 </RM> - - - -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_B3_32 => . ... </k> -<RM> 3 </RM> - - - -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_B3_32 => . ... </k> -<RM> 4 </RM> - - - -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_B3_32 => . ... </k> -<RM> 5 </RM> - - - -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_B3_32 => . ... </k> -<RM> 6 </RM> - - - -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_B3_32 => . ... </k> -<RM> 7 </RM> +syntax K ::= "UIMM16" +rule <IMMWIDTH> _ => 16 </IMMWIDTH> +<k> UIMM16 => . ... </k> -syntax K ::= "YMM_B3_64" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +syntax K ::= "CR_B" +rule <OUTREG> _ => REG_CR0 </OUTREG> +<k> CR_B => . ... </k> <REXB> 0 </REXB> <RM> 0 </RM> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> CR_B => . ... </k> <REXB> 0 </REXB> <RM> 1 </RM> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_CR2 </OUTREG> +<k> CR_B => . ... </k> <REXB> 0 </REXB> <RM> 2 </RM> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_CR3 </OUTREG> +<k> CR_B => . ... </k> <REXB> 0 </REXB> <RM> 3 </RM> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_CR4 </OUTREG> +<k> CR_B => . ... </k> <REXB> 0 </REXB> <RM> 4 </RM> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 0 </REXB> <RM> 5 </RM> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 0 </REXB> <RM> 6 </RM> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 0 </REXB> <RM> 7 </RM> -rule <OUTREG> _ => REG_YMM8 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_CR8 </OUTREG> +<k> CR_B => . ... </k> <REXB> 1 </REXB> <RM> 0 </RM> -rule <OUTREG> _ => REG_YMM9 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 1 </REXB> <RM> 1 </RM> -rule <OUTREG> _ => REG_YMM10 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 1 </REXB> <RM> 2 </RM> -rule <OUTREG> _ => REG_YMM11 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 1 </REXB> <RM> 3 </RM> -rule <OUTREG> _ => REG_YMM12 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 1 </REXB> <RM> 4 </RM> -rule <OUTREG> _ => REG_YMM13 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 1 </REXB> <RM> 5 </RM> -rule <OUTREG> _ => REG_YMM14 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 1 </REXB> <RM> 6 </RM> -rule <OUTREG> _ => REG_YMM15 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 0 </REXX> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> CR_B => . ... </k> <REXB> 1 </REXB> <RM> 7 </RM> -rule <OUTREG> _ => REG_YMM16 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +syntax K ::= "GPR32_SB" +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 0 </REXB> -<RM> 0 </RM> +<SRM> 0 </SRM> -rule <OUTREG> _ => REG_YMM17 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 0 </REXB> -<RM> 1 </RM> +<SRM> 1 </SRM> -rule <OUTREG> _ => REG_YMM18 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 0 </REXB> -<RM> 2 </RM> +<SRM> 2 </SRM> -rule <OUTREG> _ => REG_YMM19 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 0 </REXB> -<RM> 3 </RM> +<SRM> 3 </SRM> -rule <OUTREG> _ => REG_YMM20 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 0 </REXB> -<RM> 4 </RM> +<SRM> 4 </SRM> -rule <OUTREG> _ => REG_YMM21 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 0 </REXB> -<RM> 5 </RM> +<SRM> 5 </SRM> -rule <OUTREG> _ => REG_YMM22 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 0 </REXB> -<RM> 6 </RM> +<SRM> 6 </SRM> -rule <OUTREG> _ => REG_YMM23 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 0 </REXB> -<RM> 7 </RM> +<SRM> 7 </SRM> -rule <OUTREG> _ => REG_YMM24 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_R8D </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 1 </REXB> -<RM> 0 </RM> +<SRM> 0 </SRM> -rule <OUTREG> _ => REG_YMM25 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_R9D </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 1 </REXB> -<RM> 1 </RM> +<SRM> 1 </SRM> -rule <OUTREG> _ => REG_YMM26 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_R10D </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 1 </REXB> -<RM> 2 </RM> +<SRM> 2 </SRM> -rule <OUTREG> _ => REG_YMM27 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_R11D </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 1 </REXB> -<RM> 3 </RM> +<SRM> 3 </SRM> -rule <OUTREG> _ => REG_YMM28 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_R12D </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 1 </REXB> -<RM> 4 </RM> +<SRM> 4 </SRM> -rule <OUTREG> _ => REG_YMM29 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_R13D </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 1 </REXB> -<RM> 5 </RM> +<SRM> 5 </SRM> -rule <OUTREG> _ => REG_YMM30 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_R14D </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 1 </REXB> -<RM> 6 </RM> +<SRM> 6 </SRM> -rule <OUTREG> _ => REG_YMM31 </OUTREG> -<k> YMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_R15D </OUTREG> +<k> GPR32_SB => . ... </k> <REXB> 1 </REXB> -<RM> 7 </RM> - - - -syntax K ::= "ZMM_B3" -rule <k> ZMM_B3 => ZMM_B3_32 ... </k> -<MODE> 0 </MODE> - - - -rule <k> ZMM_B3 => ZMM_B3_32 ... </k> -<MODE> 1 </MODE> - - - -rule <k> ZMM_B3 => ZMM_B3_64 ... </k> -<MODE> 2 </MODE> - - - -syntax K ::= "ZMM_B3_32" -rule <OUTREG> _ => REG_ZMM0 </OUTREG> -<k> ZMM_B3_32 => . ... </k> -<RM> 0 </RM> - - - -rule <OUTREG> _ => REG_ZMM1 </OUTREG> -<k> ZMM_B3_32 => . ... </k> -<RM> 1 </RM> - - - -rule <OUTREG> _ => REG_ZMM2 </OUTREG> -<k> ZMM_B3_32 => . ... </k> -<RM> 2 </RM> +<SRM> 7 </SRM> -rule <OUTREG> _ => REG_ZMM3 </OUTREG> -<k> ZMM_B3_32 => . ... </k> -<RM> 3 </RM> +syntax K ::= "Ar9" +rule <OUTREG> _ => REG_R9W </OUTREG> +<k> Ar9 => . ... </k> +<EASZ> 1 </EASZ> -rule <OUTREG> _ => REG_ZMM4 </OUTREG> -<k> ZMM_B3_32 => . ... </k> -<RM> 4 </RM> +rule <OUTREG> _ => REG_R9D </OUTREG> +<k> Ar9 => . ... </k> +<EASZ> 2 </EASZ> -rule <OUTREG> _ => REG_ZMM5 </OUTREG> -<k> ZMM_B3_32 => . ... </k> -<RM> 5 </RM> +rule <OUTREG> _ => REG_R9 </OUTREG> +<k> Ar9 => . ... </k> +<EASZ> 3 </EASZ> -rule <OUTREG> _ => REG_ZMM6 </OUTREG> -<k> ZMM_B3_32 => . ... </k> -<RM> 6 </RM> +syntax K ::= "FINAL_SSEG1" +rule <OUTREG> _ => REG_SS </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_SSEG1 => . ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_ZMM7 </OUTREG> -<k> ZMM_B3_32 => . ... </k> -<RM> 7 </RM> +rule <OUTREG> _ => REG_SS </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_SSEG1 => . ... </k> +<MODE> 1 </MODE> -syntax K ::= "ZMM_B3_64" -rule <OUTREG> _ => REG_ZMM0 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 0 </RM> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<USINGDEFAULTSEGMENT1> _ => 1 </USINGDEFAULTSEGMENT1> +<k> FINAL_SSEG1 => . ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_ZMM1 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 1 </RM> +syntax K ::= "VSIB_YMM" +rule <SCALE> _ => 1 </SCALE> +<k> VSIB_YMM => VSIB_BASE ~> VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 0 </SIBSCALE> -rule <OUTREG> _ => REG_ZMM2 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 2 </RM> +rule <SCALE> _ => 2 </SCALE> +<k> VSIB_YMM => VSIB_BASE ~> VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 1 </SIBSCALE> -rule <OUTREG> _ => REG_ZMM3 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 3 </RM> +rule <SCALE> _ => 4 </SCALE> +<k> VSIB_YMM => VSIB_BASE ~> VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 2 </SIBSCALE> -rule <OUTREG> _ => REG_ZMM4 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 4 </RM> +rule <SCALE> _ => 8 </SCALE> +<k> VSIB_YMM => VSIB_BASE ~> VSIB_INDEX_YMM ~> OUTREGToINDEX ... </k> +<SIBSCALE> 3 </SIBSCALE> -rule <OUTREG> _ => REG_ZMM5 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 5 </RM> +syntax K ::= "VGPR32_R_32" +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> VGPR32_R_32 => . ... </k> +<REG> 0 </REG> -rule <OUTREG> _ => REG_ZMM6 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 6 </RM> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> VGPR32_R_32 => . ... </k> +<REG> 1 </REG> -rule <OUTREG> _ => REG_ZMM7 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 0 </REXB> -<RM> 7 </RM> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> VGPR32_R_32 => . ... </k> +<REG> 2 </REG> -rule <OUTREG> _ => REG_ZMM8 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 0 </RM> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> VGPR32_R_32 => . ... </k> +<REG> 3 </REG> -rule <OUTREG> _ => REG_ZMM9 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 1 </RM> +rule <OUTREG> _ => REG_ESP </OUTREG> +<k> VGPR32_R_32 => . ... </k> +<REG> 4 </REG> -rule <OUTREG> _ => REG_ZMM10 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 2 </RM> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> VGPR32_R_32 => . ... </k> +<REG> 5 </REG> -rule <OUTREG> _ => REG_ZMM11 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 3 </RM> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> VGPR32_R_32 => . ... </k> +<REG> 6 </REG> -rule <OUTREG> _ => REG_ZMM12 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 4 </RM> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> VGPR32_R_32 => . ... </k> +<REG> 7 </REG> -rule <OUTREG> _ => REG_ZMM13 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 5 </RM> +syntax K ::= "YMM_B" +rule <k> YMM_B => YMM_B_32 ... </k> +<MODE> 0 </MODE> -rule <OUTREG> _ => REG_ZMM14 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 6 </RM> +rule <k> YMM_B => YMM_B_32 ... </k> +<MODE> 1 </MODE> -rule <OUTREG> _ => REG_ZMM15 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 0 </REXX> -<REXB> 1 </REXB> -<RM> 7 </RM> +rule <k> YMM_B => YMM_B_64 ... </k> +<MODE> 2 </MODE> -rule <OUTREG> _ => REG_ZMM16 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +syntax K ::= "YMM_B_64" +rule <OUTREG> _ => REG_YMM0 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 0 </REXB> <RM> 0 </RM> -rule <OUTREG> _ => REG_ZMM17 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM1 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 0 </REXB> <RM> 1 </RM> -rule <OUTREG> _ => REG_ZMM18 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM2 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 0 </REXB> <RM> 2 </RM> -rule <OUTREG> _ => REG_ZMM19 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM3 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 0 </REXB> <RM> 3 </RM> -rule <OUTREG> _ => REG_ZMM20 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM4 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 0 </REXB> <RM> 4 </RM> -rule <OUTREG> _ => REG_ZMM21 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM5 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 0 </REXB> <RM> 5 </RM> -rule <OUTREG> _ => REG_ZMM22 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM6 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 0 </REXB> <RM> 6 </RM> -rule <OUTREG> _ => REG_ZMM23 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM7 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 0 </REXB> <RM> 7 </RM> -rule <OUTREG> _ => REG_ZMM24 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM8 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 1 </REXB> <RM> 0 </RM> -rule <OUTREG> _ => REG_ZMM25 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM9 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 1 </REXB> <RM> 1 </RM> -rule <OUTREG> _ => REG_ZMM26 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM10 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 1 </REXB> <RM> 2 </RM> -rule <OUTREG> _ => REG_ZMM27 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM11 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 1 </REXB> <RM> 3 </RM> -rule <OUTREG> _ => REG_ZMM28 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM12 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 1 </REXB> <RM> 4 </RM> -rule <OUTREG> _ => REG_ZMM29 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM13 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 1 </REXB> <RM> 5 </RM> -rule <OUTREG> _ => REG_ZMM30 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM14 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 1 </REXB> <RM> 6 </RM> -rule <OUTREG> _ => REG_ZMM31 </OUTREG> -<k> ZMM_B3_64 => . ... </k> -<REXX> 1 </REXX> +rule <OUTREG> _ => REG_YMM15 </OUTREG> +<k> YMM_B_64 => . ... </k> <REXB> 1 </REXB> <RM> 7 </RM> -syntax K ::= "XMM_N3" -rule <k> XMM_N3 => XMM_N3_32 ... </k> -<MODE> 0 </MODE> - - - -rule <k> XMM_N3 => XMM_N3_32 ... </k> -<MODE> 1 </MODE> - - - -rule <k> XMM_N3 => XMM_N3_64 ... </k> -<MODE> 2 </MODE> - - - -syntax K ::= "XMM_N3_32" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_N3_32 => . ... </k> -<VEXDEST210> 7 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_N3_32 => . ... </k> -<VEXDEST210> 6 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_N3_32 => . ... </k> -<VEXDEST210> 5 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_N3_32 => . ... </k> -<VEXDEST210> 4 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_N3_32 => . ... </k> -<VEXDEST210> 3 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_N3_32 => . ... </k> -<VEXDEST210> 2 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_N3_32 => . ... </k> -<VEXDEST210> 1 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_N3_32 => . ... </k> -<VEXDEST210> 0 </VEXDEST210> - - - -syntax K ::= "XMM_N3_64" -rule <OUTREG> _ => REG_XMM0 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM1 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM2 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM3 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM4 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM5 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM6 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM7 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM8 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM9 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM10 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM11 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM12 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM13 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM14 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM15 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM16 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM17 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM18 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM19 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM20 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM21 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM22 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> - - - -rule <OUTREG> _ => REG_XMM23 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +syntax K ::= "SIB_BASE0" +rule <k> SIB_BASE0 => ArAX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 0 </SIBBASE> -rule <OUTREG> _ => REG_XMM24 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <k> SIB_BASE0 => Ar8 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 0 </SIBBASE> -rule <OUTREG> _ => REG_XMM25 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <k> SIB_BASE0 => ArCX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 1 </SIBBASE> -rule <OUTREG> _ => REG_XMM26 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <k> SIB_BASE0 => Ar9 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 1 </SIBBASE> -rule <OUTREG> _ => REG_XMM27 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <k> SIB_BASE0 => ArDX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 2 </SIBBASE> -rule <OUTREG> _ => REG_XMM28 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <k> SIB_BASE0 => Ar10 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 2 </SIBBASE> -rule <OUTREG> _ => REG_XMM29 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <k> SIB_BASE0 => ArBX ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 3 </SIBBASE> -rule <OUTREG> _ => REG_XMM30 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <k> SIB_BASE0 => Ar11 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 3 </SIBBASE> -rule <OUTREG> _ => REG_XMM31 </OUTREG> -<k> XMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <k> SIB_BASE0 => ArSP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 4 </SIBBASE> -syntax K ::= "YMM_N3" -rule <k> YMM_N3 => YMM_N3_32 ... </k> -<MODE> 0 </MODE> +rule <k> SIB_BASE0 => Ar12 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 4 </SIBBASE> -rule <k> YMM_N3 => YMM_N3_32 ... </k> -<MODE> 1 </MODE> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<BASE0> _ => REG_INVALID </BASE0> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> SIB_BASE0 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 0 </MOD> -rule <k> YMM_N3 => YMM_N3_64 ... </k> -<MODE> 2 </MODE> +rule <DISPWIDTH> _ => 8 </DISPWIDTH> +<k> SIB_BASE0 => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 1 </MOD> -syntax K ::= "YMM_N3_32" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_N3_32 => . ... </k> -<VEXDEST210> 7 </VEXDEST210> +rule <DISPWIDTH> _ => 32 </DISPWIDTH> +<k> SIB_BASE0 => ArBP ~> OUTREGToBASE0 ~> FINAL_SSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 2 </MOD> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_N3_32 => . ... </k> -<VEXDEST210> 6 </VEXDEST210> +rule <NEEDMEMDISP> _ => 32 </NEEDMEMDISP> +<BASE0> _ => REG_INVALID </BASE0> +<k> SIB_BASE0 => FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 0 </MOD> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_N3_32 => . ... </k> -<VEXDEST210> 5 </VEXDEST210> +rule <DISPWIDTH> _ => 8 </DISPWIDTH> +<k> SIB_BASE0 => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 1 </MOD> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_N3_32 => . ... </k> -<VEXDEST210> 4 </VEXDEST210> +rule <DISPWIDTH> _ => 32 </DISPWIDTH> +<k> SIB_BASE0 => Ar13 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 5 </SIBBASE> +<MOD> 2 </MOD> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_N3_32 => . ... </k> -<VEXDEST210> 3 </VEXDEST210> +rule <k> SIB_BASE0 => ArSI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 6 </SIBBASE> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_N3_32 => . ... </k> -<VEXDEST210> 2 </VEXDEST210> +rule <k> SIB_BASE0 => Ar14 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 6 </SIBBASE> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_N3_32 => . ... </k> -<VEXDEST210> 1 </VEXDEST210> +rule <k> SIB_BASE0 => ArDI ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 0 </REXB> +<SIBBASE> 7 </SIBBASE> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_N3_32 => . ... </k> -<VEXDEST210> 0 </VEXDEST210> +rule <k> SIB_BASE0 => Ar15 ~> OUTREGToBASE0 ~> FINAL_DSEG ~> OUTREGToSEG0 ... </k> +<REXB> 1 </REXB> +<SIBBASE> 7 </SIBBASE> -syntax K ::= "YMM_N3_64" -rule <OUTREG> _ => REG_YMM0 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +syntax K ::= "GPR8_B" +rule <OUTREG> _ => REG_AL </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_YMM1 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_CL </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_YMM2 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_DL </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_YMM3 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_BL </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_YMM4 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_AH </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 4 </RM> +<REX> 0 </REX> -rule <OUTREG> _ => REG_YMM5 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_CH </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 5 </RM> +<REX> 0 </REX> -rule <OUTREG> _ => REG_YMM6 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_DH </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 6 </RM> +<REX> 0 </REX> -rule <OUTREG> _ => REG_YMM7 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_BH </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 7 </RM> +<REX> 0 </REX> -rule <OUTREG> _ => REG_YMM8 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_SPL </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 4 </RM> +<REX> 1 </REX> -rule <OUTREG> _ => REG_YMM9 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_BPL </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 5 </RM> +<REX> 1 </REX> -rule <OUTREG> _ => REG_YMM10 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_SIL </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 6 </RM> +<REX> 1 </REX> -rule <OUTREG> _ => REG_YMM11 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_DIL </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 0 </REXB> +<RM> 7 </RM> +<REX> 1 </REX> -rule <OUTREG> _ => REG_YMM12 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_R8B </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 1 </REXB> +<RM> 0 </RM> -rule <OUTREG> _ => REG_YMM13 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_R9B </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 1 </REXB> +<RM> 1 </RM> -rule <OUTREG> _ => REG_YMM14 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_R10B </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 1 </REXB> +<RM> 2 </RM> -rule <OUTREG> _ => REG_YMM15 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_R11B </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 1 </REXB> +<RM> 3 </RM> -rule <OUTREG> _ => REG_YMM16 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_R12B </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 1 </REXB> +<RM> 4 </RM> -rule <OUTREG> _ => REG_YMM17 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_R13B </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 1 </REXB> +<RM> 5 </RM> -rule <OUTREG> _ => REG_YMM18 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_R14B </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 1 </REXB> +<RM> 6 </RM> -rule <OUTREG> _ => REG_YMM19 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_R15B </OUTREG> +<k> GPR8_B => . ... </k> +<REXB> 1 </REXB> +<RM> 7 </RM> -rule <OUTREG> _ => REG_YMM20 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +syntax K ::= "MASK1" +rule <OUTREG> _ => REG_K0 </OUTREG> +<k> MASK1 => . ... </k> +<MASK> 0 </MASK> -rule <OUTREG> _ => REG_YMM21 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_K1 </OUTREG> +<k> MASK1 => . ... </k> +<MASK> 1 </MASK> -rule <OUTREG> _ => REG_YMM22 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_K2 </OUTREG> +<k> MASK1 => . ... </k> +<MASK> 2 </MASK> -rule <OUTREG> _ => REG_YMM23 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_K3 </OUTREG> +<k> MASK1 => . ... </k> +<MASK> 3 </MASK> -rule <OUTREG> _ => REG_YMM24 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_K4 </OUTREG> +<k> MASK1 => . ... </k> +<MASK> 4 </MASK> -rule <OUTREG> _ => REG_YMM25 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_K5 </OUTREG> +<k> MASK1 => . ... </k> +<MASK> 5 </MASK> -rule <OUTREG> _ => REG_YMM26 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_K6 </OUTREG> +<k> MASK1 => . ... </k> +<MASK> 6 </MASK> -rule <OUTREG> _ => REG_YMM27 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_K7 </OUTREG> +<k> MASK1 => . ... </k> +<MASK> 7 </MASK> -rule <OUTREG> _ => REG_YMM28 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +syntax K ::= "GPRy_R" +rule <k> GPRy_R => GPR64_R ... </k> +<EOSZ> 3 </EOSZ> -rule <OUTREG> _ => REG_YMM29 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <k> GPRy_R => GPR32_R ... </k> +<EOSZ> 2 </EOSZ> -rule <OUTREG> _ => REG_YMM30 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <k> GPRy_R => GPR32_R ... </k> +<EOSZ> 1 </EOSZ> -rule <OUTREG> _ => REG_YMM31 </OUTREG> -<k> YMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +syntax K ::= "NELEM_GPR_WRITER_LDOP_Q" +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_LDOP_Q => . ... </k> +<VL> 0 </VL> -syntax K ::= "ZMM_N3" -rule <k> ZMM_N3 => ZMM_N3_32 ... </k> -<MODE> 0 </MODE> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_LDOP_Q => . ... </k> +<VL> 1 </VL> -rule <k> ZMM_N3 => ZMM_N3_32 ... </k> -<MODE> 1 </MODE> +rule <NELEM> _ => 1 </NELEM> +<k> NELEM_GPR_WRITER_LDOP_Q => . ... </k> +<VL> 2 </VL> -rule <k> ZMM_N3 => ZMM_N3_64 ... </k> -<MODE> 2 </MODE> +syntax K ::= "GPR32_X" +rule <OUTREG> _ => REG_EAX </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 0 </SIBINDEX> -syntax K ::= "ZMM_N3_32" -rule <OUTREG> _ => REG_ZMM0 </OUTREG> -<k> ZMM_N3_32 => . ... </k> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_ECX </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM1 </OUTREG> -<k> ZMM_N3_32 => . ... </k> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_EDX </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM2 </OUTREG> -<k> ZMM_N3_32 => . ... </k> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_EBX </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM3 </OUTREG> -<k> ZMM_N3_32 => . ... </k> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_INVALID </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM4 </OUTREG> -<k> ZMM_N3_32 => . ... </k> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_EBP </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM5 </OUTREG> -<k> ZMM_N3_32 => . ... </k> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_ESI </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM6 </OUTREG> -<k> ZMM_N3_32 => . ... </k> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_EDI </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 0 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM7 </OUTREG> -<k> ZMM_N3_32 => . ... </k> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_R8D </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 0 </SIBINDEX> -syntax K ::= "ZMM_N3_64" -rule <OUTREG> _ => REG_ZMM0 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_R9D </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 1 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM1 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_R10D </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 2 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM2 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_R11D </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 3 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM3 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_R12D </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 4 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM4 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_R13D </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 5 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM5 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_R14D </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 6 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM6 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_R15D </OUTREG> +<k> GPR32_X => . ... </k> +<REXX> 1 </REXX> +<SIBINDEX> 7 </SIBINDEX> -rule <OUTREG> _ => REG_ZMM7 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +syntax K ::= "ESIZE_1_BITS" +rule <ELEMENTSIZE> _ => 1 </ELEMENTSIZE> +<k> ESIZE_1_BITS => . ... </k> +<REX> 0 </REX> -rule <OUTREG> _ => REG_ZMM8 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +syntax K ::= "SEG" +rule <OUTREG> _ => REG_ES </OUTREG> +<k> SEG => . ... </k> +<REG> 0 </REG> -rule <OUTREG> _ => REG_ZMM9 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_CS </OUTREG> +<k> SEG => . ... </k> +<REG> 1 </REG> -rule <OUTREG> _ => REG_ZMM10 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_SS </OUTREG> +<k> SEG => . ... </k> +<REG> 2 </REG> -rule <OUTREG> _ => REG_ZMM11 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_DS </OUTREG> +<k> SEG => . ... </k> +<REG> 3 </REG> -rule <OUTREG> _ => REG_ZMM12 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_FS </OUTREG> +<k> SEG => . ... </k> +<REG> 4 </REG> -rule <OUTREG> _ => REG_ZMM13 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_GS </OUTREG> +<k> SEG => . ... </k> +<REG> 5 </REG> -rule <OUTREG> _ => REG_ZMM14 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<ENCODERPREFERRED> _ => 1 </ENCODERPREFERRED> +<k> SEG => . ... </k> +<REG> 6 </REG> -rule <OUTREG> _ => REG_ZMM15 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 0 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_ERROR </OUTREG> +<k> SEG => . ... </k> +<REG> 7 </REG> -rule <OUTREG> _ => REG_ZMM16 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +syntax K ::= "GPR16_R" +rule <OUTREG> _ => REG_AX </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 0 </REXR> +<REG> 0 </REG> -rule <OUTREG> _ => REG_ZMM17 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_CX </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 0 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_ZMM18 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_DX </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 0 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_ZMM19 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_BX </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 0 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_ZMM20 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_SP </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 0 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_ZMM21 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_BP </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 0 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_ZMM22 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_SI </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 0 </REXR> +<REG> 6 </REG> -rule <OUTREG> _ => REG_ZMM23 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 1 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_DI </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 0 </REXR> +<REG> 7 </REG> -rule <OUTREG> _ => REG_ZMM24 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 7 </VEXDEST210> +rule <OUTREG> _ => REG_R8W </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 1 </REXR> +<REG> 0 </REG> -rule <OUTREG> _ => REG_ZMM25 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 6 </VEXDEST210> +rule <OUTREG> _ => REG_R9W </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 1 </REXR> +<REG> 1 </REG> -rule <OUTREG> _ => REG_ZMM26 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 5 </VEXDEST210> +rule <OUTREG> _ => REG_R10W </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 1 </REXR> +<REG> 2 </REG> -rule <OUTREG> _ => REG_ZMM27 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 4 </VEXDEST210> +rule <OUTREG> _ => REG_R11W </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 1 </REXR> +<REG> 3 </REG> -rule <OUTREG> _ => REG_ZMM28 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 3 </VEXDEST210> +rule <OUTREG> _ => REG_R12W </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 1 </REXR> +<REG> 4 </REG> -rule <OUTREG> _ => REG_ZMM29 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 2 </VEXDEST210> +rule <OUTREG> _ => REG_R13W </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 1 </REXR> +<REG> 5 </REG> -rule <OUTREG> _ => REG_ZMM30 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 1 </VEXDEST210> +rule <OUTREG> _ => REG_R14W </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 1 </REXR> +<REG> 6 </REG> -rule <OUTREG> _ => REG_ZMM31 </OUTREG> -<k> ZMM_N3_64 => . ... </k> -<VEXDEST4> 1 </VEXDEST4> -<VEXDEST3> 0 </VEXDEST3> -<VEXDEST210> 0 </VEXDEST210> +rule <OUTREG> _ => REG_R15W </OUTREG> +<k> GPR16_R => . ... </k> +<REXR> 1 </REXR> +<REG> 7 </REG> diff --git a/generator/datafiles/inum-opcode-map-groups.csv b/generator/datafiles/inum-opcode-map-groups.csv index 09d558804dbdf4e6b8610429391d8fcddad7d24a..c4c284e31bfdb8aefb588e1b0d44277a37d8bcc2 100644 --- a/generator/datafiles/inum-opcode-map-groups.csv +++ b/generator/datafiles/inum-opcode-map-groups.csv @@ -4952,10 +4952,18 @@ 3642,bsfq 3642,bsfw +3648,lzcntl +3648,lzcntq +3648,lzcntw + 3649,lzcntl 3649,lzcntq 3649,lzcntw +3650,bsrl +3650,bsrq +3650,bsrw + 3651,bsrl 3651,bsrq 3651,bsrw diff --git a/out.txt b/out.txt new file mode 100644 index 0000000000000000000000000000000000000000..6a07411ba38573387595b9be799f74656cec044f --- /dev/null +++ b/out.txt @@ -0,0 +1,162 @@ +adc $0x7f, %al +adcb $0x7f, (%rbx) +adcb %bl, (%rbx) +adcb %bh, (%rbx) +adc $0x7f, %bl +adcb (%rbx), %bl +adc %bl, %bl +adc %bh, %bl +adc $0x7f, %bh +adcb (%rbx), %bh +adc %bl, %bh +adc %bh, %bh +adc $0x7fffffff, %eax +adcl $0x7fffffff, (%rbx) +adcl $0x7f, (%rbx) +adcl %ebx, (%rbx) +adc $0x7fffffff, %ebx +adc $0x7f, %ebx +adcl (%rbx), %ebx +adc %ebx, %ebx +adcq $0x7fffffff, (%rbx) +adcq $0x7f, (%rbx) +adcq %rbx, (%rbx) +adc $0x7fffffff, %rbx +adc $0x7f, %rbx +adcq (%rbx), %rbx +adc %rbx, %rbx +adc $0x7fffffff, %rax +adc $0x7fff, %ax +adcw $0x7fff, (%rbx) +adcw $0x7f, (%rbx) +adcw %bx, (%rbx) +adc $0x7fff, %bx +adc $0x7f, %bx +adcw (%rbx), %bx +adc %bx, %bx +add $0x7f, %al +addb $0x7f, (%rbx) +addb %bl, (%rbx) +addb %bh, (%rbx) +add $0x7f, %bl +addb (%rbx), %bl +add %bl, %bl +add %bh, %bl +add $0x7f, %bh +addb (%rbx), %bh +add %bl, %bh +add %bh, %bh +add $0x7fffffff, %eax +addl $0x7fffffff, (%rbx) +addl $0x7f, (%rbx) +addl %ebx, (%rbx) +add $0x7fffffff, %ebx +add $0x7f, %ebx +addl (%rbx), %ebx +add %ebx, %ebx +addpdx (%rbx), %xmm1 +addpd %xmm1, %xmm1 +addpsx (%rbx), %xmm1 +addps %xmm1, %xmm1 +addq $0x7fffffff, (%rbx) +addq $0x7f, (%rbx) +addq %rbx, (%rbx) +add $0x7fffffff, %rbx +add $0x7f, %rbx +addq (%rbx), %rbx +add %rbx, %rbx +add $0x7fffffff, %rax +addsdq (%rbx), %xmm1 +addsd %xmm1, %xmm1 +addssl (%rbx), %xmm1 +addss %xmm1, %xmm1 +addsubpdx (%rbx), %xmm1 +addsubpd %xmm1, %xmm1 +addsubpsx (%rbx), %xmm1 +addsubps %xmm1, %xmm1 +add $0x7fff, %ax +addw $0x7fff, (%rbx) +addw $0x7f, (%rbx) +addw %bx, (%rbx) +add $0x7fff, %bx +add $0x7f, %bx +addw (%rbx), %bx +add %bx, %bx +and $0x7f, %al +andb $0x7f, (%rbx) +andb %bl, (%rbx) +andb %bh, (%rbx) +and $0x7f, %bl +andb (%rbx), %bl +and %bl, %bl +and %bh, %bl +and $0x7f, %bh +andb (%rbx), %bh +and %bl, %bh +and %bh, %bh +and $0x7fffffff, %eax +andl $0x7fffffff, (%rbx) +andl $0x7f, (%rbx) +andl %ebx, (%rbx) +and $0x7fffffff, %ebx +and $0x7f, %ebx +andl (%rbx), %ebx +and %ebx, %ebx +andnl (%rbx), %ebx, %ebx +andn %ebx, %ebx, %ebx +andnpdx (%rbx), %xmm1 +andnpd %xmm1, %xmm1 +andnpsx (%rbx), %xmm1 +andnps %xmm1, %xmm1 +andnq (%rbx), %rbx, %rbx +andn %rbx, %rbx, %rbx +andpdx (%rbx), %xmm1 +andpd %xmm1, %xmm1 +andpsx (%rbx), %xmm1 +andps %xmm1, %xmm1 +andq $0x7fffffff, (%rbx) +andq $0x7f, (%rbx) +andq %rbx, (%rbx) +and $0x7fffffff, %rbx +and $0x7f, %rbx +andq (%rbx), %rbx +and %rbx, %rbx +and $0x7fffffff, %rax +and $0x7fff, %ax +andw $0x7fff, (%rbx) +andw $0x7f, (%rbx) +andw %bx, (%rbx) +and $0x7fff, %bx +and $0x7f, %bx +andw (%rbx), %bx +and %bx, %bx +bextrl %ebx, (%rbx), %ebx +bextr %ebx, %ebx, %ebx +bextrq %rbx, (%rbx), %rbx +bextr %rbx, %rbx, %rbx +blendpdx $0x7f, (%rbx), %xmm1 +blendpd $0x7f, %xmm1, %xmm1 +blendpsx $0x7f, (%rbx), %xmm1 +blendps $0x7f, %xmm1, %xmm1 +blendvpdx (%rbx), %xmm1 +blendvpd %xmm1, %xmm1 +blendvpsx (%rbx), %xmm1 +blendvps %xmm1, %xmm1 +blsil (%rbx), %ebx +blsi %ebx, %ebx +blsiq (%rbx), %rbx +blsi %rbx, %rbx +blsmskl (%rbx), %ebx +blsmsk %ebx, %ebx +blsmskq (%rbx), %rbx +blsmsk %rbx, %rbx +blsrl (%rbx), %ebx +blsr %ebx, %ebx +blsrq (%rbx), %rbx +blsr %rbx, %rbx +bsfl (%rbx), %ebx +bsf %ebx, %ebx +bsfq (%rbx), %rbx +bsf %rbx, %rbx +bsfw (%rbx), %bx +bsf %bx, %bx diff --git a/semantics-glue.k b/semantics-glue.k index 2311460a12df01f0aec35965f5121d2aeca5ff4b..20d7ee1600277702bc53ee01b59ea7a73a053fc9 100644 --- a/semantics-glue.k +++ b/semantics-glue.k @@ -10,7 +10,7 @@ module SEMANTICS-GLUE syntax Register ::= UnsupportedRegister - syntax Register ::= DissassemblerRegisterToSemanticsRegister(K, Bool) [function] + syntax Register ::= DisassemblerRegisterToSemanticsRegister(K, Bool) [function] rule DisassemblerRegisterToSemanticsRegister(REG_INVALID, _) => %invalid rule DisassemblerRegisterToSemanticsRegister(REG_BND0, _) => %bnd0 diff --git a/smallest.txt b/smallest.txt new file mode 100644 index 0000000000000000000000000000000000000000..22392cc2bb22fb73e86212ed85bd6db0f5acbdf3 --- /dev/null +++ b/smallest.txt @@ -0,0 +1 @@ +Disassemble(0x264, 0xF30FBD1B); diff --git a/test-decoder.k b/test-decoder.k index 900ef06d3f13584e37efa1d48355dcf26f80aac2..4618df8122938d05f15bef939e9443c0b87dc3f9 100644 --- a/test-decoder.k +++ b/test-decoder.k @@ -63,10 +63,14 @@ module TEST-DECODER syntax KResult ::= DecoderResult syntax K ::= CheckDecodeLen(K, Int) [strict] + syntax Int ::= lengthInts(Ints) [function] + rule lengthInts(.Ints) => 0 + rule lengthInts(I:Int Is:Ints) => 1 +Int lengthInts(Is) + syntax String ::= OpcodeToString(Opcode) [function, hook(STRING.token2string)] - rule Disassemble(Addr:HexToken, Isn:HexToken) => CheckDecodeLen(Decode(HexTokenToInt(Addr), HexTokenToInts(Isn)), CountInInts(HexTokenToInts(Isn))) + rule Disassemble(Addr:HexToken, Isn:HexToken) => CheckDecodeLen(Decode(HexTokenToInt(Addr), HexTokenToInts(Isn)), lengthInts(HexTokenToInts(Isn))) - rule <k> CheckDecodeLen(DecodedInstruction(I:Int, S:String, O:Opcode _:Operands), I) => . ... </k> - <output> ... (.List => ListItem(S +String " " +String OpcodeToString(O) +String "\n")) </output> + rule <k> CheckDecodeLen(DecodedInstruction(I:Int, S:String, _), I) => . ... </k> + <output> ... (.List => ListItem(S +String "\n")) </output> endmodule