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haiyang3
Verilog Ethernet
Repository
84004c720dd1a873db96632c9c766badf1de59be
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verilog-ethernet
example
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git@gitlab.engr.illinois.edu:haiyang3/verilog-ethernet.git
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https://gitlab.engr.illinois.edu/haiyang3/verilog-ethernet.git
Use start_soon instead of fork
Alex Forencich authored
3 years ago
1f80696b
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1f80696b
3 years ago
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520N_MX/fpga_10g
ADM_PCIE_9V3
ATLYS/fpga
AU200/fpga_10g
AU250/fpga_10g
AU280/fpga_10g
AU50/fpga_10g
Arty/fpga
C10LP/fpga
DE2-115/fpga
DE5-Net/fpga
ExaNIC_X10/fpga
ExaNIC_X25/fpga_10g
HTG9200/fpga_10g
HXT100G
KC705
ML605
NetFPGA_SUME/fpga
NexysVideo/fpga
S10DX_DK/fpga_10g
S10MX_DK/fpga_10g
VCU108
VCU118
VCU1525/fpga_10g
ZCU102/fpga
ZCU106/fpga
fb2CG/fpga_10g