diff --git a/lib/axis/README.md b/lib/axis/README.md
index 8ea4b149d2eee23c026a4ff62833e76c1e7964a2..397ca505379162edc7476795cabeec72c9eb644f 100644
--- a/lib/axis/README.md
+++ b/lib/axis/README.md
@@ -205,7 +205,7 @@ Parametrizable priority encoder.
DATA_WIDTH : width of tdata signal
KEEP_ENABLE : enable tkeep signal (default DATA_WIDTH>8)
- KEEP_WIDTH : width of tkeep signal (default DATA_WIDTH/8)
+ KEEP_WIDTH : width of tkeep signal (default (DATA_WIDTH+7)/8)
LAST_ENABLE : enable tlast signal
ID_ENABLE : enable tid signal
ID_WIDTH : width of tid signal
diff --git a/lib/axis/rtl/axis_adapter.v b/lib/axis/rtl/axis_adapter.v
index cb3325106f725f2c4eb6e654e0331c3493156ccb..51aa226ac23c15742d762b34367e6dd1a6f2aa45 100644
--- a/lib/axis/rtl/axis_adapter.v
+++ b/lib/axis/rtl/axis_adapter.v
@@ -39,14 +39,14 @@ module axis_adapter #
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/rtl/axis_arb_mux.v b/lib/axis/rtl/axis_arb_mux.v
index 83bdd4f6bec5bb77bfccec8637cccddde1bc9816..43a588f4108245153b4e5761d84ce0173a07f99d 100644
--- a/lib/axis/rtl/axis_arb_mux.v
+++ b/lib/axis/rtl/axis_arb_mux.v
@@ -40,7 +40,7 @@ module axis_arb_mux #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/lib/axis/rtl/axis_arb_mux_wrap.py b/lib/axis/rtl/axis_arb_mux_wrap.py
index 091d36612846bd21fe8087c8f48b6b6e03a81e8e..076d8a1a9620caef3a7f646a437feea691f57633 100755
--- a/lib/axis/rtl/axis_arb_mux_wrap.py
+++ b/lib/axis/rtl/axis_arb_mux_wrap.py
@@ -75,7 +75,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/lib/axis/rtl/axis_async_fifo.v b/lib/axis/rtl/axis_async_fifo.v
index 2d89f2da4810cd8147e9e60080539275030c0a70..4f1e3601e8b41778fae165d2c8902263777108b4 100644
--- a/lib/axis/rtl/axis_async_fifo.v
+++ b/lib/axis/rtl/axis_async_fifo.v
@@ -43,7 +43,7 @@ module axis_async_fifo #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_async_fifo_adapter.v b/lib/axis/rtl/axis_async_fifo_adapter.v
index 76a293a695a8eaf4c9ba0c14a7a2f0f9cc1a694f..848fcf501fc27d87d6e71541fed8e24c8c832553 100644
--- a/lib/axis/rtl/axis_async_fifo_adapter.v
+++ b/lib/axis/rtl/axis_async_fifo_adapter.v
@@ -43,14 +43,14 @@ module axis_async_fifo_adapter #
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/rtl/axis_broadcast.v b/lib/axis/rtl/axis_broadcast.v
index 16137ea73be3fb9535ec6fe024f116ed41841480..34fafd2665a599cdc7024a982fd576e85b31c800 100644
--- a/lib/axis/rtl/axis_broadcast.v
+++ b/lib/axis/rtl/axis_broadcast.v
@@ -40,7 +40,7 @@ module axis_broadcast #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_broadcast_wrap.py b/lib/axis/rtl/axis_broadcast_wrap.py
index e755a20ea540a1026f1bc748687e0b5f0f6afbe8..acd31571c2e2b80b28693d12e602267d489627ca 100755
--- a/lib/axis/rtl/axis_broadcast_wrap.py
+++ b/lib/axis/rtl/axis_broadcast_wrap.py
@@ -75,7 +75,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_crosspoint.v b/lib/axis/rtl/axis_crosspoint.v
index c6574d2699dd1fe0d99778a59e76a2b872825a93..7fde4ab4ed6353be97bbda0727c65961821f28fe 100644
--- a/lib/axis/rtl/axis_crosspoint.v
+++ b/lib/axis/rtl/axis_crosspoint.v
@@ -42,7 +42,7 @@ module axis_crosspoint #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_crosspoint_wrap.py b/lib/axis/rtl/axis_crosspoint_wrap.py
index f7396532b2c3ad5d664726f232cb165395f341c4..0646ec8a8132571b4b8d7397c25cde0e64cd88e1 100755
--- a/lib/axis/rtl/axis_crosspoint_wrap.py
+++ b/lib/axis/rtl/axis_crosspoint_wrap.py
@@ -81,7 +81,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_demux.v b/lib/axis/rtl/axis_demux.v
index 796799e552355cd67f5cad94fd45eaef93fe142f..7edd757f509a5711b9469cf90fc33d29fee29af2 100644
--- a/lib/axis/rtl/axis_demux.v
+++ b/lib/axis/rtl/axis_demux.v
@@ -40,7 +40,7 @@ module axis_demux #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/rtl/axis_demux_wrap.py b/lib/axis/rtl/axis_demux_wrap.py
index 344c8bcb053654b1251c7559df08a6c4aea3f702..bc73117658dcb07a26b680127f9b1e383f1ccff8 100755
--- a/lib/axis/rtl/axis_demux_wrap.py
+++ b/lib/axis/rtl/axis_demux_wrap.py
@@ -75,7 +75,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/rtl/axis_fifo.v b/lib/axis/rtl/axis_fifo.v
index bf3be6e199c07df0d32ca322d8184b76449cfbfe..c93147461554736a903d22b6b9482daaf5dbb346 100644
--- a/lib/axis/rtl/axis_fifo.v
+++ b/lib/axis/rtl/axis_fifo.v
@@ -43,7 +43,7 @@ module axis_fifo #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_fifo_adapter.v b/lib/axis/rtl/axis_fifo_adapter.v
index 7b43b00709c623e48ada74ff5c04cf4812734f91..095d6ce7463d5328b895ebeb71fb73298a350c9a 100644
--- a/lib/axis/rtl/axis_fifo_adapter.v
+++ b/lib/axis/rtl/axis_fifo_adapter.v
@@ -43,14 +43,14 @@ module axis_fifo_adapter #
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/rtl/axis_frame_len.v b/lib/axis/rtl/axis_frame_len.v
index a1f75e5d77708caa37a6c5deb8ed42b4f0385d49..49ce097a1c24903344f483075721e6c84ba905e2 100644
--- a/lib/axis/rtl/axis_frame_len.v
+++ b/lib/axis/rtl/axis_frame_len.v
@@ -39,7 +39,7 @@ module axis_frame_len #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Width of length counter
parameter LEN_WIDTH = 16
)
diff --git a/lib/axis/rtl/axis_frame_length_adjust.v b/lib/axis/rtl/axis_frame_length_adjust.v
index 42550ad008c245e67bc642d5faa9d874fde8c122..92fb2ec1187a0afc2184345c6b89caaa3d292b53 100644
--- a/lib/axis/rtl/axis_frame_length_adjust.v
+++ b/lib/axis/rtl/axis_frame_length_adjust.v
@@ -39,7 +39,7 @@ module axis_frame_length_adjust #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/rtl/axis_frame_length_adjust_fifo.v b/lib/axis/rtl/axis_frame_length_adjust_fifo.v
index a580cee9dba80c11d3859dc4b8481cfd74761f8a..f2bc4a06564dc7014f615af29b7d7370d14f779d 100644
--- a/lib/axis/rtl/axis_frame_length_adjust_fifo.v
+++ b/lib/axis/rtl/axis_frame_length_adjust_fifo.v
@@ -39,7 +39,7 @@ module axis_frame_length_adjust_fifo #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/rtl/axis_mux.v b/lib/axis/rtl/axis_mux.v
index ba97d939097b4626ef6fef50d75b93c3eafddd72..ab021d3ef74fde89d078764d9f45e5f2c643b469 100644
--- a/lib/axis/rtl/axis_mux.v
+++ b/lib/axis/rtl/axis_mux.v
@@ -40,7 +40,7 @@ module axis_mux #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/rtl/axis_mux_wrap.py b/lib/axis/rtl/axis_mux_wrap.py
index bc1b8325b8cf5d9dcf5d9db9722a499b03bd9c9a..00698cd0d94c851bfc40c4610f53f7ba796a2a39 100755
--- a/lib/axis/rtl/axis_mux_wrap.py
+++ b/lib/axis/rtl/axis_mux_wrap.py
@@ -75,7 +75,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/rtl/axis_pipeline_fifo.v b/lib/axis/rtl/axis_pipeline_fifo.v
index 0da8145735fd41ef37996e8feb7c56f1cf28967d..4c194bf7eb31e44aebdb89500439040430a196b7 100644
--- a/lib/axis/rtl/axis_pipeline_fifo.v
+++ b/lib/axis/rtl/axis_pipeline_fifo.v
@@ -38,7 +38,7 @@ module axis_pipeline_fifo #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_pipeline_register.v b/lib/axis/rtl/axis_pipeline_register.v
index 1e22ffcc9f082eedc89c92baf641470b170f3713..9715dca4b687165a70d1b8c3525232c930d7d37f 100644
--- a/lib/axis/rtl/axis_pipeline_register.v
+++ b/lib/axis/rtl/axis_pipeline_register.v
@@ -38,7 +38,7 @@ module axis_pipeline_register #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_ram_switch.v b/lib/axis/rtl/axis_ram_switch.v
index ed831fe28435359750f45f5df7f714de42d7ae59..ac31dcca2cd24974113432458ecd075ae31df3a0 100644
--- a/lib/axis/rtl/axis_ram_switch.v
+++ b/lib/axis/rtl/axis_ram_switch.v
@@ -52,13 +52,13 @@ module axis_ram_switch #
// Propagate tkeep signal
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interfaces in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/lib/axis/rtl/axis_ram_switch_wrap.py b/lib/axis/rtl/axis_ram_switch_wrap.py
index 45adfed5bf389e29f435c06185dd2f109953f5a1..1dbd223a8d1c6ae31eeb9744a08912b6391aa96c 100755
--- a/lib/axis/rtl/axis_ram_switch_wrap.py
+++ b/lib/axis/rtl/axis_ram_switch_wrap.py
@@ -91,13 +91,13 @@ module {{name}} #
// Propagate tkeep signal
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interfaces in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/lib/axis/rtl/axis_rate_limit.v b/lib/axis/rtl/axis_rate_limit.v
index 3f91b4cbcb358cae3b07cbd1e5afd7999dddf461..24ec9546a0b45e2ece148cb763c7ece05b9cffee 100644
--- a/lib/axis/rtl/axis_rate_limit.v
+++ b/lib/axis/rtl/axis_rate_limit.v
@@ -39,7 +39,7 @@ module axis_rate_limit #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_register.v b/lib/axis/rtl/axis_register.v
index fbd245c1f66955a04755f5057e86ca0f42ff622a..7e8f109310f95da8414ed3373dc35eefee2af4b3 100644
--- a/lib/axis/rtl/axis_register.v
+++ b/lib/axis/rtl/axis_register.v
@@ -38,7 +38,7 @@ module axis_register #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_srl_fifo.v b/lib/axis/rtl/axis_srl_fifo.v
index e0cc4164a14d0dff2b1944627ecf55d512122895..7eabf8f45096245628c6ce4765e033912cf6889c 100644
--- a/lib/axis/rtl/axis_srl_fifo.v
+++ b/lib/axis/rtl/axis_srl_fifo.v
@@ -38,7 +38,7 @@ module axis_srl_fifo #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_srl_register.v b/lib/axis/rtl/axis_srl_register.v
index 4bfaeaafc066bb17322731b7cfeb95cb2b657730..f0e9efee28910e3f389832cfb1a10f72142b29db 100644
--- a/lib/axis/rtl/axis_srl_register.v
+++ b/lib/axis/rtl/axis_srl_register.v
@@ -38,7 +38,7 @@ module axis_srl_register #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/lib/axis/rtl/axis_stat_counter.v b/lib/axis/rtl/axis_stat_counter.v
index c59c441beda9fe24413cf2e1e04cf1a90413a419..cc04760839aaa472a51306335ca7b151c59d451f 100644
--- a/lib/axis/rtl/axis_stat_counter.v
+++ b/lib/axis/rtl/axis_stat_counter.v
@@ -39,7 +39,7 @@ module axis_stat_counter #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Prepend data with tag
parameter TAG_ENABLE = 1,
// Tag field width
diff --git a/lib/axis/rtl/axis_switch.v b/lib/axis/rtl/axis_switch.v
index c949b700b618e60744512075b01042628bb026e4..d791294bbffe5f91ce054b6e365f2f42dacf002e 100644
--- a/lib/axis/rtl/axis_switch.v
+++ b/lib/axis/rtl/axis_switch.v
@@ -42,7 +42,7 @@ module axis_switch #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/lib/axis/rtl/axis_switch_wrap.py b/lib/axis/rtl/axis_switch_wrap.py
index 0af37e02acbfd44393c59679191b1fa78383afd4..e3e13dc393a913e1305f3ec22077935e8eb35b43 100755
--- a/lib/axis/rtl/axis_switch_wrap.py
+++ b/lib/axis/rtl/axis_switch_wrap.py
@@ -81,7 +81,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/lib/axis/rtl/axis_tap.v b/lib/axis/rtl/axis_tap.v
index a9c7e19e1fb19f21b226f3a55170f613034a0781..13966adcb0db5bf4a613bee52fccef8bffa725e1 100644
--- a/lib/axis/rtl/axis_tap.v
+++ b/lib/axis/rtl/axis_tap.v
@@ -38,7 +38,7 @@ module axis_tap #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/lib/axis/tb/axis_adapter/Makefile b/lib/axis/tb/axis_adapter/Makefile
index af559301a0111272bcbb019702ef979a78e5e765..621657d76c2508b7b9403c664847a0086ca77204 100644
--- a/lib/axis/tb/axis_adapter/Makefile
+++ b/lib/axis/tb/axis_adapter/Makefile
@@ -34,10 +34,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_adapter/test_axis_adapter.py b/lib/axis/tb/axis_adapter/test_axis_adapter.py
index addc7274575cf45a2a6e3f6c1052dacac03e367f..5997d61ef9c13172d55da2cba0866b11dab3ec6e 100644
--- a/lib/axis/tb/axis_adapter/test_axis_adapter.py
+++ b/lib/axis/tb/axis_adapter/test_axis_adapter.py
@@ -227,10 +227,10 @@ def test_axis_register(request, s_data_width, m_data_width):
parameters['S_DATA_WIDTH'] = s_data_width
parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
- parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+ parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
parameters['M_DATA_WIDTH'] = m_data_width
parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
- parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+ parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/lib/axis/tb/axis_arb_mux/Makefile b/lib/axis/tb/axis_arb_mux/Makefile
index 962af950fff112fe5abc2a58d73bb66fd484e15a..936f22b1c00610f811cc6ef63dee03d6051cb232 100644
--- a/lib/axis/tb/axis_arb_mux/Makefile
+++ b/lib/axis/tb/axis_arb_mux/Makefile
@@ -40,7 +40,7 @@ VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 8
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())")
diff --git a/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py b/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py
index ec23a41c7a80eb31c8a4181063409e8b596d7b18..187964b326fc987db0b8d7b890a80e2349bf0478 100644
--- a/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py
+++ b/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py
@@ -344,7 +344,7 @@ def test_axis_arb_mux(request, ports, data_width, round_robin):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['S_ID_WIDTH'] = 8
parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (ports-1).bit_length()
diff --git a/lib/axis/tb/axis_async_fifo/Makefile b/lib/axis/tb/axis_async_fifo/Makefile
index 75efe9944f8e5eeaf3560c0d5d4e468fd40e45ee..f301f8b4546ecd68f56a484d20e5ed0cefed5ff2 100644
--- a/lib/axis/tb/axis_async_fifo/Makefile
+++ b/lib/axis/tb/axis_async_fifo/Makefile
@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py b/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py
index 223a7e36c062dec830ce95a1fab1b2745e9b5979..fb3026d8b71e921afb2921e4c71950c7a3623605 100644
--- a/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py
+++ b/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py
@@ -539,7 +539,7 @@ def test_axis_async_fifo(request, data_width, frame_fifo, drop_oversize_frame, d
parameters['DEPTH'] = 1024
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/lib/axis/tb/axis_async_fifo_adapter/Makefile b/lib/axis/tb/axis_async_fifo_adapter/Makefile
index 1471541eb47aba5fe4a200418c9026b27e551bcf..c193ebb0d90aa0b72acdcfdaad2215ca9933331d 100644
--- a/lib/axis/tb/axis_async_fifo_adapter/Makefile
+++ b/lib/axis/tb/axis_async_fifo_adapter/Makefile
@@ -37,10 +37,10 @@ VERILOG_SOURCES += ../../rtl/axis_adapter.v
export PARAM_DEPTH ?= 1024
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py b/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py
index 6ff2ac88debed9a7cee28ef5a76b59f7c48e5b36..bae15ef00be128fcb59251011e80a5bdaaef1c0f 100644
--- a/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py
+++ b/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py
@@ -536,10 +536,10 @@ def test_axis_async_fifo_adapter(request, s_data_width, m_data_width, frame_fifo
parameters['DEPTH'] = 1024
parameters['S_DATA_WIDTH'] = s_data_width
parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
- parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+ parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
parameters['M_DATA_WIDTH'] = m_data_width
parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
- parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+ parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/lib/axis/tb/axis_broadcast/Makefile b/lib/axis/tb/axis_broadcast/Makefile
index 8bd2282a3c509ea4a699b40b95f463a00d2029bc..7b66215cdaec9d09ee8773d74999fbe088b5938c 100644
--- a/lib/axis/tb/axis_broadcast/Makefile
+++ b/lib/axis/tb/axis_broadcast/Makefile
@@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_broadcast/test_axis_broadcast.py b/lib/axis/tb/axis_broadcast/test_axis_broadcast.py
index 8bc7ac9a9fb5f2f550cc1c72f0fbe0286f54ce30..caca51885f940f744c345f7400c9a47465342e23 100644
--- a/lib/axis/tb/axis_broadcast/test_axis_broadcast.py
+++ b/lib/axis/tb/axis_broadcast/test_axis_broadcast.py
@@ -170,7 +170,7 @@ def test_axis_broadcast(request, ports, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/lib/axis/tb/axis_demux/Makefile b/lib/axis/tb/axis_demux/Makefile
index 6fd45472c44729026641fdf1970bca311c490cc0..8822019d2dd379998a9051bff532bd608387d052 100644
--- a/lib/axis/tb/axis_demux/Makefile
+++ b/lib/axis/tb/axis_demux/Makefile
@@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/lib/axis/tb/axis_demux/test_axis_demux.py b/lib/axis/tb/axis_demux/test_axis_demux.py
index 832b02118e1c79f57be7531f8e19c8bf024480cf..bce6b471c5deafd857df027eb9597b5347560972 100644
--- a/lib/axis/tb/axis_demux/test_axis_demux.py
+++ b/lib/axis/tb/axis_demux/test_axis_demux.py
@@ -186,7 +186,7 @@ def test_axis_demux(request, ports, data_width, tdest_route):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/lib/axis/tb/axis_fifo/Makefile b/lib/axis/tb/axis_fifo/Makefile
index 9073da6cc4f221f2a5c4d9b740c3f92c5690ca0d..fabad14d26cf62119028ddd7dfe49acc37249b13 100644
--- a/lib/axis/tb/axis_fifo/Makefile
+++ b/lib/axis/tb/axis_fifo/Makefile
@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_fifo/test_axis_fifo.py b/lib/axis/tb/axis_fifo/test_axis_fifo.py
index 61b5351dea5b856c2fb2f598f8d0c9bfbc9e132a..db13ca87bb701eda6716e98057601670ec0ece02 100644
--- a/lib/axis/tb/axis_fifo/test_axis_fifo.py
+++ b/lib/axis/tb/axis_fifo/test_axis_fifo.py
@@ -329,7 +329,7 @@ def test_axis_fifo(request, data_width, frame_fifo, drop_oversize_frame, drop_ba
parameters['DEPTH'] = 1024
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/lib/axis/tb/axis_fifo_adapter/Makefile b/lib/axis/tb/axis_fifo_adapter/Makefile
index 786c51c5329af7bc4ad92d3dfd4e4cad0c39eb9a..86e3f2f3c2e41f4da73d6164dfbad9af31f7d615 100644
--- a/lib/axis/tb/axis_fifo_adapter/Makefile
+++ b/lib/axis/tb/axis_fifo_adapter/Makefile
@@ -37,10 +37,10 @@ VERILOG_SOURCES += ../../rtl/axis_adapter.v
export PARAM_DEPTH ?= 1024
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py b/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py
index 6ff21ca98c249f44bdae8a702ed9e4e506d2aa68..bc3fc76ecb38002155506c7c9655bfc2d82fbfc8 100644
--- a/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py
+++ b/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py
@@ -332,10 +332,10 @@ def test_axis_fifo_adapter(request, s_data_width, m_data_width, frame_fifo, drop
parameters['DEPTH'] = 1024
parameters['S_DATA_WIDTH'] = s_data_width
parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
- parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+ parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
parameters['M_DATA_WIDTH'] = m_data_width
parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
- parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+ parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/lib/axis/tb/axis_frame_length_adjust/Makefile b/lib/axis/tb/axis_frame_length_adjust/Makefile
index 0cec922d893316b004bc694b25a88e81ca753404..abe6052c376d3de472816fcccd72ad8c20ec061b 100644
--- a/lib/axis/tb/axis_frame_length_adjust/Makefile
+++ b/lib/axis/tb/axis_frame_length_adjust/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py b/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py
index 5817f5c0d2cfb86593dec104ba1ec8e3a8554339..260c9fe524887189e7b93c98f23102aa33d23b87 100644
--- a/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py
+++ b/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py
@@ -214,7 +214,7 @@ def test_axis_frame_length_adjust(request, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile b/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile
index ed886c2a2494e2a42734b4183443825fcd18ac70..59b5d822c84095019f7d22a89fc48b443b10a672 100644
--- a/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile
+++ b/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile
@@ -36,7 +36,7 @@ VERILOG_SOURCES += ../../rtl/axis_fifo.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py b/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py
index b3403cd00cd320f4664ec53fd91d73746bdb4484..0ad01cf862fe4ebeb1c6fd502672db7650cc4fcd 100644
--- a/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py
+++ b/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py
@@ -306,7 +306,7 @@ def test_axis_frame_length_adjust_fifo(request, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/lib/axis/tb/axis_mux/Makefile b/lib/axis/tb/axis_mux/Makefile
index 5323a4d3f44dac3b2ea64797cf0c822e7b4d08d1..247a0784c3aa2d1137e073d02a849741b407ff6f 100644
--- a/lib/axis/tb/axis_mux/Makefile
+++ b/lib/axis/tb/axis_mux/Makefile
@@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/lib/axis/tb/axis_mux/test_axis_mux.py b/lib/axis/tb/axis_mux/test_axis_mux.py
index 217b03ce6d542494297326f6c29d1a4027c8ab92..d722acf11006385c59e7d51acc8d395e3eb005c0 100644
--- a/lib/axis/tb/axis_mux/test_axis_mux.py
+++ b/lib/axis/tb/axis_mux/test_axis_mux.py
@@ -206,7 +206,7 @@ def test_axis_mux(request, ports, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/lib/axis/tb/axis_pipeline_fifo/Makefile b/lib/axis/tb/axis_pipeline_fifo/Makefile
index cfb36c0b3895d06d4438a31a1d6608c76a276e0a..a356a55e1374bd7b4ff14070649d12e2d279f921 100644
--- a/lib/axis/tb/axis_pipeline_fifo/Makefile
+++ b/lib/axis/tb/axis_pipeline_fifo/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py b/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py
index 830b0337662301422055c3e3175f7514fe81b2d2..575598579b985638ec36de36f7d400605a107d0f 100644
--- a/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py
+++ b/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py
@@ -317,7 +317,7 @@ def test_axis_pipeline_fifo(request, length, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/lib/axis/tb/axis_pipeline_register/Makefile b/lib/axis/tb/axis_pipeline_register/Makefile
index b635f72897d00c146cfdc2b6a603e8d24a74f8f2..13e6e6cf5ed9486d67acce90b1efb96829b6e9d5 100644
--- a/lib/axis/tb/axis_pipeline_register/Makefile
+++ b/lib/axis/tb/axis_pipeline_register/Makefile
@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/axis_register.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py b/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py
index a971e8e19d527b7019b5b1af8d3315420f9db349..2ea13bf52487db94fee3cdf7ab551a81b1cc358f 100644
--- a/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py
+++ b/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py
@@ -229,7 +229,7 @@ def test_axis_pipeline_register(request, length, data_width, reg_type):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/lib/axis/tb/axis_ram_switch/Makefile b/lib/axis/tb/axis_ram_switch/Makefile
index adfea859f019261fbcd2b520c947fcfa7cbb6e3c..6b07dabe71db33c95e771b41bd736f0fac973bb9 100644
--- a/lib/axis/tb/axis_ram_switch/Makefile
+++ b/lib/axis/tb/axis_ram_switch/Makefile
@@ -45,10 +45,10 @@ export PARAM_CMD_FIFO_DEPTH ?= 32
export PARAM_SPEEDUP ?= 0
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 16
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
diff --git a/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py b/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py
index 422fcd843e1f936bc94e9244bf6e6145a0292717..6bc3fd1ee52909b848369a3f6dcd21d0e16021da 100644
--- a/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py
+++ b/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py
@@ -356,10 +356,10 @@ def test_axis_ram_switch(request, s_count, m_count, s_data_width, m_data_width):
parameters['SPEEDUP'] = 0
parameters['S_DATA_WIDTH'] = s_data_width
parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
- parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+ parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
parameters['M_DATA_WIDTH'] = m_data_width
parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
- parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+ parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['S_ID_WIDTH'] = 16
parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length()
diff --git a/lib/axis/tb/axis_rate_limit/Makefile b/lib/axis/tb/axis_rate_limit/Makefile
index 4da3e0bb0de9ded490c7ead775ed8c1c1654381f..002d611ce06fc93a36e73e63d6e4376655fe304d 100644
--- a/lib/axis/tb/axis_rate_limit/Makefile
+++ b/lib/axis/tb/axis_rate_limit/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py b/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py
index 170419df2affda23fd4a45b0b6e08815ac04c8ae..f54828e7c85d6ac2f16b2ebbea36fc1f347b711c 100644
--- a/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py
+++ b/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py
@@ -187,7 +187,7 @@ def test_axis_rate_limit(request, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/lib/axis/tb/axis_register/Makefile b/lib/axis/tb/axis_register/Makefile
index 20747961b54981ad45cf02f0af9b658a16e48dde..0a2e2e9de46d8958cadf5780917fe335fc51c9a7 100644
--- a/lib/axis/tb/axis_register/Makefile
+++ b/lib/axis/tb/axis_register/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_register/test_axis_register.py b/lib/axis/tb/axis_register/test_axis_register.py
index bd9e3e794cb3114a942d8de953a038452f961332..55e4c7864a6ecbd8276480571994c2cd1df3473d 100644
--- a/lib/axis/tb/axis_register/test_axis_register.py
+++ b/lib/axis/tb/axis_register/test_axis_register.py
@@ -227,7 +227,7 @@ def test_axis_register(request, data_width, reg_type):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/lib/axis/tb/axis_srl_fifo/Makefile b/lib/axis/tb/axis_srl_fifo/Makefile
index 35b77686b0c17afb1515f939ca35c8588a3b82e5..43b43716c7f12ff5b0029a195b8c53f010d2ee02 100644
--- a/lib/axis/tb/axis_srl_fifo/Makefile
+++ b/lib/axis/tb/axis_srl_fifo/Makefile
@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py b/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py
index e18fd8a88cf762035d035ccb41a9bebbc42355aa..0e7281a818b910594f7228f1ee5257a515ae0adc 100644
--- a/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py
+++ b/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py
@@ -317,7 +317,7 @@ def test_axis_srl_fifo(request, data_width):
parameters['DEPTH'] = 1024
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/lib/axis/tb/axis_srl_register/Makefile b/lib/axis/tb/axis_srl_register/Makefile
index d1842025d76e84f49b14170f4243bc3d1e7a93ce..d7c66b7642f7e2fc7f669a1092b916c0a740744b 100644
--- a/lib/axis/tb/axis_srl_register/Makefile
+++ b/lib/axis/tb/axis_srl_register/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/lib/axis/tb/axis_srl_register/test_axis_srl_register.py b/lib/axis/tb/axis_srl_register/test_axis_srl_register.py
index 4dd1c0c37fd4f2bbb7f300d5149c7d03d56531ef..7be3ad87348db0d1206ef5303b5acaea75edc65c 100644
--- a/lib/axis/tb/axis_srl_register/test_axis_srl_register.py
+++ b/lib/axis/tb/axis_srl_register/test_axis_srl_register.py
@@ -226,7 +226,7 @@ def test_axis_srl_register(request, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/lib/axis/tb/axis_switch/Makefile b/lib/axis/tb/axis_switch/Makefile
index 9cf5559934b5339837f0cc42b2ed4e27c42cf8b3..a59fb3dbeae404810b529073ded110253f4f64a7 100644
--- a/lib/axis/tb/axis_switch/Makefile
+++ b/lib/axis/tb/axis_switch/Makefile
@@ -42,7 +42,7 @@ VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 16
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
diff --git a/lib/axis/tb/axis_switch/test_axis_switch.py b/lib/axis/tb/axis_switch/test_axis_switch.py
index 9e250e3334ab54fb7809b11b001c944b42909f7a..c2da5a08e13c7dd0942f2905b026063fd088cee4 100644
--- a/lib/axis/tb/axis_switch/test_axis_switch.py
+++ b/lib/axis/tb/axis_switch/test_axis_switch.py
@@ -351,7 +351,7 @@ def test_axis_switch(request, s_count, m_count, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['S_ID_WIDTH'] = 16
parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length()
diff --git a/lib/axis/tox.ini b/lib/axis/tox.ini
index 2fc6307f2e5296b86bb91ba79f44bd3ccb3f5a6c..0fba1b4bdbc23dd51eadd93f0c5ec9d043e22611 100644
--- a/lib/axis/tox.ini
+++ b/lib/axis/tox.ini
@@ -1,21 +1,23 @@
# tox configuration
[tox]
-envlist = py39
+envlist = py3
skipsdist = True
+minversion = 3.2.0
+requires = virtualenv >= 16.1
[gh-actions]
python =
- 3.9: py39
+ 3.9: py3
[testenv]
deps =
- pytest
- pytest-xdist
- pytest-split
- cocotb
- cocotb-test
- cocotbext-axi
- jinja2
+ pytest == 6.2.5
+ pytest-xdist == 2.4.0
+ pytest-split == 0.4.0
+ cocotb == 1.6.1
+ cocotb-test == 0.2.1
+ cocotbext-axi == 0.1.16
+ jinja2 == 3.0.3
commands =
pytest -n auto {posargs}