diff --git a/.gitignore b/.gitignore
index 868687a4769264ce17fb5713265a9153ba2de4a8..ab4f34111ef35ecff9636aed80434c6826e5dce0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,3 +4,6 @@
*.vvp
*.kate-swp
*.vcd
+fpga/
+*.jou
+*.log
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.veo b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.veo
new file mode 100644
index 0000000000000000000000000000000000000000..29e71b52e2eaa33e16c95b460bbc97f3eb62d2a4
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.veo
@@ -0,0 +1,76 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
+// IP Revision: 16
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+axis_dwidth_converter_256_64 your_instance_name (
+ .aclk(aclk), // input wire aclk
+ .aresetn(aresetn), // input wire aresetn
+ .s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
+ .s_axis_tready(s_axis_tready), // output wire s_axis_tready
+ .s_axis_tdata(s_axis_tdata), // input wire [255 : 0] s_axis_tdata
+ .s_axis_tkeep(s_axis_tkeep), // input wire [31 : 0] s_axis_tkeep
+ .s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast
+ .m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
+ .m_axis_tready(m_axis_tready), // input wire m_axis_tready
+ .m_axis_tdata(m_axis_tdata), // output wire [63 : 0] m_axis_tdata
+ .m_axis_tkeep(m_axis_tkeep), // output wire [7 : 0] m_axis_tkeep
+ .m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file axis_dwidth_converter_256_64.v when simulating
+// the core, axis_dwidth_converter_256_64. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.vho b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.vho
new file mode 100644
index 0000000000000000000000000000000000000000..3f68a29c66179a4e126170ce59080d679d1e1b39
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.vho
@@ -0,0 +1,97 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
+-- IP Revision: 16
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT axis_dwidth_converter_256_64
+ PORT (
+ aclk : IN STD_LOGIC;
+ aresetn : IN STD_LOGIC;
+ s_axis_tvalid : IN STD_LOGIC;
+ s_axis_tready : OUT STD_LOGIC;
+ s_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+ s_axis_tkeep : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axis_tlast : IN STD_LOGIC;
+ m_axis_tvalid : OUT STD_LOGIC;
+ m_axis_tready : IN STD_LOGIC;
+ m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+ m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ m_axis_tlast : OUT STD_LOGIC
+ );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : axis_dwidth_converter_256_64
+ PORT MAP (
+ aclk => aclk,
+ aresetn => aresetn,
+ s_axis_tvalid => s_axis_tvalid,
+ s_axis_tready => s_axis_tready,
+ s_axis_tdata => s_axis_tdata,
+ s_axis_tkeep => s_axis_tkeep,
+ s_axis_tlast => s_axis_tlast,
+ m_axis_tvalid => m_axis_tvalid,
+ m_axis_tready => m_axis_tready,
+ m_axis_tdata => m_axis_tdata,
+ m_axis_tkeep => m_axis_tkeep,
+ m_axis_tlast => m_axis_tlast
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file axis_dwidth_converter_256_64.vhd when simulating
+-- the core, axis_dwidth_converter_256_64. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.xci b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.xci
new file mode 100644
index 0000000000000000000000000000000000000000..30d630bcde1e3f51569ece81066df0477328ecad
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.xci
@@ -0,0 +1,102 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>axis_dwidth_converter_256_64</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_dwidth_converter" spirit:version="1.1"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKENIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_BUSIF"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_RESET"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.FREQ_HZ">10000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RSTIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_SIGNAL_SET">0b00000000000000000000000000011011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_TUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_TDATA_WIDTH">256</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_TUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axis_dwidth_converter_256_64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_MI_TKEEP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TLAST">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TREADY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_TDATA_NUM_BYTES">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcvu3p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvc1517</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_MI_TKEEP" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TKEEP" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TLAST" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.xml b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.xml
new file mode 100644
index 0000000000000000000000000000000000000000..9ec38351a4a8be8237a5630312ee11d7a819a2f0
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64.xml
@@ -0,0 +1,1525 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>customized_ip</spirit:library>
+ <spirit:name>axis_dwidth_converter_256_64</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>S_AXIS</spirit:name>
+ <spirit:displayName>S_AXIS</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TKEEP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tkeep</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
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+ <spirit:name>TLAST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tlast</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDEST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tdest</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tuser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>TDATA_NUM_BYTES</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">32</spirit:value>
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diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64_ooc.xdc b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64_ooc.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..fe7ad213da7a632d1930850f800954c298405df6
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/axis_dwidth_converter_256_64_ooc.xdc
@@ -0,0 +1,57 @@
+# (c) Copyright 2012-2022 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 100 -name aclk [get_ports aclk]
+
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/doc/axis_dwidth_converter_v1_1_changelog.txt b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/doc/axis_dwidth_converter_v1_1_changelog.txt
new file mode 100755
index 0000000000000000000000000000000000000000..c45ae2488b06b3d2d240826a0df9a7d4b8b5b874
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/doc/axis_dwidth_converter_v1_1_changelog.txt
@@ -0,0 +1,161 @@
+2018.2:
+ * Version 1.1 (Rev. 16)
+ * Revision change in one or more subcores
+
+2018.1:
+ * Version 1.1 (Rev. 15)
+ * General: Update internal register slice instantiation to tie-off unused input clock aclk2x.
+ * General: Change fsm encoding and remove unnecessary combinatorial reset tie-off on output valid/ready signals.
+ * General: Update initial values on register declarations to match reset values for reset-less operation.
+ * Revision change in one or more subcores
+
+2017.4:
+ * Version 1.1 (Rev. 14)
+ * Revision change in one or more subcores
+
+2017.3:
+ * Version 1.1 (Rev. 13)
+ * Initializing Valid/Ready Outputs to zero before reset kicks in
+ * Revision change in one or more subcores
+
+2017.2:
+ * Version 1.1 (Rev. 12)
+ * Revision change in one or more subcores
+
+2017.1:
+ * Version 1.1 (Rev. 11)
+ * Revision change in one or more subcores
+
+2016.4:
+ * Version 1.1 (Rev. 10)
+ * Revision change in one or more subcores
+
+2016.3:
+ * Version 1.1 (Rev. 9)
+ * Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Revision change in one or more subcores
+
+2016.2:
+ * Version 1.1 (Rev. 8)
+ * Revision change in one or more subcores
+
+2016.1:
+ * Version 1.1 (Rev. 7)
+ * Changes to HDL library management to support Vivado IP simulation library
+ * Revision change in one or more subcores
+
+2015.4.2:
+ * Version 1.1 (Rev. 6)
+ * No changes
+
+2015.4.1:
+ * Version 1.1 (Rev. 6)
+ * No changes
+
+2015.4:
+ * Version 1.1 (Rev. 6)
+ * Revision change in one or more subcores
+
+2015.3:
+ * Version 1.1 (Rev. 5)
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Configurations where there is non-multiple tdata width conversion (e.g., 2:3, 4:3, etc), no TKEEP and no TID, TDEST or TLAST signals present were found to be adding the TKEEP signal with all bits tied to LOW to the output M_AXIS interface. The TKEEP output can be ignored in this configuration. While the TKEEP is not needed, it has been kept to not break backwards compatibility and the vector is now being driven HIGH to produce a valid output. Configurations that require an upsizer (more than 1 input transfer is accumulated into 1 or more output transfers) and have TID/TDEST/TLAST and no TKEEP, will still produce a TKEEP. The TKEEP in this instance is not always tied HIGH and must be monitored if the input stream is not conditioned to ensure that TID/TDEST/TLAST do not toggle during accumulation.
+ * Revision change in one or more subcores
+
+2015.2.1:
+ * Version 1.1 (Rev. 4)
+ * No changes
+
+2015.2:
+ * Version 1.1 (Rev. 4)
+ * No changes
+
+2015.1:
+ * Version 1.1 (Rev. 4)
+ * The support status for Kintex UltraScale is changed from Pre-Production to Production.
+ * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF
+
+2014.4.1:
+ * Version 1.1 (Rev. 3)
+ * No changes
+
+2014.4:
+ * Version 1.1 (Rev. 3)
+ * Architecture support updated
+
+2014.3:
+ * Version 1.1 (Rev. 2)
+ * No changes
+
+2014.2:
+ * Version 1.1 (Rev. 2)
+ * No changes
+
+2014.1:
+ * Version 1.1 (Rev. 2)
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 1.1 (Rev. 1)
+ * Kintex UltraScale Pre-Production support
+
+2013.3:
+ * Version 1.1
+ * Added example design
+ * Initial default value for maximum range of TUSER bits per num TDATA bytes changed from 32 to 2048 to correspond with a TDATA number of bytes of 2. Absolute TUSER width limit is 4096 bits wide.
+ * Reduced warnings in synthesis and simulation
+
+2013.2:
+ * Version 1.0 (Rev. 1)
+ * Architecture support updated
+
+2013.1:
+ * Version 1.0
+ * Native Vivado Release
+ * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
+
+(c) Copyright 2012 - 2018 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_dwidth_converter_v1_1_vl_rfs.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_dwidth_converter_v1_1_vl_rfs.v
new file mode 100755
index 0000000000000000000000000000000000000000..cc0642eda603f420dafc4089e5a7c66dba2106d8
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_dwidth_converter_v1_1_vl_rfs.v
@@ -0,0 +1,1172 @@
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// axisc_downsizer
+// Convert from SI data width > MI datawidth.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_dwidth_converter_v1_1_16_axisc_downsizer #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_S_AXIS_TDATA_WIDTH = 96,
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ parameter integer C_AXIS_TID_WIDTH = 1,
+ parameter integer C_AXIS_TDEST_WIDTH = 1,
+ parameter integer C_S_AXIS_TUSER_WIDTH = 3,
+ parameter integer C_M_AXIS_TUSER_WIDTH = 1,
+ parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF ,
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ parameter integer C_RATIO = 3 // Should always be C_RATIO:1 (downsizer)
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // System Signals
+ input wire ACLK,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire S_AXIS_TVALID,
+ output wire S_AXIS_TREADY,
+ input wire [C_S_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TSTRB,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TKEEP,
+ input wire S_AXIS_TLAST,
+ input wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID,
+ input wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST,
+ input wire [C_S_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER,
+
+ // Master side
+ output wire M_AXIS_TVALID,
+ input wire M_AXIS_TREADY,
+ output wire [C_M_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TSTRB,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TKEEP,
+ output wire M_AXIS_TLAST,
+ output wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID,
+ output wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST,
+ output wire [C_M_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_S_AXIS_TSTRB_WIDTH = C_S_AXIS_TDATA_WIDTH/8;
+localparam P_M_AXIS_TSTRB_WIDTH = C_M_AXIS_TDATA_WIDTH/8;
+localparam P_RATIO_WIDTH = f_clogb2(C_RATIO);
+// State Machine possible states.
+localparam SM_RESET = 3'b000;
+localparam SM_IDLE = 3'b001;
+localparam SM_ACTIVE = 3'b010;
+localparam SM_END = 3'b011;
+localparam SM_END_TO_ACTIVE = 3'b110;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+(* fsm_encoding = "none" *) reg [2:0] state = SM_RESET;
+
+wire [C_RATIO-1:0] is_null;
+wire [C_RATIO-1:0] r0_is_end;
+
+wire [C_M_AXIS_TDATA_WIDTH-1:0] data_out;
+wire [P_M_AXIS_TSTRB_WIDTH-1:0] strb_out;
+wire [P_M_AXIS_TSTRB_WIDTH-1:0] keep_out;
+wire last_out;
+wire [C_AXIS_TID_WIDTH-1:0] id_out;
+wire [C_AXIS_TDEST_WIDTH-1:0] dest_out;
+wire [C_M_AXIS_TUSER_WIDTH-1:0] user_out;
+
+reg [C_S_AXIS_TDATA_WIDTH-1:0] r0_data;
+reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_strb;
+reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_keep;
+reg r0_last;
+reg [C_AXIS_TID_WIDTH-1:0] r0_id;
+reg [C_AXIS_TDEST_WIDTH-1:0] r0_dest;
+reg [C_S_AXIS_TUSER_WIDTH-1:0] r0_user;
+reg [C_RATIO-1:0] r0_is_null_r = {C_RATIO{1'b0}};
+
+wire r0_load;
+
+reg [C_M_AXIS_TDATA_WIDTH-1:0] r1_data;
+reg [P_M_AXIS_TSTRB_WIDTH-1:0] r1_strb;
+reg [P_M_AXIS_TSTRB_WIDTH-1:0] r1_keep;
+reg r1_last;
+reg [C_AXIS_TID_WIDTH-1:0] r1_id;
+reg [C_AXIS_TDEST_WIDTH-1:0] r1_dest;
+reg [C_M_AXIS_TUSER_WIDTH-1:0] r1_user;
+
+wire r1_load;
+
+reg [P_RATIO_WIDTH-1:0] r0_out_sel_r = {P_RATIO_WIDTH{1'b0}};
+wire [P_RATIO_WIDTH-1:0] r0_out_sel_ns;
+wire sel_adv;
+reg [P_RATIO_WIDTH-1:0] r0_out_sel_next_r = {P_RATIO_WIDTH{1'b0}} + 1'b1;
+wire [P_RATIO_WIDTH-1:0] r0_out_sel_next_ns;
+reg xfer_is_end;
+reg next_xfer_is_end;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+// S Ready/M Valid outputs are encoded in the current state.
+assign S_AXIS_TREADY = state[0];
+assign M_AXIS_TVALID = state[1];
+
+// State machine controls M_AXIS_TVALID and S_AXIS_TREADY, and loading
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ state <= SM_RESET;
+ end else if (ACLKEN) begin
+ case (state)
+ SM_RESET: begin
+ state <= SM_IDLE;
+ end
+
+ // No transactions
+ SM_IDLE: begin
+ if (S_AXIS_TVALID) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_IDLE;
+ end
+ end
+
+ // Active entry in holding register r0
+ SM_ACTIVE: begin
+ if (M_AXIS_TREADY & r0_is_end[0]) begin
+ state <= SM_IDLE;
+ end
+ else if (M_AXIS_TREADY & next_xfer_is_end) begin
+ state <= SM_END;
+ end
+ else begin
+ state <= SM_ACTIVE;
+ end
+ end
+
+ // Entry in last transfer register r1.
+ SM_END: begin
+ if (M_AXIS_TREADY & S_AXIS_TVALID) begin
+ state <= SM_ACTIVE;
+ end
+ else if (M_AXIS_TREADY & ~S_AXIS_TVALID) begin
+ state <= SM_IDLE;
+ end
+ else if (~M_AXIS_TREADY & S_AXIS_TVALID) begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ else begin
+ state <= SM_END;
+ end
+ end
+
+ SM_END_TO_ACTIVE: begin
+ if (M_AXIS_TREADY) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ end
+
+ default: begin
+ state <= SM_IDLE;
+ end
+
+ endcase // case (state)
+ end
+end
+
+// Algorithm to figure out which beat is the last non-null transfer. Split into 2 steps.
+// 1) Figuring out which output transfers are null before storing in r0.
+// (cycle steal to reduce critical path).
+// 2) For transfer X, if transfer X+1 to transfer C_RATIO-1 is null, then transfer
+// X is the new END transfer for the split. Transfer C_RATIO-1 is always marked
+// as END.
+genvar i;
+generate
+ if (C_AXIS_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep_is_enabled
+ for (i = 0; i < C_RATIO-1; i = i + 1) begin : gen_is_null
+ // 1)
+ assign is_null[i] = ~(|S_AXIS_TKEEP[i*P_M_AXIS_TSTRB_WIDTH +: P_M_AXIS_TSTRB_WIDTH]);
+ // 2)
+ assign r0_is_end[i] = (&r0_is_null_r[C_RATIO-1:i+1]);
+ end
+ assign is_null[C_RATIO-1] = ~(|S_AXIS_TKEEP[(C_RATIO-1)*P_M_AXIS_TSTRB_WIDTH +: P_M_AXIS_TSTRB_WIDTH]);
+ assign r0_is_end[C_RATIO-1] = 1'b1;
+ end
+ else begin : gen_tkeep_is_disabled
+ assign is_null = {C_RATIO{1'b0}};
+ assign r0_is_end = {1'b1, {C_RATIO-1{1'b0}}};
+ end
+endgenerate
+
+assign M_AXIS_TDATA = data_out[0+:C_M_AXIS_TDATA_WIDTH];
+assign M_AXIS_TSTRB = strb_out[0+:P_M_AXIS_TSTRB_WIDTH];
+assign M_AXIS_TKEEP = keep_out[0+:P_M_AXIS_TSTRB_WIDTH];
+assign M_AXIS_TLAST = last_out;
+assign M_AXIS_TID = id_out[0+:C_AXIS_TID_WIDTH];
+assign M_AXIS_TDEST = dest_out[0+:C_AXIS_TDEST_WIDTH];
+assign M_AXIS_TUSER = user_out[0+:C_M_AXIS_TUSER_WIDTH];
+
+// Select data output by shifting data right, upper most datum is always from r1
+assign data_out = {r1_data, r0_data[0+:C_M_AXIS_TDATA_WIDTH*(C_RATIO-1)]} >> (C_M_AXIS_TDATA_WIDTH*r0_out_sel_r);
+assign strb_out = {r1_strb, r0_strb[0+:P_M_AXIS_TSTRB_WIDTH*(C_RATIO-1)]} >> (P_M_AXIS_TSTRB_WIDTH*r0_out_sel_r);
+assign keep_out = {r1_keep, r0_keep[0+:P_M_AXIS_TSTRB_WIDTH*(C_RATIO-1)]} >> (P_M_AXIS_TSTRB_WIDTH*r0_out_sel_r);
+assign last_out = (state == SM_END || state == SM_END_TO_ACTIVE) ? r1_last : r0_last & r0_is_end[0];
+assign id_out = (state == SM_END || state == SM_END_TO_ACTIVE) ? r1_id : r0_id;
+assign dest_out = (state == SM_END || state == SM_END_TO_ACTIVE) ? r1_dest : r0_dest;
+assign user_out = {r1_user, r0_user[0+:C_M_AXIS_TUSER_WIDTH*(C_RATIO-1)]} >> (C_M_AXIS_TUSER_WIDTH*r0_out_sel_r);
+
+// First register stores the incoming transfer.
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ r0_data <= r0_load ? S_AXIS_TDATA : r0_data;
+ r0_strb <= r0_load ? S_AXIS_TSTRB : r0_strb;
+ r0_keep <= r0_load ? S_AXIS_TKEEP : r0_keep;
+ r0_last <= r0_load ? S_AXIS_TLAST : r0_last;
+ r0_id <= r0_load ? S_AXIS_TID : r0_id ;
+ r0_dest <= r0_load ? S_AXIS_TDEST : r0_dest;
+ r0_user <= r0_load ? S_AXIS_TUSER : r0_user;
+ end
+end
+
+// r0_is_null_r must always be set to known values to avoid x propagations.
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ r0_is_null_r <= {C_RATIO{1'b0}};
+ end
+ else if (ACLKEN) begin
+ r0_is_null_r <= r0_load & S_AXIS_TVALID ? is_null : r0_is_null_r;
+ end
+end
+
+assign r0_load = (state == SM_IDLE) || (state == SM_END);
+// Second register only stores a single slice of r0.
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ r1_data <= r1_load ? r0_data >> (C_M_AXIS_TDATA_WIDTH*r0_out_sel_next_r) : r1_data;
+ r1_strb <= r1_load ? r0_strb >> (P_M_AXIS_TSTRB_WIDTH*r0_out_sel_next_r) : r1_strb;
+ r1_keep <= r1_load ? r0_keep >> (P_M_AXIS_TSTRB_WIDTH*r0_out_sel_next_r) : r1_keep;
+ r1_last <= r1_load ? r0_last : r1_last;
+ r1_id <= r1_load ? r0_id : r1_id ;
+ r1_dest <= r1_load ? r0_dest : r1_dest;
+ r1_user <= r1_load ? r0_user >> (C_M_AXIS_TUSER_WIDTH*r0_out_sel_next_r) : r1_user;
+ end
+end
+
+assign r1_load = (state == SM_ACTIVE);
+
+// Counter to select which datum to send.
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ r0_out_sel_r <= {P_RATIO_WIDTH{1'b0}};
+ end else if (ACLKEN) begin
+ r0_out_sel_r <= r0_out_sel_ns;
+ end
+end
+
+assign r0_out_sel_ns = (xfer_is_end & sel_adv) || (state == SM_IDLE) ? {P_RATIO_WIDTH{1'b0}}
+ : next_xfer_is_end & sel_adv ? C_RATIO[P_RATIO_WIDTH-1:0]-1'b1
+ : sel_adv ? r0_out_sel_next_r : r0_out_sel_r;
+
+assign sel_adv = M_AXIS_TREADY;
+
+
+// Count ahead to the next value
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ r0_out_sel_next_r <= {P_RATIO_WIDTH{1'b0}} + 1'b1;
+ end else if (ACLKEN) begin
+ r0_out_sel_next_r <= r0_out_sel_next_ns;
+ end
+end
+
+assign r0_out_sel_next_ns = (xfer_is_end & sel_adv) || (state == SM_IDLE) ? {P_RATIO_WIDTH{1'b0}} + 1'b1
+ : ~next_xfer_is_end & sel_adv ? r0_out_sel_next_r + 1'b1
+ : r0_out_sel_next_r;
+
+always @(*) begin
+ xfer_is_end = r0_is_end[r0_out_sel_r];
+end
+
+always @(*) begin
+ next_xfer_is_end = r0_is_end[r0_out_sel_next_r];
+end
+
+endmodule // axisc_downsizer
+
+`default_nettype wire
+
+
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// axisc_downsizer
+// Convert from SI data width < MI datawidth.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_dwidth_converter_v1_1_16_axisc_upsizer #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32,
+ parameter integer C_M_AXIS_TDATA_WIDTH = 96,
+ parameter integer C_AXIS_TID_WIDTH = 1,
+ parameter integer C_AXIS_TDEST_WIDTH = 1,
+ parameter integer C_S_AXIS_TUSER_WIDTH = 1,
+ parameter integer C_M_AXIS_TUSER_WIDTH = 3,
+ parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF ,
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ parameter integer C_RATIO = 3 // Should always be 1:C_RATIO (upsizer)
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // System Signals
+ input wire ACLK,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire S_AXIS_TVALID,
+ output wire S_AXIS_TREADY,
+ input wire [C_S_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TSTRB,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TKEEP,
+ input wire S_AXIS_TLAST,
+ input wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID,
+ input wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST,
+ input wire [C_S_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER,
+
+ // Master side
+ output wire M_AXIS_TVALID,
+ input wire M_AXIS_TREADY,
+ output wire [C_M_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TSTRB,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TKEEP,
+ output wire M_AXIS_TLAST,
+ output wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID,
+ output wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST,
+ output wire [C_M_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_READY_EXIST = C_AXIS_SIGNAL_SET[0];
+localparam P_DATA_EXIST = C_AXIS_SIGNAL_SET[1];
+localparam P_STRB_EXIST = C_AXIS_SIGNAL_SET[2];
+localparam P_KEEP_EXIST = C_AXIS_SIGNAL_SET[3];
+localparam P_LAST_EXIST = C_AXIS_SIGNAL_SET[4];
+localparam P_ID_EXIST = C_AXIS_SIGNAL_SET[5];
+localparam P_DEST_EXIST = C_AXIS_SIGNAL_SET[6];
+localparam P_USER_EXIST = C_AXIS_SIGNAL_SET[7];
+localparam P_S_AXIS_TSTRB_WIDTH = C_S_AXIS_TDATA_WIDTH/8;
+localparam P_M_AXIS_TSTRB_WIDTH = C_M_AXIS_TDATA_WIDTH/8;
+
+// State Machine possible states. Bits 1:0 used to encode output signals.
+// /--- M_AXIS_TVALID state
+// |/-- S_AXIS_TREADY state
+localparam SM_RESET = 3'b000; // De-assert Ready during reset
+localparam SM_IDLE = 3'b001; // R0 reg is empty
+localparam SM_ACTIVE = 3'b101; // R0 reg is active
+localparam SM_END = 3'b011; // R0 reg is empty and ACC reg is active
+localparam SM_END_TO_ACTIVE = 3'b010; // R0/ACC reg are both active.
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+(* fsm_encoding = "none" *)
+reg [2:0] state = SM_RESET;
+
+reg [C_M_AXIS_TDATA_WIDTH-1:0] acc_data;
+reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_strb;
+reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_keep;
+reg acc_last;
+reg [C_AXIS_TID_WIDTH-1:0] acc_id;
+reg [C_AXIS_TDEST_WIDTH-1:0] acc_dest;
+reg [C_M_AXIS_TUSER_WIDTH-1:0] acc_user;
+
+wire [C_RATIO-1:0] acc_reg_en;
+reg [C_RATIO-1:0] r0_reg_sel = {{C_RATIO-1{1'b0}},1'b1}; // 1-hot
+wire next_xfer_is_end;
+
+reg [C_S_AXIS_TDATA_WIDTH-1:0] r0_data;
+reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_strb;
+reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_keep;
+reg r0_last;
+reg [C_AXIS_TID_WIDTH-1:0] r0_id;
+reg [C_AXIS_TDEST_WIDTH-1:0] r0_dest;
+reg [C_S_AXIS_TUSER_WIDTH-1:0] r0_user;
+
+wire id_match;
+wire dest_match;
+wire id_dest_mismatch;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// S Ready/M Valid outputs are encoded in the current state.
+assign S_AXIS_TREADY = state[0];
+assign M_AXIS_TVALID = state[1];
+
+// State machine controls M_AXIS_TVALID and S_AXIS_TREADY, and loading
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ state <= SM_RESET;
+ end else if (ACLKEN) begin
+ case (state)
+ SM_RESET: begin
+ state <= SM_IDLE;
+ end
+
+ SM_IDLE: begin
+ if (S_AXIS_TVALID & id_dest_mismatch & ~r0_reg_sel[0]) begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ else if (S_AXIS_TVALID & next_xfer_is_end) begin
+ state <= SM_END;
+ end
+ else if (S_AXIS_TVALID) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_IDLE;
+ end
+ end
+
+ SM_ACTIVE: begin
+ if (S_AXIS_TVALID & (id_dest_mismatch | r0_last)) begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ else if ((~S_AXIS_TVALID & r0_last) | (S_AXIS_TVALID & next_xfer_is_end)) begin
+ state <= SM_END;
+ end
+ else if (S_AXIS_TVALID & ~next_xfer_is_end) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_IDLE;
+ end
+ end
+
+ SM_END: begin
+ if (M_AXIS_TREADY & S_AXIS_TVALID) begin
+ state <= SM_ACTIVE;
+ end
+ else if ( ~M_AXIS_TREADY & S_AXIS_TVALID) begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ else if ( M_AXIS_TREADY & ~S_AXIS_TVALID) begin
+ state <= SM_IDLE;
+ end
+ else begin
+ state <= SM_END;
+ end
+ end
+
+ SM_END_TO_ACTIVE: begin
+ if (M_AXIS_TREADY) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ end
+
+ default: begin
+ state <= SM_IDLE;
+ end
+
+ endcase // case (state)
+ end
+end
+
+
+assign M_AXIS_TDATA = acc_data;
+assign M_AXIS_TSTRB = acc_strb;
+assign M_AXIS_TKEEP = acc_keep;
+assign M_AXIS_TUSER = acc_user;
+
+generate
+ genvar i;
+ // DATA/USER/STRB/KEEP accumulators
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[0] ? r0_data
+ : acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
+ acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[0] ? r0_user
+ : acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
+ acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_strb
+ : acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_keep
+ : acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ end
+ end
+ for (i = 1; i < C_RATIO-1; i = i + 1) begin : gen_data_accumulator
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[i] ? r0_data
+ : acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
+ acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[i] ? r0_user
+ : acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
+ acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
+ : acc_reg_en[i] ? r0_strb : acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
+ : acc_reg_en[i] ? r0_keep : acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ end
+ end
+ end
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
+ ? S_AXIS_TDATA : acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
+ acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
+ ? S_AXIS_TUSER : acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
+ acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE | state == SM_IDLE))
+ ? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
+ ? S_AXIS_TSTRB : acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE| state == SM_IDLE))
+ ? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
+ ? S_AXIS_TKEEP : acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ end
+ end
+
+endgenerate
+
+assign acc_reg_en = (state == SM_ACTIVE) ? r0_reg_sel : {C_RATIO{1'b0}};
+
+// Accumulator selector (1 hot left barrel shifter)
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ r0_reg_sel[0] <= 1'b1;
+ r0_reg_sel[1+:C_RATIO-1] <= {C_RATIO{1'b0}};
+ end else if (ACLKEN) begin
+ r0_reg_sel[0] <= M_AXIS_TVALID & M_AXIS_TREADY ? 1'b1
+ : (state == SM_ACTIVE) ? 1'b0 : r0_reg_sel[0];
+ r0_reg_sel[1+:C_RATIO-1] <= M_AXIS_TVALID & M_AXIS_TREADY ? {C_RATIO-1{1'b0}}
+ : (state == SM_ACTIVE) ? r0_reg_sel[0+:C_RATIO-1] : r0_reg_sel[1+:C_RATIO-1];
+ end
+end
+
+assign next_xfer_is_end = (r0_reg_sel[C_RATIO-2] && (state == SM_ACTIVE)) | r0_reg_sel[C_RATIO-1];
+
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ r0_data <= S_AXIS_TREADY ? S_AXIS_TDATA : r0_data;
+ r0_strb <= S_AXIS_TREADY ? S_AXIS_TSTRB : r0_strb;
+ r0_keep <= S_AXIS_TREADY ? S_AXIS_TKEEP : r0_keep;
+ r0_last <= (!P_LAST_EXIST) ? 1'b0 : S_AXIS_TREADY ? S_AXIS_TLAST : r0_last;
+ r0_id <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TID : r0_id;
+ r0_dest <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TDEST : r0_dest;
+ r0_user <= S_AXIS_TREADY ? S_AXIS_TUSER : r0_user;
+ end
+end
+
+assign M_AXIS_TLAST = acc_last;
+
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_last <= (state == SM_END | state == SM_END_TO_ACTIVE) ? acc_last :
+ (state == SM_ACTIVE & r0_last ) ? 1'b1 :
+ (id_dest_mismatch & (state == SM_IDLE)) ? 1'b0 :
+ (id_dest_mismatch & (state == SM_ACTIVE)) ? r0_last :
+ S_AXIS_TLAST;
+ end
+end
+
+assign M_AXIS_TID = acc_id;
+assign M_AXIS_TDEST = acc_dest;
+
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_id <= acc_reg_en[0] ? r0_id : acc_id;
+ acc_dest <= acc_reg_en[0] ? r0_dest : acc_dest;
+ end
+end
+
+assign id_match = P_ID_EXIST ? (S_AXIS_TID == r0_id) : 1'b1;
+assign dest_match = P_DEST_EXIST ? (S_AXIS_TDEST == r0_dest) : 1'b1;
+
+assign id_dest_mismatch = (~id_match | ~dest_match) ? 1'b1 : 1'b0;
+
+endmodule // axisc_upsizer
+
+`default_nettype wire
+
+
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// axis_dwidth_converter
+// Converts data when C_S_AXIS_TDATA_WIDTH != C_M_AXIS_TDATA_WIDTH.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_dwidth_converter
+// register_slice (instantiated with upsizer)
+// axisc_upsizer
+// axisc_downsizer
+// register_slice (instantiated with downsizer)
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_dwidth_converter_v1_1_16_axis_dwidth_converter #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter C_FAMILY = "virtex7",
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32,
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ parameter integer C_AXIS_TID_WIDTH = 1,
+ parameter integer C_AXIS_TDEST_WIDTH = 1,
+ parameter integer C_S_AXIS_TUSER_WIDTH = 1,
+ parameter integer C_M_AXIS_TUSER_WIDTH = 1,
+ // Ratio of C_S_AXIS_TDATA_WIDTH : C_M_AXIS_TDATA_WIDTH must be the same as
+ // the ratio of C_S_AXIS_TUSER_WIDTH : C_M_AXIS_TUSER_WIDTH if USER signals are present.
+ parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present (Required)
+ // [1] => TDATA present (Required, used to calculate ratios)
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present (Required if TLAST, TID,
+ // TDEST present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // System Signals
+ input wire aclk,
+ input wire aresetn,
+ input wire aclken,
+
+ // Slave side
+ input wire s_axis_tvalid,
+ output wire s_axis_tready,
+ input wire [C_S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep,
+ input wire s_axis_tlast,
+ input wire [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
+ input wire [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
+ input wire [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
+
+ // Master side
+ output wire m_axis_tvalid,
+ input wire m_axis_tready,
+ output wire [C_M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep,
+ output wire m_axis_tlast,
+ output wire [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
+ output wire [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
+ output wire [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+// TKEEP required if TID/TLAST/TDEST signals enabled
+localparam [31:0] P_SS_TKEEP_REQUIRED = (C_AXIS_SIGNAL_SET & (G_MASK_SS_TID | G_MASK_SS_TDEST | G_MASK_SS_TLAST))
+ ? G_MASK_SS_TKEEP : 32'h0;
+// TREADY/TDATA must always be present
+localparam [31:0] P_AXIS_SIGNAL_SET = C_AXIS_SIGNAL_SET | G_MASK_SS_TREADY | G_MASK_SS_TDATA | P_SS_TKEEP_REQUIRED;
+localparam P_S_RATIO = f_lcm(C_S_AXIS_TDATA_WIDTH, C_M_AXIS_TDATA_WIDTH) / C_S_AXIS_TDATA_WIDTH;
+localparam P_M_RATIO = f_lcm(C_S_AXIS_TDATA_WIDTH, C_M_AXIS_TDATA_WIDTH) / C_M_AXIS_TDATA_WIDTH;
+localparam P_D2_TDATA_WIDTH = C_S_AXIS_TDATA_WIDTH * P_S_RATIO;
+// To protect against bad TUSER M/S ratios when not using TUSER, base all
+// TUSER widths off of the calculated ratios and the slave tuser input width.
+localparam P_D1_TUSER_WIDTH = C_AXIS_SIGNAL_SET[G_INDX_SS_TUSER] ? C_S_AXIS_TUSER_WIDTH : C_S_AXIS_TDATA_WIDTH/8;
+localparam P_D2_TUSER_WIDTH = P_D1_TUSER_WIDTH * P_S_RATIO;
+localparam P_D3_TUSER_WIDTH = P_D2_TUSER_WIDTH / P_M_RATIO;
+
+localparam P_D1_REG_CONFIG = 0; // Disable
+localparam P_D3_REG_CONFIG = 0; // Disable
+
+////////////////////////////////////////////////////////////////////////////////
+// DRCs
+////////////////////////////////////////////////////////////////////////////////
+// synthesis translate_off
+integer retval;
+integer retval_all;
+initial
+begin : DRC
+ retval_all = 0;
+ t_check_tdata_width(C_S_AXIS_TDATA_WIDTH, "C_S_AXIS_TDATA_WIDTH", "axis_dwidth_converter", G_TASK_SEVERITY_ERR, retval);
+ retval_all = retval_all | retval;
+
+ t_check_tdata_width(C_M_AXIS_TDATA_WIDTH, "C_M_AXIS_TDATA_WIDTH", "axis_dwidth_converter", G_TASK_SEVERITY_ERR, retval);
+ retval_all = retval_all | retval;
+ if (C_AXIS_SIGNAL_SET[G_INDX_SS_TUSER]) begin
+ t_check_tuser_width (
+ C_S_AXIS_TUSER_WIDTH, "C_S_AXIS_TUSER_WIDTH" ,
+ C_S_AXIS_TDATA_WIDTH, "C_S_AXIS_TDATA_WIDTH" ,
+ "axis_dwidth_converter", G_TASK_SEVERITY_ERR ,
+ retval
+ );
+ retval_all = retval_all | retval;
+ t_check_tuser_width(
+ C_M_AXIS_TUSER_WIDTH, "C_M_AXIS_TUSER_WIDTH",
+ C_M_AXIS_TDATA_WIDTH, "C_M_AXIS_TDATA_WIDTH",
+ "axis_dwidth_converter", G_TASK_SEVERITY_ERR,
+ retval
+ );
+ retval_all = retval_all | retval;
+ end
+ else begin
+ // No check
+ end
+ if (retval_all > 0) begin
+ $stop;
+ end else begin
+ // Do nothing
+ end
+
+
+end
+// synthesis translate_on
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+reg areset_r = 1'b0;
+
+// Tie-offs for required signals if not present on inputs
+wire tready_in;
+wire [C_S_AXIS_TDATA_WIDTH-1:0] tdata_in;
+wire [C_S_AXIS_TDATA_WIDTH/8-1:0] tkeep_in;
+wire [P_D1_TUSER_WIDTH-1:0] tuser_in;
+
+// Output of first register stage
+wire d1_valid;
+wire d1_ready;
+wire [C_S_AXIS_TDATA_WIDTH-1:0] d1_data;
+wire [C_S_AXIS_TDATA_WIDTH/8-1:0] d1_strb;
+wire [C_S_AXIS_TDATA_WIDTH/8-1:0] d1_keep;
+wire d1_last;
+wire [C_AXIS_TID_WIDTH-1:0] d1_id;
+wire [C_AXIS_TDEST_WIDTH-1:0] d1_dest;
+wire [P_D1_TUSER_WIDTH-1:0] d1_user;
+
+// Output of upsizer stage
+wire d2_valid;
+wire d2_ready;
+wire [P_D2_TDATA_WIDTH-1:0] d2_data;
+wire [P_D2_TDATA_WIDTH/8-1:0] d2_strb;
+wire [P_D2_TDATA_WIDTH/8-1:0] d2_keep;
+wire d2_last;
+wire [C_AXIS_TID_WIDTH-1:0] d2_id;
+wire [C_AXIS_TDEST_WIDTH-1:0] d2_dest;
+wire [P_D2_TUSER_WIDTH-1:0] d2_user;
+
+// Output of downsizer stage
+wire d3_valid;
+wire d3_ready;
+wire [C_M_AXIS_TDATA_WIDTH-1:0] d3_data;
+wire [C_M_AXIS_TDATA_WIDTH/8-1:0] d3_strb;
+wire [C_M_AXIS_TDATA_WIDTH/8-1:0] d3_keep;
+wire d3_last;
+wire [C_AXIS_TID_WIDTH-1:0] d3_id;
+wire [C_AXIS_TDEST_WIDTH-1:0] d3_dest;
+wire [P_D3_TUSER_WIDTH-1:0] d3_user;
+wire [P_D3_TUSER_WIDTH-1:0] m_axis_tuser_out;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+always @(posedge aclk) begin
+ areset_r <= ~aresetn;
+end
+
+// Tie-offs for required signals if not present on inputs
+assign tready_in = C_AXIS_SIGNAL_SET[G_INDX_SS_TREADY] ? m_axis_tready : 1'b1;
+assign tdata_in = C_AXIS_SIGNAL_SET[G_INDX_SS_TDATA] ? s_axis_tdata : {C_S_AXIS_TDATA_WIDTH{1'b0}};
+assign tkeep_in = C_AXIS_SIGNAL_SET[G_INDX_SS_TKEEP] ? s_axis_tkeep : {(C_S_AXIS_TDATA_WIDTH/8){1'b1}};
+assign tuser_in = C_AXIS_SIGNAL_SET[G_INDX_SS_TUSER] ? s_axis_tuser : {P_D1_TUSER_WIDTH{1'b1}};
+
+axis_register_slice_v1_1_17_axis_register_slice #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) ,
+ .C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_AXIS_TUSER_WIDTH ( P_D1_TUSER_WIDTH ) ,
+ .C_AXIS_SIGNAL_SET ( P_AXIS_SIGNAL_SET ) ,
+ .C_REG_CONFIG ( P_D1_REG_CONFIG )
+)
+axis_register_slice_0
+(
+ .aclk ( aclk ) ,
+ .aclk2x ( 1'b1 ) ,
+ .aclken ( aclken ) ,
+ .aresetn ( aresetn ) ,
+ .s_axis_tvalid ( s_axis_tvalid ) ,
+ .s_axis_tready ( s_axis_tready ) ,
+ .s_axis_tdata ( tdata_in ) ,
+ .s_axis_tstrb ( s_axis_tstrb ) ,
+ .s_axis_tkeep ( tkeep_in ) ,
+ .s_axis_tlast ( s_axis_tlast ) ,
+ .s_axis_tid ( s_axis_tid ) ,
+ .s_axis_tdest ( s_axis_tdest ) ,
+ .s_axis_tuser ( tuser_in ) ,
+ .m_axis_tvalid ( d1_valid ) ,
+ .m_axis_tready ( d1_ready ) ,
+ .m_axis_tdata ( d1_data ) ,
+ .m_axis_tstrb ( d1_strb ) ,
+ .m_axis_tkeep ( d1_keep ) ,
+ .m_axis_tlast ( d1_last ) ,
+ .m_axis_tid ( d1_id ) ,
+ .m_axis_tdest ( d1_dest ) ,
+ .m_axis_tuser ( d1_user )
+);
+
+
+generate
+ if (P_S_RATIO > 1) begin : gen_upsizer_conversion
+ axis_dwidth_converter_v1_1_16_axisc_upsizer #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_S_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) ,
+ .C_M_AXIS_TDATA_WIDTH ( P_D2_TDATA_WIDTH ) ,
+ .C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_S_AXIS_TUSER_WIDTH ( P_D1_TUSER_WIDTH ) ,
+ .C_M_AXIS_TUSER_WIDTH ( P_D2_TUSER_WIDTH ) ,
+ .C_AXIS_SIGNAL_SET ( P_AXIS_SIGNAL_SET ) ,
+ .C_RATIO ( P_S_RATIO )
+ )
+ axisc_upsizer_0 (
+ .ACLK ( aclk ) ,
+ .ARESET ( areset_r ) ,
+ .ACLKEN ( aclken ) ,
+ .S_AXIS_TVALID ( d1_valid ) ,
+ .S_AXIS_TREADY ( d1_ready ) ,
+ .S_AXIS_TDATA ( d1_data ) ,
+ .S_AXIS_TSTRB ( d1_strb ) ,
+ .S_AXIS_TKEEP ( d1_keep ) ,
+ .S_AXIS_TLAST ( d1_last ) ,
+ .S_AXIS_TID ( d1_id ) ,
+ .S_AXIS_TDEST ( d1_dest ) ,
+ .S_AXIS_TUSER ( d1_user ) ,
+ .M_AXIS_TVALID ( d2_valid ) ,
+ .M_AXIS_TREADY ( d2_ready ) ,
+ .M_AXIS_TDATA ( d2_data ) ,
+ .M_AXIS_TSTRB ( d2_strb ) ,
+ .M_AXIS_TKEEP ( d2_keep ) ,
+ .M_AXIS_TLAST ( d2_last ) ,
+ .M_AXIS_TID ( d2_id ) ,
+ .M_AXIS_TDEST ( d2_dest ) ,
+ .M_AXIS_TUSER ( d2_user )
+ );
+ end
+ else begin : gen_no_upsizer_passthru
+ assign d2_valid = d1_valid;
+ assign d1_ready = d2_ready;
+ assign d2_data = d1_data;
+ assign d2_strb = d1_strb;
+ assign d2_keep = d1_keep;
+ assign d2_last = d1_last;
+ assign d2_id = d1_id;
+ assign d2_dest = d1_dest;
+ assign d2_user = d1_user;
+ end
+ if (P_M_RATIO > 1) begin : gen_downsizer_conversion
+ axis_dwidth_converter_v1_1_16_axisc_downsizer #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_S_AXIS_TDATA_WIDTH ( P_D2_TDATA_WIDTH ) ,
+ .C_M_AXIS_TDATA_WIDTH ( C_M_AXIS_TDATA_WIDTH ) ,
+ .C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_S_AXIS_TUSER_WIDTH ( P_D2_TUSER_WIDTH ) ,
+ .C_M_AXIS_TUSER_WIDTH ( P_D3_TUSER_WIDTH ) ,
+ .C_AXIS_SIGNAL_SET ( P_AXIS_SIGNAL_SET ) ,
+ .C_RATIO ( P_M_RATIO )
+ )
+ axisc_downsizer_0 (
+ .ACLK ( aclk ) ,
+ .ARESET ( areset_r ) ,
+ .ACLKEN ( aclken ) ,
+ .S_AXIS_TVALID ( d2_valid ) ,
+ .S_AXIS_TREADY ( d2_ready ) ,
+ .S_AXIS_TDATA ( d2_data ) ,
+ .S_AXIS_TSTRB ( d2_strb ) ,
+ .S_AXIS_TKEEP ( d2_keep ) ,
+ .S_AXIS_TLAST ( d2_last ) ,
+ .S_AXIS_TID ( d2_id ) ,
+ .S_AXIS_TDEST ( d2_dest ) ,
+ .S_AXIS_TUSER ( d2_user ) ,
+ .M_AXIS_TVALID ( d3_valid ) ,
+ .M_AXIS_TREADY ( d3_ready ) ,
+ .M_AXIS_TDATA ( d3_data ) ,
+ .M_AXIS_TSTRB ( d3_strb ) ,
+ .M_AXIS_TKEEP ( d3_keep ) ,
+ .M_AXIS_TLAST ( d3_last ) ,
+ .M_AXIS_TID ( d3_id ) ,
+ .M_AXIS_TDEST ( d3_dest ) ,
+ .M_AXIS_TUSER ( d3_user )
+ );
+ end
+ else begin : gen_no_downsizer_passthru
+ assign d3_valid = d2_valid;
+ assign d2_ready = d3_ready;
+ assign d3_data = d2_data;
+ assign d3_strb = d2_strb;
+ assign d3_keep = d2_keep;
+ assign d3_last = d2_last;
+ assign d3_id = d2_id;
+ assign d3_dest = d2_dest;
+ assign d3_user = d2_user;
+ end
+endgenerate
+
+axis_register_slice_v1_1_17_axis_register_slice #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_AXIS_TDATA_WIDTH ( C_M_AXIS_TDATA_WIDTH ) ,
+ .C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_AXIS_TUSER_WIDTH ( P_D3_TUSER_WIDTH ) ,
+ .C_AXIS_SIGNAL_SET ( P_AXIS_SIGNAL_SET ) ,
+ .C_REG_CONFIG ( P_D3_REG_CONFIG )
+)
+axis_register_slice_1
+(
+ .aclk ( aclk ) ,
+ .aclk2x ( 1'b1 ) ,
+ .aclken ( aclken ) ,
+ .aresetn ( aresetn ) ,
+ .s_axis_tvalid ( d3_valid ) ,
+ .s_axis_tready ( d3_ready ) ,
+ .s_axis_tdata ( d3_data ) ,
+ .s_axis_tstrb ( d3_strb ) ,
+ .s_axis_tkeep ( d3_keep ) ,
+ .s_axis_tlast ( d3_last ) ,
+ .s_axis_tid ( d3_id ) ,
+ .s_axis_tdest ( d3_dest ) ,
+ .s_axis_tuser ( d3_user ) ,
+ .m_axis_tvalid ( m_axis_tvalid ) ,
+ .m_axis_tready ( tready_in ) ,
+ .m_axis_tdata ( m_axis_tdata ) ,
+ .m_axis_tstrb ( m_axis_tstrb ) ,
+ .m_axis_tkeep ( m_axis_tkeep ) ,
+ .m_axis_tlast ( m_axis_tlast ) ,
+ .m_axis_tid ( m_axis_tid ) ,
+ .m_axis_tdest ( m_axis_tdest ) ,
+ .m_axis_tuser ( m_axis_tuser_out )
+);
+
+assign m_axis_tuser = C_AXIS_SIGNAL_SET[G_INDX_SS_TUSER] ? m_axis_tuser_out[P_D3_TUSER_WIDTH-1:0]
+ : {C_M_AXIS_TUSER_WIDTH{1'bx}};
+
+endmodule // axis_dwidth_converter
+
+`default_nettype wire
+
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_infrastructure_v1_1_0.vh b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_infrastructure_v1_1_0.vh
new file mode 100755
index 0000000000000000000000000000000000000000..14d3524515efbc513cd40e85a11234164beb08ca
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_infrastructure_v1_1_0.vh
@@ -0,0 +1,337 @@
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+// Global Parameters:
+//
+// Functions:
+// f_clogb2
+// f_gcd
+// f_lcm
+// f_get_tdata_indx
+// f_get_tstrb_indx
+// f_get_tkeep_indx
+// f_get_tlast_indx
+// f_get_tid_indx
+// f_get_tdest_indx
+// f_get_tuser_indx
+// f_payload_width
+// Tasks:
+// t_display_tdata_error
+//--------------------------------------------------------------------------
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Global Parameters
+///////////////////////////////////////////////////////////////////////////////
+// Define Signal Set indices
+localparam G_INDX_SS_TREADY = 0;
+localparam G_INDX_SS_TDATA = 1;
+localparam G_INDX_SS_TSTRB = 2;
+localparam G_INDX_SS_TKEEP = 3;
+localparam G_INDX_SS_TLAST = 4;
+localparam G_INDX_SS_TID = 5;
+localparam G_INDX_SS_TDEST = 6;
+localparam G_INDX_SS_TUSER = 7;
+localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
+localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA;
+localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB;
+localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP;
+localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST;
+localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ;
+localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST;
+localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER;
+
+// Task DRC error levels
+localparam G_TASK_SEVERITY_ERR = 2;
+localparam G_TASK_SEVERITY_WARNING = 1;
+localparam G_TASK_SEVERITY_INFO = 0;
+
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Functions
+///////////////////////////////////////////////////////////////////////////////
+// ceiling logb2
+ function integer f_clogb2 (input integer size);
+ integer s;
+ begin
+ s = size;
+ s = s - 1;
+ for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
+ s = s >> 1;
+ end
+ endfunction // clogb2
+
+ // Calculates the Greatest Common Divisor between two integers using the
+ // euclidean algorithm.
+ function automatic integer f_gcd (
+ input integer a,
+ input integer b
+ );
+ begin : main
+ if (a == 0) begin
+ f_gcd = b;
+ end else if (b == 0) begin
+ f_gcd = a;
+ end else if (a > b) begin
+ f_gcd = f_gcd(a % b, b);
+ end else begin
+ f_gcd = f_gcd(a, b % a);
+ end
+ end
+ endfunction
+
+ // Calculates the Lowest Common Denominator between two integers
+ function integer f_lcm (
+ input integer a,
+ input integer b
+ );
+ begin : main
+ f_lcm = ( a / f_gcd(a, b)) * b;
+ end
+ endfunction
+
+ // Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tdata_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ f_get_tdata_indx = 0;
+ end
+ endfunction
+
+ // Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tstrb_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
+ // If TDATA exists, then add its width to its base to get the tstrb index
+ f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tkeep_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tlast_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tid_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tdest_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tuser_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
+ end
+ endfunction
+
+ // Payload is the sum of all the AXIS signals present except for
+ // TREADY/TVALID
+ function integer f_payload_width (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
+ f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
+ // Ensure that the return value is never less than 1
+ f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
+ end
+ endfunction
+
+ task t_check_tdata_width(
+ input integer data_width,
+ input [8*80-1:0] var_name,
+ input [8*80-1:0] inst_name,
+ input integer severity_lvl,
+ output integer ret_val
+ );
+ // Severity levels:
+ // 0 = INFO
+ // 1 = WARNING
+ // 2 = ERROR
+ begin : t_check_tdata_width
+ if (data_width%8 != 0) begin
+ // 000 1 2 3 4 5 6 7 8
+ // 012 0 0 0 0 0 0 0 0
+ if (severity_lvl >= 2) begin
+ $display("ERROR: %m::%s", inst_name);
+ end else if (severity_lvl == 1) begin
+ $display("WARNING: %m::%s", inst_name);
+ end else begin
+ $display("INFO: %m::%s", inst_name);
+ end
+ $display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
+ $display(" AXI4-Stream data width is only defined for byte multiples. See the ");
+ $display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
+ $display(" information.");
+ ret_val = 1;
+ end else begin
+ ret_val = 0;
+ end
+ end
+ endtask
+
+ task t_check_tuser_width(
+ input integer tuser_width,
+ input [8*80-1:0] tuser_name,
+ input integer tdata_width,
+ input [8*80-1:0] tdata_name,
+ input [8*80-1:0] inst_name,
+ input integer severity_lvl,
+ output integer ret_val
+ );
+ // Severity levels:
+ // 0 = INFO
+ // 1 = WARNING
+ // 2 = ERROR
+ begin : t_check_tuser_width
+ integer tdata_bytes;
+ tdata_bytes = tdata_width/8;
+ if ((tuser_width%tdata_bytes) != 0) begin
+ // 000 1 2 3 4 5 6 7 8
+ // 012 0 0 0 0 0 0 0 0
+ if (severity_lvl >= 2) begin
+ $display("ERROR: %m::%s", inst_name);
+ end else if (severity_lvl == 1) begin
+ $display("WARNING: %m::%s", inst_name);
+ end else begin
+ $display("INFO: %m::%s", inst_name);
+ end
+ $display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
+ $display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width);
+ $display(" TUSER width in this module is only defined when the TUSER is the");
+ $display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0");
+ $display(" Section 2.1, 2.3.3 and 2.8 for more information. ");
+ ret_val = 1;
+ end else begin
+ ret_val = 0;
+ end
+ end
+ endtask
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_infrastructure_v1_1_vl_rfs.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_infrastructure_v1_1_vl_rfs.v
new file mode 100755
index 0000000000000000000000000000000000000000..e44cf420621e47c17e00cae5f07e554fc7946430
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_infrastructure_v1_1_vl_rfs.v
@@ -0,0 +1,1324 @@
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//-----------------------------------------------------------------------------
+//
+// Description:
+// Optimized Mux using MUXF7/8.
+// Any mux ratio.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// mux_enc
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V
+`define AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_mux_enc #
+ (
+ parameter C_FAMILY = "rtl",
+ // FPGA Family. Current version: virtex6 or spartan6.
+ parameter integer C_RATIO = 4,
+ // Mux select ratio. Can be any binary value (>= 1)
+ parameter integer C_SEL_WIDTH = 2,
+ // Log2-ceiling of C_RATIO (>= 1)
+ parameter integer C_DATA_WIDTH = 1
+ // Data width for comparator (>= 1)
+ )
+ (
+ input wire [C_SEL_WIDTH-1:0] S,
+ input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
+ output wire [C_DATA_WIDTH-1:0] O,
+ input wire OE
+ );
+
+ wire [C_DATA_WIDTH-1:0] o_i;
+ genvar bit_cnt;
+
+ function [C_DATA_WIDTH-1:0] f_mux
+ (
+ input [C_SEL_WIDTH-1:0] s,
+ input [C_RATIO*C_DATA_WIDTH-1:0] a
+ );
+ integer i;
+ reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
+ begin
+ carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
+ for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
+ carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
+ carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
+ ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
+ end
+ f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
+ end
+ endfunction
+
+ function [C_DATA_WIDTH-1:0] f_mux4
+ (
+ input [1:0] s,
+ input [4*C_DATA_WIDTH-1:0] a
+ );
+ integer i;
+ reg [4*C_DATA_WIDTH-1:0] carry;
+ begin
+ carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
+ for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
+ carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
+ carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
+ ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
+ end
+ f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
+ end
+ endfunction
+
+ assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
+
+ generate
+ if ( C_RATIO < 2 ) begin : gen_bypass
+ assign o_i = A;
+ end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
+ assign o_i = f_mux(S, A);
+
+ end else begin : gen_fpga
+ wire [C_DATA_WIDTH-1:0] l;
+ wire [C_DATA_WIDTH-1:0] h;
+ wire [C_DATA_WIDTH-1:0] ll;
+ wire [C_DATA_WIDTH-1:0] lh;
+ wire [C_DATA_WIDTH-1:0] hl;
+ wire [C_DATA_WIDTH-1:0] hh;
+
+ case (C_RATIO)
+ 1, 5, 9, 13:
+ assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ 2, 6, 10, 14:
+ assign hh = S[0] ?
+ A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
+ 3, 7, 11, 15:
+ assign hh = S[1] ?
+ A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ (S[0] ?
+ A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
+ 4, 8, 12, 16:
+ assign hh = S[1] ?
+ (S[0] ?
+ A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
+ (S[0] ?
+ A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
+ 17:
+ assign hh = S[1] ?
+ (S[0] ?
+ A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
+ (S[0] ?
+ A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
+ default:
+ assign hh = 0;
+ endcase
+
+ case (C_RATIO)
+ 5, 6, 7, 8: begin
+ assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+ for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
+ MUXF7 mux_s2_inst
+ (
+ .I0 (l[bit_cnt]),
+ .I1 (hh[bit_cnt]),
+ .S (S[2]),
+ .O (o_i[bit_cnt])
+ );
+ end
+ end
+
+ 9, 10, 11, 12: begin
+ assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+ assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
+ MUXF7 muxf_s2_low_inst
+ (
+ .I0 (ll[bit_cnt]),
+ .I1 (lh[bit_cnt]),
+ .S (S[2]),
+ .O (l[bit_cnt])
+ );
+ MUXF8 muxf_s3_inst
+ (
+ .I0 (l[bit_cnt]),
+ .I1 (hh[bit_cnt]),
+ .S (S[3]),
+ .O (o_i[bit_cnt])
+ );
+ end
+ end
+
+ 13,14,15,16: begin
+ assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+ assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
+ MUXF7 muxf_s2_low_inst
+ (
+ .I0 (ll[bit_cnt]),
+ .I1 (lh[bit_cnt]),
+ .S (S[2]),
+ .O (l[bit_cnt])
+ );
+ MUXF7 muxf_s2_hi_inst
+ (
+ .I0 (hl[bit_cnt]),
+ .I1 (hh[bit_cnt]),
+ .S (S[2]),
+ .O (h[bit_cnt])
+ );
+
+ MUXF8 muxf_s3_inst
+ (
+ .I0 (l[bit_cnt]),
+ .I1 (h[bit_cnt]),
+ .S (S[3]),
+ .O (o_i[bit_cnt])
+ );
+ end
+ end
+
+ 17: begin
+ assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
+ assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
+ MUXF7 muxf_s2_low_inst
+ (
+ .I0 (ll[bit_cnt]),
+ .I1 (lh[bit_cnt]),
+ .S (S[2]),
+ .O (l[bit_cnt])
+ );
+ MUXF7 muxf_s2_hi_inst
+ (
+ .I0 (hl[bit_cnt]),
+ .I1 (hh[bit_cnt]),
+ .S (S[2]),
+ .O (h[bit_cnt])
+ );
+ MUXF8 muxf_s3_inst
+ (
+ .I0 (l[bit_cnt]),
+ .I1 (h[bit_cnt]),
+ .S (S[3]),
+ .O (o_i[bit_cnt])
+ );
+ end
+ end
+
+ default: // If RATIO > 17, use RTL
+ assign o_i = f_mux(S, A);
+ endcase
+ end // gen_fpga
+ endgenerate
+endmodule
+
+`endif
+
+
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_infrastructure_v1_1_0_util_aclken_converter
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V
+`define AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_aclken_converter # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_PAYLOAD_WIDTH = 32,
+ parameter integer C_S_ACLKEN_CAN_TOGGLE = 1,
+ parameter integer C_M_ACLKEN_CAN_TOGGLE = 1
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // Slave side
+ input wire ACLK,
+ input wire ARESETN,
+
+ input wire S_ACLKEN,
+ input wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ input wire M_ACLKEN,
+ output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,
+ output wire M_VALID,
+ input wire M_READY
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+// State machine states
+localparam SM_NOT_READY = 3'b000;
+localparam SM_EMPTY = 3'b001;
+localparam SM_R0_NOT_READY = 3'b010;
+localparam SM_R0 = 3'b011;
+localparam SM_R1 = 3'b100;
+localparam SM_FULL = 3'b110;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire s_aclken_i;
+wire m_aclken_i;
+reg areset;
+
+reg [2:0] state = SM_NOT_READY;
+
+// r0 is the output register
+reg [C_PAYLOAD_WIDTH-1:0] r0;
+wire load_r0;
+wire load_r0_from_r1;
+
+// r1 is the overflow register
+reg [C_PAYLOAD_WIDTH-1:0] r1;
+wire load_r1;
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+assign s_aclken_i = C_S_ACLKEN_CAN_TOGGLE ? S_ACLKEN : 1'b1;
+assign m_aclken_i = C_M_ACLKEN_CAN_TOGGLE ? M_ACLKEN : 1'b1;
+
+always @(posedge ACLK) begin
+ areset <= ~ARESETN;
+end
+
+// Valid/Ready outputs encoded into state machine.
+assign S_READY = (state == SM_NOT_READY ) ? 1'b0 : state[0] ;
+assign M_VALID = (state == SM_NOT_READY ) ? 1'b0 : state[1];
+
+// State machine: Controls outputs and hold register state info
+always @(posedge ACLK) begin
+ if (areset) begin
+ state <= SM_NOT_READY;
+ end
+ else begin
+ case (state)
+ // De-assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied
+ SM_NOT_READY: begin
+ if (s_aclken_i) begin
+ state <= SM_EMPTY;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // Assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied
+ SM_EMPTY: begin
+ if (s_aclken_i & S_VALID & m_aclken_i) begin
+ state <= SM_R0;
+ end
+ else if (s_aclken_i & S_VALID & ~m_aclken_i) begin
+ state <= SM_R1;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // Assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied
+ SM_R0: begin
+ if ((m_aclken_i & M_READY) & ~(s_aclken_i & S_VALID)) begin
+ state <= SM_EMPTY;
+ end
+ else if (~(m_aclken_i & M_READY) & (s_aclken_i & S_VALID)) begin
+ state <= SM_FULL;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // De-assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied
+ SM_R0_NOT_READY: begin
+ if (s_aclken_i & m_aclken_i & M_READY) begin
+ state <= SM_EMPTY;
+ end
+ else if (~s_aclken_i & m_aclken_i & M_READY) begin
+ state <= SM_NOT_READY;
+ end
+ else if (s_aclken_i) begin
+ state <= SM_R0;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // De-assert s_ready, De-assert m_valid, R0 unoccupied, R1 occupied
+ SM_R1: begin
+ if (~s_aclken_i & m_aclken_i) begin
+ state <= SM_R0_NOT_READY;
+ end
+ else if (s_aclken_i & m_aclken_i) begin
+ state <= SM_R0;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // De-assert s_ready, De-assert m_valid, R0 occupied, R1 occupied
+ SM_FULL: begin
+ if (~s_aclken_i & m_aclken_i & M_READY) begin
+ state <= SM_R0_NOT_READY;
+ end
+ else if (s_aclken_i & m_aclken_i & M_READY) begin
+ state <= SM_R0;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ default: begin
+ state <= SM_NOT_READY;
+ end
+ endcase
+ end
+end
+
+assign M_PAYLOAD = r0;
+
+always @(posedge ACLK) begin
+ if (m_aclken_i) begin
+ r0 <= ~load_r0 ? r0 :
+ load_r0_from_r1 ? r1 :
+ S_PAYLOAD ;
+ end
+end
+
+assign load_r0 = (state == SM_EMPTY)
+ | (state == SM_R1)
+ | ((state == SM_R0) & M_READY)
+ | ((state == SM_FULL) & M_READY);
+
+assign load_r0_from_r1 = (state == SM_R1) | (state == SM_FULL);
+
+always @(posedge ACLK) begin
+ r1 <= ~load_r1 ? r1 : S_PAYLOAD;
+end
+
+assign load_r1 = (state == SM_EMPTY) | (state == SM_R0);
+
+
+endmodule // axis_infrastructure_v1_1_0_util_aclken_converter
+
+`default_nettype wire
+`endif
+
+
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+// Verilog-standard: Verilog 2001
+////////////////////////////////////////////////////////////
+//
+// Structure:
+// axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
+// axis_infrastructure_v1_1_0_util_axis2_vector
+// axis_infrastructure_v1_1_0_util_aclken_converter
+// axis_infrastructure_v1_1_0_util_vector2axis
+//
+////////////////////////////////////////////////////////////
+`ifndef axis_infrastructure_v1_1_0_UTIL_ACLKEN_CONVERTER_WRAPPER_V
+`define axis_infrastructure_v1_1_0_UTIL_ACLKEN_CONVERTER_WRAPPER_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_aclken_converter_wrapper # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_TDATA_WIDTH = 32,
+ parameter integer C_TID_WIDTH = 1,
+ parameter integer C_TDEST_WIDTH = 1,
+ parameter integer C_TUSER_WIDTH = 1,
+ parameter [31:0] C_SIGNAL_SET = 32'hFF,
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ parameter integer C_S_ACLKEN_CAN_TOGGLE = 1,
+ parameter integer C_M_ACLKEN_CAN_TOGGLE = 1
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // Slave side
+ input wire ACLK,
+ input wire ARESETN,
+ input wire S_ACLKEN,
+ input wire S_VALID,
+ output wire S_READY,
+ input wire [C_TDATA_WIDTH-1:0] S_TDATA,
+ input wire [C_TDATA_WIDTH/8-1:0] S_TSTRB,
+ input wire [C_TDATA_WIDTH/8-1:0] S_TKEEP,
+ input wire S_TLAST,
+ input wire [C_TID_WIDTH-1:0] S_TID,
+ input wire [C_TDEST_WIDTH-1:0] S_TDEST,
+ input wire [C_TUSER_WIDTH-1:0] S_TUSER,
+
+ input wire M_ACLKEN,
+ output wire M_VALID,
+ input wire M_READY,
+ output wire [C_TDATA_WIDTH-1:0] M_TDATA,
+ output wire [C_TDATA_WIDTH/8-1:0] M_TSTRB,
+ output wire [C_TDATA_WIDTH/8-1:0] M_TKEEP,
+ output wire M_TLAST,
+ output wire [C_TID_WIDTH-1:0] M_TID,
+ output wire [C_TDEST_WIDTH-1:0] M_TDEST,
+ output wire [C_TUSER_WIDTH-1:0] M_TUSER
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+localparam integer P_TPAYLOAD_WIDTH = f_payload_width(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire [P_TPAYLOAD_WIDTH-1:0] s_tpayload;
+wire [P_TPAYLOAD_WIDTH-1:0] m_tpayload;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+axis_infrastructure_v1_1_0_util_axis2vector #(
+ .C_TDATA_WIDTH ( C_TDATA_WIDTH ) ,
+ .C_TID_WIDTH ( C_TID_WIDTH ) ,
+ .C_TDEST_WIDTH ( C_TDEST_WIDTH ) ,
+ .C_TUSER_WIDTH ( C_TUSER_WIDTH ) ,
+ .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_SIGNAL_SET ( C_SIGNAL_SET )
+)
+util_axis2vector_0 (
+ .TDATA ( S_TDATA ) ,
+ .TSTRB ( S_TSTRB ) ,
+ .TKEEP ( S_TKEEP ) ,
+ .TLAST ( S_TLAST ) ,
+ .TID ( S_TID ) ,
+ .TDEST ( S_TDEST ) ,
+ .TUSER ( S_TUSER ) ,
+ .TPAYLOAD ( s_tpayload )
+);
+
+generate
+if (C_S_ACLKEN_CAN_TOGGLE | C_M_ACLKEN_CAN_TOGGLE) begin : gen_aclken_converter
+ axis_infrastructure_v1_1_0_util_aclken_converter #(
+ .C_PAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_S_ACLKEN_CAN_TOGGLE ( C_S_ACLKEN_CAN_TOGGLE ) ,
+ .C_M_ACLKEN_CAN_TOGGLE ( C_M_ACLKEN_CAN_TOGGLE )
+ )
+ s_util_aclken_converter_0 (
+ .ACLK ( ACLK ) ,
+ .ARESETN ( ARESETN ) ,
+ .S_ACLKEN ( S_ACLKEN ) ,
+ .S_PAYLOAD ( s_tpayload ) ,
+ .S_VALID ( S_VALID ) ,
+ .S_READY ( S_READY ) ,
+ .M_ACLKEN ( M_ACLKEN ) ,
+ .M_PAYLOAD ( m_tpayload ) ,
+ .M_VALID ( M_VALID ) ,
+ .M_READY ( M_READY )
+ );
+end
+else begin : gen_aclken_passthru
+ assign m_tpayload = s_tpayload;
+ assign M_VALID = S_VALID;
+ assign S_READY = M_READY;
+end
+endgenerate
+
+axis_infrastructure_v1_1_0_util_vector2axis #(
+ .C_TDATA_WIDTH ( C_TDATA_WIDTH ) ,
+ .C_TID_WIDTH ( C_TID_WIDTH ) ,
+ .C_TDEST_WIDTH ( C_TDEST_WIDTH ) ,
+ .C_TUSER_WIDTH ( C_TUSER_WIDTH ) ,
+ .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_SIGNAL_SET ( C_SIGNAL_SET )
+)
+util_vector2axis_0 (
+ .TPAYLOAD ( m_tpayload ) ,
+ .TDATA ( M_TDATA ) ,
+ .TSTRB ( M_TSTRB ) ,
+ .TKEEP ( M_TKEEP ) ,
+ .TLAST ( M_TLAST ) ,
+ .TID ( M_TID ) ,
+ .TDEST ( M_TDEST ) ,
+ .TUSER ( M_TUSER )
+);
+
+endmodule // axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
+
+`default_nettype wire
+`endif
+
+
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+// axis to vector
+// A generic module to merge all axis 'data' signals into one signal called payload.
+// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_infrastructure_v1_1_0_util_axis2vector
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
+`define AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_axis2vector #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_TDATA_WIDTH = 32,
+ parameter integer C_TID_WIDTH = 1,
+ parameter integer C_TDEST_WIDTH = 1,
+ parameter integer C_TUSER_WIDTH = 1,
+ parameter integer C_TPAYLOAD_WIDTH = 44,
+ parameter [31:0] C_SIGNAL_SET = 32'hFF
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // inputs
+ input wire [C_TDATA_WIDTH-1:0] TDATA,
+ input wire [C_TDATA_WIDTH/8-1:0] TSTRB,
+ input wire [C_TDATA_WIDTH/8-1:0] TKEEP,
+ input wire TLAST,
+ input wire [C_TID_WIDTH-1:0] TID,
+ input wire [C_TDEST_WIDTH-1:0] TDEST,
+ input wire [C_TUSER_WIDTH-1:0] TUSER,
+
+ // outputs
+ output wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+generate
+ if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
+ assign TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] = TDATA;
+ end else begin : no_gen_tdata
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
+ assign TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8] = TSTRB;
+ end else begin : no_gen_tstrb
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
+ assign TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8] = TKEEP;
+ end else begin : no_gen_tkeep
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
+ assign TPAYLOAD[P_TLAST_INDX+:1] = TLAST;
+ end else begin : no_gen_tlast
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
+ assign TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] = TID;
+ end else begin : no_gen_tid
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
+ assign TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] = TDEST;
+ end else begin : no_gen_tdest
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
+ assign TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] = TUSER;
+ end else begin : no_gen_tuser
+ // Do nothing
+ end
+endgenerate
+endmodule
+
+`default_nettype wire
+`endif
+
+
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+// axis to vector
+// A generic module to unmerge all axis 'data' signals from payload.
+// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_infrastructure_v1_1_0_util_vector2axis
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
+`define AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_vector2axis #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_TDATA_WIDTH = 32,
+ parameter integer C_TID_WIDTH = 1,
+ parameter integer C_TDEST_WIDTH = 1,
+ parameter integer C_TUSER_WIDTH = 1,
+ parameter integer C_TPAYLOAD_WIDTH = 44,
+ parameter [31:0] C_SIGNAL_SET = 32'hFF
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // outputs
+ input wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD,
+
+ // inputs
+ output wire [C_TDATA_WIDTH-1:0] TDATA,
+ output wire [C_TDATA_WIDTH/8-1:0] TSTRB,
+ output wire [C_TDATA_WIDTH/8-1:0] TKEEP,
+ output wire TLAST,
+ output wire [C_TID_WIDTH-1:0] TID,
+ output wire [C_TDEST_WIDTH-1:0] TDEST,
+ output wire [C_TUSER_WIDTH-1:0] TUSER
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+generate
+ if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
+ assign TDATA = TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] ;
+ end
+ else begin : no_gen_tdata
+ assign TDATA = {C_TDATA_WIDTH{1'b0}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
+ assign TSTRB = TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8];
+ end
+ else begin : no_gen_tstrb
+ assign TSTRB = {(C_TDATA_WIDTH/8){1'b0}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
+ assign TKEEP = TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8];
+ end
+ else begin : no_gen_tkeep
+ assign TKEEP = {(C_TDATA_WIDTH/8){1'b1}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
+ assign TLAST = TPAYLOAD[P_TLAST_INDX+:1] ;
+ end
+ else begin : no_gen_tlast
+ assign TLAST = 1'b0;
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
+ assign TID = TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] ;
+ end
+ else begin : no_gen_tid
+ assign TID = {C_TID_WIDTH{1'b0}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
+ assign TDEST = TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] ;
+ end
+ else begin : no_gen_tdest
+ assign TDEST = {C_TDEST_WIDTH{1'b0}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
+ assign TUSER = TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] ;
+ end
+ else begin : no_gen_tuser
+ assign TUSER = {C_TUSER_WIDTH{1'b0}};
+ end
+endgenerate
+endmodule
+
+`default_nettype wire
+`endif
+
+
+//*****************************************************************************
+// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+// Description
+// This module instantiates the clock synchronization logic. It passes the
+// incoming signal through two flops to ensure metastability.
+//
+//*****************************************************************************
+`timescale 1ps / 1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_clock_synchronizer # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_NUM_STAGES = 4
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ input wire clk,
+ input wire synch_in ,
+ output wire synch_out
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Local Parameters
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+xpm_cdc_single #(
+ .DEST_SYNC_FF ( C_NUM_STAGES ) ,
+ .SRC_INPUT_REG ( 0 ) ,
+ .SIM_ASSERT_CHK ( 0 )
+)
+inst_xpm_cdc_single (
+ .src_clk ( 1'b0 ) ,
+ .src_in ( synch_in ) ,
+ .dest_out ( synch_out ) ,
+ .dest_clk ( clk )
+);
+
+endmodule
+
+`default_nettype wire
+
+
+// (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axis_infrastructure_v1_1_0_cdc_handshake
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
+`default_nettype none
+
+module axis_infrastructure_v1_1_0_cdc_handshake #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_WIDTH = 32,
+ parameter integer C_NUM_SYNCHRONIZER_STAGES = 2
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ input wire from_clk,
+ input wire req,
+ output wire ack,
+ input wire [C_WIDTH-1:0] data_in,
+
+ input wire to_clk,
+ output wire data_valid,
+ output wire [C_WIDTH-1:0] data_out
+);
+
+/////////////////////////////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+///////////////////////////////////////////////////////////////////////////////
+xpm_cdc_handshake #(
+ .WIDTH ( C_WIDTH ) ,
+ .DEST_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) ,
+ .SRC_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) ,
+ .DEST_EXT_HSK ( 0 ) ,
+ .SIM_ASSERT_CHK ( 0 )
+)
+inst_xpm_cdc_handshake (
+ .src_in ( data_in ) ,
+ .src_send ( req ) ,
+ .src_rcv ( ack ) ,
+ .src_clk ( from_clk ) ,
+ .dest_out ( data_out ) ,
+ .dest_req ( data_valid ) ,
+ .dest_ack ( 1'b0 ) ,
+ .dest_clk ( to_clk )
+);
+
+endmodule // axis_infrastructure_v1_1_0_cdc_handshake
+
+`default_nettype wire
+
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_register_slice_v1_1_vl_rfs.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_register_slice_v1_1_vl_rfs.v
new file mode 100755
index 0000000000000000000000000000000000000000..93a196e91ffad2e74c6b60ec2572fc1554e32fe6
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/hdl/axis_register_slice_v1_1_vl_rfs.v
@@ -0,0 +1,2425 @@
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+module axis_register_slice_v1_1_17_tdm_sample (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ input wire slow_clk,
+ input wire fast_clk,
+ output wire sample_cycle
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+reg slow_clk_div2 = 1'b0;
+reg posedge_finder_first;
+reg posedge_finder_second;
+wire first_edge;
+wire second_edge;
+reg sample_cycle_d;
+(* shreg_extract = "no" *) reg sample_cycle_r;
+
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+ always @(posedge slow_clk) begin
+ slow_clk_div2 <= ~slow_clk_div2;
+ end
+
+ // Find matching rising edges by clocking slow_clk_div2 onto faster clock
+ always @(posedge fast_clk) begin
+ posedge_finder_first <= slow_clk_div2;
+ end
+ always @(posedge fast_clk) begin
+ posedge_finder_second <= ~slow_clk_div2;
+ end
+
+ assign first_edge = slow_clk_div2 & ~posedge_finder_first;
+ assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;
+
+ always @(*) begin
+ sample_cycle_d = first_edge | second_edge;
+ end
+
+ always @(posedge fast_clk) begin
+ sample_cycle_r <= sample_cycle_d;
+ end
+
+ assign sample_cycle = sample_cycle_r;
+
+endmodule // tdm_sample
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2010 - 2018 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+// Generic single-channel AXI pipeline register on forward and/or reverse signal path
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axic_register_slice_slr
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_multi_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_NUM_SLR_CROSSINGS = 0,
+ parameter integer C_PIPELINES_MASTER = 0,
+ parameter integer C_PIPELINES_SLAVE = 0,
+ parameter integer C_PIPELINES_MIDDLE = 0
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLKEN,
+ input wire ARESET,
+
+ // Slave side
+ input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
+ output wire M_VALID,
+ input wire M_READY
+ );
+
+ localparam integer P_MULTI_SLR = 15;
+ localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;
+ localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;
+ localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);
+
+ generate
+
+ if (C_NUM_SLR_CROSSINGS==0) begin : single_slr
+
+ axis_register_slice_v1_1_17_single_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_PIPELINES (C_PIPELINES_MASTER)
+ )
+ slr_master (
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+ .M_PAYLOAD_DATA (M_PAYLOAD_DATA),
+ .M_VALID (M_VALID),
+ .M_READY (M_READY)
+ );
+
+ end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr
+
+ wire [C_DATA_WIDTH-1:0] src_payload;
+ wire src_handshake;
+ wire src_reset;
+ wire src_ready;
+
+ axis_register_slice_v1_1_17_source_region_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES ( C_PIPELINES_MASTER) ,
+ .C_REG_CONFIG ( P_MULTI_SLR )
+ )
+ slr_master (
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+ .laguna_m_reset_out ( src_reset ) ,
+ .laguna_m_payload ( src_payload ) ,
+ .laguna_m_handshake ( src_handshake ) ,
+ .laguna_m_ready ( src_ready )
+ );
+
+ axis_register_slice_v1_1_17_dest_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( P_MULTI_SLR ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_SLAVE),
+ .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)
+ )
+ slr_slave (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( src_reset ) ,
+ .laguna_s_payload ( src_payload ) ,
+ .laguna_s_handshake ( src_handshake ) ,
+ .laguna_s_ready ( src_ready ) ,
+ .M_PAYLOAD_DATA (M_PAYLOAD_DATA),
+ .M_VALID (M_VALID),
+ .M_READY (M_READY)
+ );
+
+ end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr
+
+ wire [C_DATA_WIDTH-1:0] src_payload;
+ wire src_handshake;
+ wire src_ready;
+ wire src_reset;
+ wire [C_DATA_WIDTH-1:0] dest_payload;
+ wire dest_handshake;
+ wire dest_ready;
+ wire dest_reset;
+
+ axis_register_slice_v1_1_17_source_region_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_MASTER) ,
+ .C_REG_CONFIG ( P_MULTI_SLR )
+ )
+ slr_master (
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+ .laguna_m_reset_out ( src_reset ) ,
+ .laguna_m_payload ( src_payload ) ,
+ .laguna_m_handshake ( src_handshake ) ,
+ .laguna_m_ready ( src_ready )
+ );
+
+ axis_register_slice_v1_1_17_middle_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_PIPELINES (C_PIPELINES_MIDDLE),
+ .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)
+ )
+ slr_middle (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( src_reset ) ,
+ .laguna_s_payload ( src_payload ) ,
+ .laguna_s_handshake ( src_handshake ) ,
+ .laguna_s_ready ( src_ready ) ,
+ .laguna_m_reset_out ( dest_reset ) ,
+ .laguna_m_payload ( dest_payload ) ,
+ .laguna_m_handshake ( dest_handshake ) ,
+ .laguna_m_ready ( dest_ready )
+ );
+
+ axis_register_slice_v1_1_17_dest_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( P_MULTI_SLR ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_SLAVE),
+ .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)
+ )
+ slr_slave (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( dest_reset ) ,
+ .laguna_s_payload ( dest_payload ) ,
+ .laguna_s_handshake ( dest_handshake ) ,
+ .laguna_s_ready ( dest_ready ) ,
+ .M_PAYLOAD_DATA (M_PAYLOAD_DATA),
+ .M_VALID (M_VALID),
+ .M_READY (M_READY)
+ );
+
+ end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr
+
+ wire [C_DATA_WIDTH-1:0] src_payload;
+ wire src_handshake;
+ wire src_ready;
+ wire src_reset;
+ wire [C_DATA_WIDTH-1:0] mid_payload;
+ wire mid_handshake;
+ wire mid_ready;
+ wire mid_reset;
+ wire [C_DATA_WIDTH-1:0] dest_payload;
+ wire dest_handshake;
+ wire dest_ready;
+ wire dest_reset;
+
+ axis_register_slice_v1_1_17_source_region_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_MASTER) ,
+ .C_REG_CONFIG ( P_MULTI_SLR )
+ )
+ slr_master (
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+ .laguna_m_reset_out ( src_reset ) ,
+ .laguna_m_payload ( src_payload ) ,
+ .laguna_m_handshake ( src_handshake ) ,
+ .laguna_m_ready ( src_ready )
+ );
+
+ axis_register_slice_v1_1_17_middle_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_PIPELINES (C_PIPELINES_MIDDLE),
+ .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)
+ )
+ slr_middle_master (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( src_reset ) ,
+ .laguna_s_payload ( src_payload ) ,
+ .laguna_s_handshake ( src_handshake ) ,
+ .laguna_s_ready ( src_ready ) ,
+ .laguna_m_reset_out ( mid_reset ) ,
+ .laguna_m_payload ( mid_payload ) ,
+ .laguna_m_handshake ( mid_handshake ) ,
+ .laguna_m_ready ( mid_ready )
+ );
+
+ axis_register_slice_v1_1_17_middle_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_PIPELINES (C_PIPELINES_MIDDLE),
+ .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)
+ )
+ slr_middle_slave (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( mid_reset ) ,
+ .laguna_s_payload ( mid_payload ) ,
+ .laguna_s_handshake ( mid_handshake ) ,
+ .laguna_s_ready ( mid_ready ) ,
+ .laguna_m_reset_out ( dest_reset ) ,
+ .laguna_m_payload ( dest_payload ) ,
+ .laguna_m_handshake ( dest_handshake ) ,
+ .laguna_m_ready ( dest_ready )
+ );
+
+ axis_register_slice_v1_1_17_dest_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( P_MULTI_SLR ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_SLAVE),
+ .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)
+ )
+ slr_slave (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( dest_reset ) ,
+ .laguna_s_payload ( dest_payload ) ,
+ .laguna_s_handshake ( dest_handshake ) ,
+ .laguna_s_ready ( dest_ready ) ,
+ .M_PAYLOAD_DATA (M_PAYLOAD_DATA),
+ .M_VALID (M_VALID),
+ .M_READY (M_READY)
+ );
+
+ end
+
+endgenerate
+endmodule // multi_slr
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_middle_region_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_PIPELINES = 0,
+ parameter integer C_SOURCE_LATENCY = 1
+ // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLKEN,
+ input wire ARESET,
+
+ // Slave side
+ input wire laguna_s_reset_in,
+ input wire [C_DATA_WIDTH-1:0] laguna_s_payload,
+ input wire laguna_s_handshake,
+ output wire laguna_s_ready,
+
+ // Master side
+ output wire laguna_m_reset_out,
+ output wire [C_DATA_WIDTH-1:0] laguna_m_payload,
+ output wire laguna_m_handshake,
+ input wire laguna_m_ready
+ );
+
+ localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;
+ localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;
+
+ generate
+
+ (* keep="true" *) reg s_reset_dd = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_s_reset_in_d = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_m_reset_out_i = 1'b0;
+
+ assign laguna_m_reset_out = laguna_m_reset_out_i;
+
+ always @(posedge ACLK) begin
+ laguna_s_reset_in_d <= laguna_s_reset_in;
+ s_reset_dd <= laguna_s_reset_in_d;
+ laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;
+ end
+
+ wire ACLEAR;
+ assign ACLEAR = ARESET;
+
+ if (1) begin : common
+ (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;
+ (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;
+ wire laguna_s_handshake_q;
+ wire m_handshake_d;
+ wire laguna_m_handshake_q;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_m_ready_d = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_s_ready_i = 1'b0;
+ (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};
+ wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;
+ wire [(C_PIPELINES+2)-1:0] handshake_i;
+ genvar p;
+
+ assign laguna_m_payload = laguna_m_payload_i;
+ assign m_handshake_d = handshake_i[C_PIPELINES];
+ assign laguna_m_handshake = laguna_m_handshake_q;
+ assign laguna_s_ready = laguna_s_ready_i;
+
+ always @(posedge ACLK) begin
+ laguna_m_ready_d <= laguna_m_ready;
+ laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];
+ ready_d <= {ready_d, laguna_m_ready_d};
+ end
+
+ for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data;
+ wire payload_valid_d;
+ wire payload_valid_q;
+
+ assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;
+ assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;
+ assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];
+
+ always @(posedge ACLK) begin
+ if (p==0) begin
+ laguna_s_payload_d <= laguna_s_payload;
+ end else if (p==C_PIPELINES+1) begin
+ laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end else begin
+ payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ FDCE #(
+ .INIT(1'b0)
+ ) payload_valid_asyncclear_inst (
+ .Q (payload_valid_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (payload_valid_d)
+ );
+ end // loop p
+
+ (* USER_SLL_REG="true" *)
+ FDCE #(
+ .INIT(1'b0)
+ ) laguna_m_handshake_asyncclear_inst (
+ .Q (laguna_m_handshake_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (m_handshake_d)
+ );
+
+ (* USER_SLL_REG="true" *)
+ FDCE #(
+ .INIT(1'b0)
+ ) laguna_s_handshake_asyncclear_inst (
+ .Q (laguna_s_handshake_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (laguna_s_handshake)
+ );
+
+ end // gen_slr
+ endgenerate
+endmodule // middle_region_slr
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_source_region_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_REG_CONFIG = 12,
+ parameter integer C_PIPELINES = 0,
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_SLR_WIDTH = 32
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLK2X,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ output wire laguna_m_reset_out,
+ output wire [C_SLR_WIDTH-1:0] laguna_m_payload,
+ output wire laguna_m_handshake,
+ input wire laguna_m_ready
+ );
+
+ generate
+
+ if (C_REG_CONFIG == 13) begin : gen_slr_tdm
+ localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;
+
+ (* keep="true" *) reg areset_d = 1'b0;
+ always @(posedge ACLK) begin
+ areset_d <= ARESET;
+ end
+
+ assign laguna_m_reset_out = 1'b0;
+
+ (* shreg_extract = "no" *) reg [P_EVEN_WIDTH-1:0] payload_d1;
+ (* shreg_extract = "no" *) reg [C_SLR_WIDTH-1:0] laguna_payload_tdm_d2;
+ (* shreg_extract = "no" *) reg laguna_handshake_d1 = 1'b0;
+ reg s_ready_d2 = 1'b0;
+ wire sample_cycle;
+ integer i;
+
+ assign laguna_m_payload = laguna_payload_tdm_d2;
+ assign laguna_m_handshake = laguna_handshake_d1;
+ assign S_READY = s_ready_d2;
+
+ always @(posedge ACLK) begin
+ if (s_ready_d2) begin
+ payload_d1 <= S_PAYLOAD_DATA; // ACLK cycle 1
+ end
+ end
+
+ always @(posedge ACLK2X) begin
+ for (i=0;i<C_SLR_WIDTH;i=i+1) begin
+ if (s_ready_d2) begin
+ if (~sample_cycle) begin // First (high) phase of ACLK cycle 2
+ laguna_payload_tdm_d2[i] <= payload_d1[2*i+1]; // Mux odd bits
+ end else begin // Second (low) phase of ACLK cycle 2
+ laguna_payload_tdm_d2[i] <= payload_d1[2*i]; // Mux even bits
+ end
+ end
+ end
+ end
+
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ laguna_handshake_d1 <= 1'b0;
+ s_ready_d2 <= 1'b0;
+ end else begin
+ if (s_ready_d2) begin
+ laguna_handshake_d1 <= S_VALID & ACLKEN;
+ end
+ s_ready_d2 <= laguna_m_ready; // Half-cycle setup from dest_region.s_ready_d1
+ end
+ end
+
+ axis_register_slice_v1_1_17_tdm_sample tdm_sample_inst (
+ .slow_clk (ACLK),
+ .fast_clk (ACLK2X),
+ .sample_cycle (sample_cycle)
+ );
+
+ end else begin : gen_slr_common
+
+ localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;
+
+ (* keep="true" *) reg areset_r = 1'b0;
+ (* keep="true" *) reg areset_d = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_m_reset_out_i = 1'b0;
+ reg [15:0] areset_dly = 16'b0;
+
+ assign laguna_m_reset_out = laguna_m_reset_out_i;
+
+ always @(posedge ACLK) begin
+ areset_r <= ARESET;
+ areset_dly <= {16{areset_r}} | (areset_dly<<1);
+ areset_d <= C_REG_CONFIG == 12 ? ARESET : areset_dly[15];
+ laguna_m_reset_out_i <= areset_d; // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.
+ end
+
+ wire ACLEAR;
+ assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ARESET;
+
+ (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;
+ wire m_handshake_d;
+ wire laguna_m_handshake_q;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_m_ready_d = 1'b0;
+ (* keep="true" *) reg s_ready_i = 1'b0;
+ (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};
+ wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;
+ wire [(C_PIPELINES+1)-1:0] handshake_i;
+ genvar p;
+
+ assign laguna_m_payload = laguna_m_payload_i;
+ assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & ACLKEN & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];
+ assign laguna_m_handshake = laguna_m_handshake_q;
+ assign S_READY = s_ready_i;
+
+ always @(posedge ACLK) begin
+ laguna_m_ready_d <= laguna_m_ready;
+ ready_d <= {ready_d, laguna_m_ready_d};
+ if (areset_d) begin
+ s_ready_i <= 1'b0;
+ end else begin
+ s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];
+ end
+ end
+
+ for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data;
+ wire payload_valid_d;
+ wire payload_valid_q;
+
+ assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;
+ assign handshake_i[p] = payload_valid_q;
+ assign payload_valid_d = (p==0) ? (S_VALID & ACLKEN & s_ready_i) : handshake_i[((p>0)?(p-1):0)];
+
+ always @(posedge ACLK) begin
+ if (p==C_PIPELINES) begin
+ laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end else if (p==0) begin
+ payload_data <= S_PAYLOAD_DATA;
+ end else begin
+ payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ FDCE #(
+ .INIT(1'b0)
+ ) payload_valid_asyncclear_inst (
+ .Q (payload_valid_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (payload_valid_d)
+ );
+ end // loop p
+
+ (* USER_SLL_REG="true" *)
+ FDCE #(
+ .INIT(1'b0)
+ ) laguna_m_handshake_asyncclear_inst (
+ .Q (laguna_m_handshake_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (m_handshake_d)
+ );
+
+ end // gen_slr
+endgenerate
+endmodule // source_region_slr
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_dest_region_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_REG_CONFIG = 12,
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_SLR_WIDTH = 32,
+ parameter integer C_PIPELINES = 0,
+ parameter integer C_SOURCE_LATENCY = 1
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLK2X,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire laguna_s_reset_in,
+ input wire [C_SLR_WIDTH-1:0] laguna_s_payload,
+ input wire laguna_s_handshake,
+ output wire laguna_s_ready,
+
+ // Master side
+ output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
+ output wire M_VALID,
+ input wire M_READY
+ );
+
+ generate
+
+ if (C_REG_CONFIG == 13) begin : gen_slr_tdm
+ (* keep="true" *) reg areset_d = 1'b0;
+ always @(posedge ACLK) begin
+ areset_d <= ARESET;
+ end
+
+ localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;
+
+ (* shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] laguna_payload_tdm_d3;
+ (* shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] payload_tdm_d4;
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] fifo_out;
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;
+ (* shreg_extract="no" *) reg laguna_handshake_d2 = 1'b0;
+ (* shreg_extract="no" *) reg s_ready_d1 = 1'b0;
+ (* shreg_extract="no" *) reg s_ready_d2 = 1'b0;
+ reg [P_EVEN_WIDTH-1:0] payload_demux;
+ reg m_valid_r = 1'b0;
+ wire push;
+ wire pop;
+ reg [1:0] fifo_cnt = 2'h0;
+ integer i;
+
+ assign laguna_s_ready = s_ready_d1;
+ assign M_VALID = m_valid_r;
+ assign M_PAYLOAD_DATA = fifo_out; // Registered outputs
+ assign pop = M_READY & ACLKEN & m_valid_r;
+ assign push = laguna_handshake_d2 & s_ready_d2;
+
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ laguna_handshake_d2 <= 1'b0;
+ end else if (s_ready_d2) begin
+ laguna_handshake_d2 <= laguna_s_handshake;
+ end
+ end
+
+ always @(posedge ACLK2X) begin
+ if (s_ready_d2) begin
+ payload_tdm_d4 <= laguna_payload_tdm_d3;
+ laguna_payload_tdm_d3 <= laguna_s_payload;
+ end
+ end
+
+ always @ * begin
+ for (i=0;i<C_SLR_WIDTH;i=i+1) begin
+ payload_demux[2*i+1] = payload_tdm_d4[i]; // Odd bits captured during second (low) phase of ACLK cycle 2
+ payload_demux[2*i] = laguna_payload_tdm_d3[i]; // Even bits captured during first (high) phase of ACLK cycle 3
+ // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)
+ end
+ end
+
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ fifo_cnt <= 2'h0;
+ m_valid_r <= 1'b0;
+ s_ready_d2 <= 1'b0;
+ end else begin
+ s_ready_d2 <= s_ready_d1; // Half-cycle setup from s_ready_d1
+ if (push & ~pop) begin
+ fifo_cnt <= fifo_cnt + 2'h1;
+ m_valid_r <= 1'b1;
+ end else if (~push & pop) begin
+ fifo_cnt <= fifo_cnt - 2'h1;
+ m_valid_r <= fifo_cnt[1]; // fifo_cnt >= 2
+ end
+ end
+ end
+
+ always @(negedge ACLK) begin
+ if (areset_d) begin
+ s_ready_d1 <= 1'b0;
+ end else begin
+ s_ready_d1 <= (M_READY & ACLKEN) | ~m_valid_r; // Half-cycle setup
+ end
+ end
+
+ always @(posedge ACLK) begin
+ case (fifo_cnt)
+ 2'h0: begin // EMPTY
+ fifo_out <= payload_demux;
+ end
+
+ 2'h1: begin
+ fifo_out_n1 <= payload_demux;
+ if (pop) begin
+ fifo_out <= payload_demux;
+ end
+ end
+
+ default: begin // fifo_cnt == 2
+ if (pop) begin
+ fifo_out <= fifo_out_n1;
+ fifo_out_n1 <= payload_demux;
+ end
+ end
+ endcase
+ end
+
+ end else begin : gen_slr_common
+
+ localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;
+ localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;
+
+ (* keep="true" *) reg areset_d = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_s_reset_in_d = 1'b0;
+
+ always @(posedge ACLK) begin
+ laguna_s_reset_in_d <= laguna_s_reset_in;
+ areset_d <= C_REG_CONFIG == 12 ? ARESET : laguna_s_reset_in_d;
+ end
+
+ wire ACLEAR;
+ assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ARESET;
+
+ (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;
+ wire laguna_s_handshake_q;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_s_ready_i = 1'b0;
+ (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};
+ wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;
+ wire [(C_PIPELINES+1)-1:0] handshake_i;
+ wire m_valid_i;
+ wire push;
+ wire pop;
+ genvar p;
+
+ assign laguna_s_ready = laguna_s_ready_i;
+ assign pop = M_READY & ACLKEN & m_valid_i;
+ assign push = handshake_i[C_PIPELINES];
+ assign M_VALID = m_valid_i;
+
+ always @(posedge ACLK) begin
+ laguna_s_ready_i <= (C_PIPELINES==0) ? ((M_READY & ACLKEN) | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];
+ ready_d <= {ready_d, ((M_READY & ACLKEN) | ~m_valid_i)};
+ end
+
+ for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data;
+ wire payload_valid_d;
+ wire payload_valid_q;
+
+ assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;
+ assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;
+ assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];
+
+ always @(posedge ACLK) begin
+ if (p==0) begin
+ laguna_s_payload_d <= laguna_s_payload;
+ end else begin
+ payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ FDCE #(
+ .INIT(1'b0)
+ ) payload_valid_asyncclear_inst (
+ .Q (payload_valid_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (payload_valid_d)
+ );
+ end // loop p
+
+ (* USER_SLL_REG="true" *)
+ FDCE #(
+ .INIT(1'b0)
+ ) laguna_s_handshake_asyncclear_inst (
+ .Q (laguna_s_handshake_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (laguna_s_handshake)
+ );
+
+ axis_register_slice_v1_1_17_axic_reg_srl_fifo #
+ (
+ .C_FIFO_WIDTH (C_DATA_WIDTH),
+ .C_FIFO_SIZE ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)
+ )
+ srl_fifo_0
+ (
+ .aclk (ACLK),
+ .areset (areset_d),
+ .aclear (ACLEAR),
+ .s_mesg (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),
+ .s_valid (push),
+ .m_mesg (M_PAYLOAD_DATA),
+ .m_valid (m_valid_i),
+ .m_ready (pop)
+ );
+
+ end // gen_slr
+endgenerate
+endmodule // dest_region_slr
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_single_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_PIPELINES = 0
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLKEN,
+ input wire ARESET,
+
+ // Slave side
+ input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
+ output wire M_VALID,
+ input wire M_READY
+ );
+
+ generate
+
+ localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;
+
+ reg areset_d = 1'b0;
+ reg [3:0] areset_dly = 4'b0;
+ always @(posedge ACLK) begin
+ areset_dly <= {4{ARESET}} | (areset_dly<<1);
+ areset_d <= areset_dly[3];
+ end
+
+ if (1) begin : common
+ reg s_ready_i = 1'b0;
+ (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};
+ wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;
+ wire [(C_PIPELINES+1)-1:0] handshake_i;
+ wire m_valid_i;
+ wire push;
+ wire pop;
+ genvar p;
+
+ assign pop = M_READY & ACLKEN & m_valid_i;
+ assign push = handshake_i[C_PIPELINES];
+ assign M_VALID = m_valid_i;
+ assign S_READY = s_ready_i;
+
+ always @(posedge ACLK) begin
+ ready_d <= {ready_d, ((M_READY & ACLKEN) | ~m_valid_i)};
+ if (areset_d) begin
+ s_ready_i <= 1'b0;
+ end else begin
+ s_ready_i <= (C_PIPELINES==0) ? ((M_READY & ACLKEN) | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];
+ end
+ end
+
+ assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;
+ assign handshake_i[0] = S_VALID & ACLKEN & s_ready_i;
+
+ for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data;
+ (* keep="true" *) reg payload_valid = 1'b0;
+
+ assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;
+ assign handshake_i[p] = payload_valid;
+
+ always @(posedge ACLK) begin
+ if (p==1) begin
+ payload_data <= S_PAYLOAD_DATA;
+ payload_valid <= S_VALID & ACLKEN & s_ready_i & ~areset_d;
+ end else begin
+ payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ payload_valid <= handshake_i[((p>0)?(p-1):0)];
+ end
+ end
+ end
+
+ if (C_PIPELINES==0) begin : ff_fifo
+
+ (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out;
+ (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;
+ (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;
+ reg [1:0] fifo_cnt = 2'h0;
+ reg m_valid_r = 1'b0;
+
+ assign M_PAYLOAD_DATA = fifo_out;
+ assign m_valid_i = m_valid_r;
+
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ fifo_cnt <= 2'h0;
+ m_valid_r <= 1'b0;
+ end else begin
+ if (push & ~pop) begin
+ fifo_cnt <= fifo_cnt + 2'h1;
+ m_valid_r <= 1'b1;
+ end else if (~push & pop) begin
+ fifo_cnt <= fifo_cnt - 2'h1;
+ m_valid_r <= fifo_cnt[1]; // fifo_cnt >= 2
+ end
+ end
+ end
+
+ always @(posedge ACLK) begin
+ case (fifo_cnt)
+ 2'h0: begin // EMPTY
+ fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+
+ 2'h1: begin
+ fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ if (pop) begin
+ fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ 2'h2: begin
+ fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ if (pop) begin
+ fifo_out <= fifo_out_n1;
+ fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ default: begin // fifo_cnt == 3
+ if (pop) begin
+ fifo_out <= fifo_out_n1;
+ fifo_out_n1 <= fifo_out_n2;
+ fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+ endcase
+ end
+
+ end else begin : srl_fifo
+
+ axis_register_slice_v1_1_17_axic_reg_srl_fifo #
+ (
+ .C_FIFO_WIDTH (C_DATA_WIDTH),
+ .C_FIFO_SIZE ((C_PIPELINES>12) ? 5 : 4)
+ )
+ srl_fifo_0
+ (
+ .aclk (ACLK),
+ .areset (areset_d),
+ .aclear (1'b0),
+ .s_mesg (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),
+ .s_valid (push),
+ .m_mesg (M_PAYLOAD_DATA),
+ .m_valid (m_valid_i),
+ .m_ready (pop)
+ );
+
+ end // gen_fifo
+ end // gen_slr
+ endgenerate
+endmodule // single_slr
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_axic_reg_srl_fifo #
+ // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full
+ (
+ parameter integer C_FIFO_WIDTH = 1, // Width of s_mesg/m_mesg.
+ parameter integer C_FIFO_SIZE = 5 // Depth of FIFO is 2**C_FIFO_SIZE.
+ )
+ (
+ input wire aclk, // Clock
+ input wire areset, // Reset
+ input wire aclear, // Async clear
+ input wire [C_FIFO_WIDTH-1:0] s_mesg, // Input data
+ input wire s_valid, // Input data valid
+ output wire [C_FIFO_WIDTH-1:0] m_mesg, // Output data
+ output wire m_valid, // Output data valid
+ input wire m_ready // Output data ready
+ );
+
+ genvar i;
+
+ generate
+
+ localparam integer P_FIFO_DEPTH = 2**C_FIFO_SIZE;
+ localparam [C_FIFO_SIZE-1:0] P_EMPTY = {C_FIFO_SIZE{1'b1}};
+ localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};
+
+ localparam M_VALID_0 = 1'b0;
+ localparam M_VALID_1 = 1'b1;
+ localparam SRL_VALID_0 = 1'b0;
+ localparam SRL_VALID_1 = 1'b1;
+ localparam S_VALID_0 = 1'b0;
+ localparam S_VALID_1 = 1'b1;
+ localparam M_READY_0 = 1'b0;
+ localparam M_READY_1 = 1'b1;
+
+ localparam [1:0] K_EMPTY = {SRL_VALID_0, M_VALID_0};
+ localparam [1:0] K_HAS1 = {SRL_VALID_0, M_VALID_1};
+ localparam [1:0] K_MIN2 = {SRL_VALID_1, M_VALID_1};
+
+ reg push; // SRL push
+ reg pop; // SRL pop
+ wire [C_FIFO_WIDTH-1:0] srl_reg;
+ reg [C_FIFO_SIZE-1:0] fifoaddr = P_EMPTY;
+
+ wire [1:0] state; // State vector register
+ reg [1:0] next; // Next state value
+ wire [1:0] next_qual; // Next state value
+
+ reg load_mesg; // Load output register
+ reg srl2mesg; // Output reg loads from SRL (else from s_mesg)
+ reg [C_FIFO_WIDTH-1:0] mesg_reg; // No initial state
+ reg m_valid_d;
+ wire m_valid_q;
+
+ assign m_valid = m_valid_q;
+ assign next_qual = areset ? K_EMPTY : next;
+ assign m_mesg = mesg_reg;
+
+ FDCE #(
+ .INIT(1'b0)
+ ) asyncclear_mvalid_inst (
+ .Q (m_valid_q),
+ .C (aclk),
+ .CE (1'b1),
+ .CLR (aclear),
+ .D (m_valid_d)
+ );
+
+ FDCE #(
+ .INIT(1'b0)
+ ) asyncclear_state0_inst (
+ .Q (state[0]),
+ .C (aclk),
+ .CE (1'b1),
+ .CLR (aclear),
+ .D (next_qual[0])
+ );
+
+ FDCE #(
+ .INIT(1'b0)
+ ) asyncclear_state1_inst (
+ .Q (state[1]),
+ .C (aclk),
+ .CE (1'b1),
+ .CLR (aclear),
+ .D (next_qual[1])
+ );
+
+ always @ * begin
+ next = state; // Default: hold state unless re-assigned
+ m_valid_d = m_valid_q & ~areset;
+ load_mesg = 1'b1;
+ srl2mesg = 1'b0;
+ push = 1'b0;
+ pop = 1'b0;
+ case (state)
+ K_EMPTY: begin // FIFO Empty; pre-assert s_ready
+ load_mesg = s_valid;
+ srl2mesg = 1'b0;
+ push = 1'b0;
+ pop = 1'b0;
+ if (s_valid & ~areset) begin
+ next = K_HAS1;
+ m_valid_d = 1'b0;
+ end
+ end // EMPTY
+
+ K_HAS1: begin // FIFO contains 1 item in the output register (SRL empty)
+ srl2mesg = 1'b0;
+ pop = 1'b0;
+ casex ({s_valid,m_ready})
+ {S_VALID_1,M_READY_0}: begin // Receive a 2nd item, push into SRL
+ next = K_MIN2;
+ load_mesg = 1'b0;
+ push = 1'b1;
+ m_valid_d = 1'b1;
+ end
+
+ {S_VALID_0,M_READY_1}: begin // Pop to empty
+ next = K_EMPTY;
+ load_mesg = 1'b1; // Inconsequential
+ push = 1'b0;
+ m_valid_d = 1'b0;
+ end
+
+ {S_VALID_1,M_READY_1}: begin // Push a new item while popping; replace contents of output reg
+ next = K_HAS1;
+ load_mesg = 1'b1;
+ push = 1'b0;
+ m_valid_d = 1'b1;
+ end
+
+ default: begin // s_valid=0, m_ready=0: hold state
+ next = K_HAS1;
+ load_mesg = 1'b0;
+ push = 1'b0;
+ m_valid_d = 1'b1;
+ end
+ endcase
+ end // HAS1
+
+ K_MIN2: begin // FIFO contains >1 item, some in SRL
+ srl2mesg = 1'b1;
+ m_valid_d = 1'b1;
+ casex ({s_valid,m_ready})
+ {S_VALID_1,M_READY_0}: begin // Receive a new item, push into SRL
+ next = K_MIN2;
+ load_mesg = 1'b0;
+ push = 1'b1;
+ pop = 1'b0;
+ end
+
+ {S_VALID_0,M_READY_1}: begin // Pop SRL to replace output reg
+ next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;
+ load_mesg = 1'b1;
+ push = 1'b0;
+ pop = 1'b1;
+ end
+
+ {S_VALID_1,M_READY_1}: begin // Push a new item while popping
+ next = K_MIN2;
+ load_mesg = 1'b1;
+ push = 1'b1;
+ pop = 1'b1;
+ end
+
+ default: begin // s_valid=0, m_ready=0: hold state
+ next = K_MIN2;
+ load_mesg = 1'b0;
+ push = 1'b0;
+ pop = 1'b0;
+ end
+ endcase
+ end // MIN2
+
+ default: begin // Same as RESET
+ next = K_EMPTY;
+ end // default
+ endcase
+ end
+
+ always @(posedge aclk) begin // Payload reg needs no reset
+ if (load_mesg) begin
+ mesg_reg <= srl2mesg ? srl_reg : s_mesg;
+ end
+ end
+
+ // SRL FIFO address pointer
+ always @(posedge aclk) begin
+ if (areset) begin
+ fifoaddr <= P_EMPTY;
+ end else begin
+ if (push & ~pop) begin
+ fifoaddr <= fifoaddr + 1;
+ end else if (~push & pop) begin
+ fifoaddr <= fifoaddr - 1;
+ end
+ end
+ end
+
+ //---------------------------------------------------------------------------
+ // Instantiate SRLs
+ //---------------------------------------------------------------------------
+ for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl
+ (* keep_hierarchy = "yes" *) axis_register_slice_v1_1_17_srl_rtl #
+ (
+ .C_A_WIDTH (C_FIFO_SIZE)
+ )
+ srl_nx1
+ (
+ .clk (aclk),
+ .a (fifoaddr),
+ .ce (s_valid),
+ .d (s_mesg[i]),
+ .q (srl_reg[i])
+ );
+ end
+ endgenerate
+
+endmodule // axic_reg_srl_fifo
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_srl_rtl #
+ (
+ parameter C_A_WIDTH = 2 // Address Width (>= 1)
+ )
+ (
+ input wire clk, // Clock
+ input wire [C_A_WIDTH-1:0] a, // Address
+ input wire ce, // Clock Enable
+ input wire d, // Input Data
+ output wire q // Output Data
+ );
+
+ localparam integer P_SRLDEPTH = 2**C_A_WIDTH;
+
+ reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
+ always @(posedge clk)
+ if (ce)
+ shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};
+ assign q = shift_reg[a];
+
+endmodule // srl_rtl
+
+
+// (c) Copyright 2010-2011, 2013-2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+// Generic single-channel AXI pipeline register on forward and/or reverse signal path
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axic_register_slice
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_axisc_register_slice #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter C_DATA_WIDTH = 32,
+ parameter C_REG_CONFIG = 32'h00000001,
+ // C_REG_CONFIG:
+ // 0 => BYPASS = The channel is just wired through the module.
+ // 1 => DEFAULT = Minimized fanout on input signals M_READY and S_TVALID
+ // 2 => FWD = The master VALID and payload signals are registrated.
+ // 3 => REV = The slave ready signal is registrated
+ // 4 => RESERVED (all outputs driven to 0).
+ // 5 => RESERVED (all outputs driven to 0).
+ // 6 => INPUTS = Slave and Master side inputs are registrated.
+ // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+ // 8 => FWD_REV = Both FWD and REV (fully-registered)
+ // 10 => NO_READY = Assume no ready signal
+ // 12 => SLR Crossing (source->dest flops, full-width payload, single clock)
+ // 13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)
+ parameter integer C_NUM_SLR_CROSSINGS = 0,
+ parameter integer C_PIPELINES_MASTER = 0,
+ parameter integer C_PIPELINES_SLAVE = 0,
+ parameter integer C_PIPELINES_MIDDLE = 0
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLK2X,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
+ output wire M_VALID,
+ input wire M_READY
+ );
+
+ generate
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 0
+ // Bypass mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ if (C_REG_CONFIG == 32'h00000000)
+ begin
+ assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
+ assign M_VALID = S_VALID;
+ assign S_READY = M_READY;
+ end
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 15
+ // Multi SLR Crossing
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 15) begin : gen_multi_slr
+
+ axis_register_slice_v1_1_17_multi_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,
+ .C_PIPELINES_MASTER (C_PIPELINES_MASTER) ,
+ .C_PIPELINES_SLAVE (C_PIPELINES_SLAVE) ,
+ .C_PIPELINES_MIDDLE (C_PIPELINES_MIDDLE)
+ )
+ multi (
+ // System Signals
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+
+ // Slave side
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+
+ // Master side
+ .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) ,
+ .M_VALID ( M_VALID ) ,
+ .M_READY ( M_READY )
+ );
+ end
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 12 or 13
+ // TDM SLR Crossing
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if ((C_REG_CONFIG == 32'h0000000C) || (C_REG_CONFIG == 32'h0000000D))
+ begin : gen_slr_crossing
+ localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;
+ localparam integer P_TDM_WIDTH = P_EVEN_WIDTH/2;
+ localparam integer P_SLR_WIDTH = (C_REG_CONFIG == 13) ? P_TDM_WIDTH : C_DATA_WIDTH;
+
+ wire [P_SLR_WIDTH-1:0] slr_payload;
+ wire slr_handshake;
+ wire slr_ready;
+
+ axis_register_slice_v1_1_17_source_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( C_REG_CONFIG ) ,
+ .C_PIPELINES (0),
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( P_SLR_WIDTH )
+ )
+ slr_source_0 (
+ .ACLK ( ACLK ) ,
+ .ACLK2X ( ACLK2X ) ,
+ .ARESET (ARESET),
+ .ACLKEN ( ACLKEN ) ,
+ .laguna_m_reset_out ( ) ,
+ .S_PAYLOAD_DATA ( S_PAYLOAD_DATA ) ,
+ .S_VALID ( S_VALID ) ,
+ .S_READY ( S_READY ) ,
+ .laguna_m_payload ( slr_payload ) ,
+ .laguna_m_handshake ( slr_handshake ) ,
+ .laguna_m_ready ( slr_ready )
+ );
+
+ axis_register_slice_v1_1_17_dest_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( C_REG_CONFIG ) ,
+ .C_PIPELINES (0),
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( P_SLR_WIDTH )
+ )
+ slr_dest_0 (
+ .ACLK ( ACLK ) ,
+ .ACLK2X ( ACLK2X ) ,
+ .ARESET (ARESET),
+ .ACLKEN ( ACLKEN ) ,
+ .laguna_s_reset_in ( 1'b0 ) ,
+ .laguna_s_payload ( slr_payload ) ,
+ .laguna_s_handshake ( slr_handshake ) ,
+ .laguna_s_ready ( slr_ready ) ,
+ .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) ,
+ .M_VALID ( M_VALID ) ,
+ .M_READY ( M_READY )
+ );
+
+ end // if (C_REG_CONFIG == 12 or 13 )
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 10
+ // No ready, single stage register
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h0000000A)
+ begin : NO_READY
+
+ reg [C_DATA_WIDTH-1:0] storage_data1;
+ reg m_valid_r = 1'b0; //local signal of output
+
+ // assign local signal to its output signal
+ assign S_READY = 1'b1;
+ assign M_VALID = m_valid_r;
+
+ // Load storage1 with slave side data
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN) begin
+ storage_data1 <= S_PAYLOAD_DATA;
+ m_valid_r <= S_VALID;
+ end
+ end
+
+ assign M_PAYLOAD_DATA = storage_data1;
+
+
+ end // if (C_REG_CONFIG == 10 )
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 1
+ // Minimized fanout on input signals M_READY and S_TVALID
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000001) begin : gen_AB_reg_slice
+ // /----------S_READY
+ // |/---------M_VALID
+ localparam SM_RESET = 2'b00;
+ localparam SM_IDLE = 2'b10;
+ localparam SM_ONE = 2'b11;
+ localparam SM_FULL = 2'b01;
+
+ (* fsm_encoding = "none" *) reg [1:0] state = SM_RESET;
+ reg [C_DATA_WIDTH-1:0] payload_a;
+ reg [C_DATA_WIDTH-1:0] payload_b;
+ reg sel_rd = 1'b0;
+ reg sel_wr = 1'b0;
+ wire sel;
+ wire load_a;
+ wire load_b;
+
+ assign M_VALID = state[0];
+ assign S_READY = state[1];
+
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ state <= SM_RESET;
+ end
+ else if (ACLKEN) begin
+ case (state)
+ SM_IDLE:
+ if (S_VALID)
+ state <= SM_ONE;
+ SM_ONE:
+ if (S_VALID & ~M_READY)
+ state <= SM_FULL;
+ else if (~S_VALID & M_READY)
+ state <= SM_IDLE;
+ SM_FULL:
+ if (M_READY)
+ state <= SM_ONE;
+ // SM_RESET:
+ default:
+ state <= SM_IDLE;
+ endcase
+ end
+ end
+
+ assign sel = sel_rd;
+
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ sel_rd <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ sel_rd <= (M_READY & M_VALID) ? ~sel_rd : sel_rd;
+ end
+ end
+
+ assign load_a = ~sel_wr & (state != SM_FULL);
+ assign load_b = sel_wr & (state != SM_FULL);
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ sel_wr <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ sel_wr <= (S_READY & S_VALID) ? ~sel_wr : sel_wr;
+ end
+ end
+
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ payload_a <= load_a ? S_PAYLOAD_DATA : payload_a;
+ end
+ end
+
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ payload_b <= load_b ? S_PAYLOAD_DATA : payload_b;
+ end
+ end
+
+ assign M_PAYLOAD_DATA = sel ? payload_b : payload_a;
+
+ end // if (C_REG_CONFIG == 1 )
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 8
+ // Both FWD and REV mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if ((C_REG_CONFIG == 32'h00000008))
+ begin
+ localparam [1:0]
+ ZERO = 2'b10,
+ ONE = 2'b11,
+ TWO = 2'b01;
+ (* fsm_encoding = "none" *) reg [1:0] state = ZERO;
+
+ reg [C_DATA_WIDTH-1:0] storage_data1;
+ reg [C_DATA_WIDTH-1:0] storage_data2;
+ reg load_s1;
+ wire load_s2;
+ wire load_s1_from_s2;
+ reg s_ready_i = 1'b0; //local signal of output
+ wire m_valid_i; //local signal of output
+
+ // assign local signal to its output signal
+ assign S_READY = s_ready_i;
+ assign M_VALID = m_valid_i;
+
+ (* equivalent_register_removal = "no" *) reg [1:0] areset_d = 2'b11; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= {areset_d[0], ARESET};
+ end
+ end
+
+ // Load storage1 with either slave side data or from storage2
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN) begin
+ storage_data1 <= ~load_s1 ? storage_data1 :
+ load_s1_from_s2 ? storage_data2 :
+ S_PAYLOAD_DATA;
+ end
+ end
+
+ // Load storage2 with slave side data
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN) begin
+ storage_data2 <= load_s2 ? S_PAYLOAD_DATA : storage_data2;
+ end
+ end
+
+ assign M_PAYLOAD_DATA = storage_data1;
+
+ // Always load s2 on a valid transaction even if it's unnecessary
+ assign load_s2 = S_VALID & s_ready_i;
+
+ // Loading s1
+ always @ *
+ begin
+ if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
+ // Load when ONE if we both have read and write at the same time
+ ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
+ // Load when TWO and we have a transaction on Master side
+ ((state == TWO) && (M_READY == 1)))
+ load_s1 = 1'b1;
+ else
+ load_s1 = 1'b0;
+ end // always @ *
+
+ assign load_s1_from_s2 = (state == TWO);
+
+ // State Machine for handling output signals
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ s_ready_i <= 1'b0;
+ state <= ZERO;
+ end else if (ACLKEN && areset_d == 2'b10) begin
+ s_ready_i <= 1'b1;
+ state <= ZERO;
+ end else if (ACLKEN && areset_d == 2'b00) begin
+ case (state)
+ // No transaction stored locally
+ ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
+
+ // One transaction stored locally
+ ONE: begin
+ if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
+ if (~M_READY & S_VALID) begin
+ state <= TWO; // Got another one so move to TWO
+ s_ready_i <= 1'b0;
+ end
+ end
+
+ // TWO transaction stored locally
+ TWO: if (M_READY) begin
+ state <= ONE; // Read out one so move to ONE
+ s_ready_i <= 1'b1;
+ end
+
+ default:
+ state <= ZERO;
+
+ endcase // case (state)
+ end
+ end // always @ (posedge ACLK)
+
+ assign m_valid_i = state[0];
+
+ end // if (C_REG_CONFIG == 8)
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 2
+ // Only FWD mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000002)
+ begin
+ reg [C_DATA_WIDTH-1:0] storage_data;
+ wire s_ready_i; //local signal of output
+ reg m_valid_i = 1'b0; //local signal of output
+
+ // assign local signal to its output signal
+ assign S_READY = s_ready_i;
+ assign M_VALID = m_valid_i;
+
+ (* equivalent_register_removal = "no" *) reg [1:0] areset_d; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= {areset_d[0], ARESET};
+ end
+ end
+
+ // Save payload data whenever we have a transaction on the slave side
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN)
+ storage_data <= (S_VALID & s_ready_i) ? S_PAYLOAD_DATA : storage_data;
+ end
+
+ assign M_PAYLOAD_DATA = storage_data;
+
+ // M_Valid set to high when we have a completed transfer on slave side
+ // Is removed on a M_READY except if we have a new transfer on the slave side
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ m_valid_i <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ m_valid_i <= S_VALID ? 1'b1 : // Always set m_valid_i when slave side is valid
+ M_READY ? 1'b0 : // Clear (or keep) when no slave side is valid but master side is ready
+ m_valid_i;
+ end
+ end // always @ (posedge ACLK)
+
+ // Slave Ready is either when Master side drives M_Ready or we have space in our storage data
+ assign s_ready_i = (M_READY | ~m_valid_i) & ~|areset_d;
+
+ end // if (C_REG_CONFIG == 2)
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 3
+ // Only REV mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000003)
+ begin
+ reg [C_DATA_WIDTH-1:0] storage_data;
+ reg s_ready_i = 1'b0; //local signal of output
+ reg has_valid_storage_i;
+ reg has_valid_storage;
+
+ (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= ARESET;
+ end
+ end
+
+ // Save payload data whenever we have a transaction on the slave side
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN)
+ storage_data <= (S_VALID & s_ready_i) ? S_PAYLOAD_DATA : storage_data;
+ end
+
+ assign M_PAYLOAD_DATA = has_valid_storage ? storage_data : S_PAYLOAD_DATA;
+
+ // Need to determine when we need to save a payload
+ // Need a combinatorial signals since it will also effect S_READY
+ always @ *
+ begin
+ // Set the value if we have a slave transaction but master side is not ready
+ if (S_VALID & s_ready_i & ~M_READY)
+ has_valid_storage_i = 1'b1;
+
+ // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
+ // transaction
+ else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
+ has_valid_storage_i = 1'b0;
+ else
+ has_valid_storage_i = has_valid_storage;
+ end // always @ *
+
+ always @(posedge ACLK)
+ begin
+ if (ARESET) begin
+ has_valid_storage <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ has_valid_storage <= has_valid_storage_i;
+ end
+ end
+
+ // S_READY is either clocked M_READY or that we have room in local storage
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ s_ready_i <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ s_ready_i <= M_READY | ~has_valid_storage_i;
+ end
+ end
+
+ // assign local signal to its output signal
+ assign S_READY = s_ready_i;
+
+ // M_READY is either combinatorial S_READY or that we have valid data in local storage
+ assign M_VALID = (S_VALID | has_valid_storage) & ~areset_d;
+
+ end // if (C_REG_CONFIG == 3)
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
+ begin
+// synthesis translate_off
+ initial begin
+ $display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
+ end
+// synthesis translate_on
+ assign M_PAYLOAD_DATA = 0;
+ assign M_VALID = 1'b0;
+ assign S_READY = 1'b0;
+ end
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 6
+ // INPUTS mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000006)
+ begin
+ localparam [1:0]
+ ZERO = 2'b00,
+ ONE = 2'b01,
+ TWO = 2'b11;
+ reg [1:0] state = ZERO;
+ reg [1:0] next_state;
+
+ reg [C_DATA_WIDTH-1:0] storage_data1;
+ reg [C_DATA_WIDTH-1:0] storage_data2;
+ reg s_valid_d = 1'b0;
+ reg s_ready_d = 1'b0;
+ reg m_ready_d = 1'b0;
+ reg m_valid_d = 1'b0;
+ reg load_s2;
+ reg sel_s2;
+ wire new_access;
+ wire access_done;
+ wire s_ready_i; //local signal of output
+ reg s_ready_ii;
+ reg m_valid_i; //local signal of output
+
+ (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= ARESET;
+ end
+ end
+
+ // assign local signal to its output signal
+ assign S_READY = (state == ZERO) ? 1'b0 : s_ready_i;
+ assign M_VALID = (state == ZERO) ? 1'b0 : m_valid_i;
+ assign s_ready_i = s_ready_ii & ~areset_d;
+
+ // Registrate input control signals
+ always @(posedge ACLK)
+ begin
+ if (ARESET) begin
+ s_valid_d <= 1'b0;
+ s_ready_d <= 1'b0;
+ m_ready_d <= 1'b0;
+ end else if (ACLKEN) begin
+ s_valid_d <= S_VALID;
+ s_ready_d <= s_ready_i;
+ m_ready_d <= M_READY;
+ end
+ end // always @ (posedge ACLK)
+
+ // Load storage1 with slave side payload data when slave side ready is high
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN)
+ storage_data1 <= (s_ready_i) ? S_PAYLOAD_DATA : storage_data1;
+ end
+
+ // Load storage2 with storage data
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN)
+ storage_data2 <= load_s2 ? storage_data1 : storage_data2;
+ end
+
+ always @(posedge ACLK)
+ begin
+ if (ARESET)
+ m_valid_d <= 1'b0;
+ else if (ACLKEN)
+ m_valid_d <= m_valid_i;
+ end
+
+ // Local help signals
+ assign new_access = s_ready_d & s_valid_d;
+ assign access_done = m_ready_d & m_valid_d;
+
+
+ // State Machine for handling output signals
+ always @*
+ begin
+ next_state = state; // Stay in the same state unless we need to move to another state
+ load_s2 = 0;
+ sel_s2 = 0;
+ m_valid_i = 0;
+ s_ready_ii = 0;
+ case (state)
+ // No transaction stored locally
+ ZERO: begin
+ load_s2 = 0;
+ sel_s2 = 0;
+ m_valid_i = 0;
+ s_ready_ii = 1;
+ if (new_access) begin
+ next_state = ONE; // Got one so move to ONE
+ load_s2 = 1;
+ m_valid_i = 0;
+ end
+ else begin
+ next_state = next_state;
+ load_s2 = load_s2;
+ m_valid_i = m_valid_i;
+ end
+
+ end // case: ZERO
+
+ // One transaction stored locally
+ ONE: begin
+ load_s2 = 0;
+ sel_s2 = 1;
+ m_valid_i = 1;
+ s_ready_ii = 1;
+ if (~new_access & access_done) begin
+ next_state = ZERO; // Read out one so move to ZERO
+ m_valid_i = 0;
+ end
+ else if (new_access & ~access_done) begin
+ next_state = TWO; // Got another one so move to TWO
+ s_ready_ii = 0;
+ end
+ else if (new_access & access_done) begin
+ load_s2 = 1;
+ sel_s2 = 0;
+ end
+ else begin
+ load_s2 = load_s2;
+ sel_s2 = sel_s2;
+ end
+
+
+ end // case: ONE
+
+ // TWO transaction stored locally
+ TWO: begin
+ load_s2 = 0;
+ sel_s2 = 1;
+ m_valid_i = 1;
+ s_ready_ii = 0;
+ if (access_done) begin
+ next_state = ONE; // Read out one so move to ONE
+ s_ready_ii = 1;
+ load_s2 = 1;
+ sel_s2 = 0;
+ end
+ else begin
+ next_state = next_state;
+ s_ready_ii = s_ready_ii;
+ load_s2 = load_s2;
+ sel_s2 = sel_s2;
+ end
+ end // case: TWO
+ endcase // case (state)
+ end // always @ *
+
+
+ // State Machine for handling output signals
+ always @(posedge ACLK)
+ begin
+ if (ARESET)
+ state <= ZERO;
+ else if (ACLKEN)
+ state <= next_state; // Stay in the same state unless we need to move to another state
+ end
+
+ // Master Payload mux
+ assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
+
+ end // if (C_REG_CONFIG == 6)
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 7
+ // Light-weight mode.
+ // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+ // Operates same as 1-deep FIFO
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000007)
+ begin
+ reg [C_DATA_WIDTH-1:0] storage_data1;
+ reg s_ready_i = 1'b0; //local signal of output
+ reg m_valid_i = 1'b0; //local signal of output
+
+ // assign local signal to its output signal
+ assign S_READY = s_ready_i;
+ assign M_VALID = m_valid_i;
+
+ (* equivalent_register_removal = "no" *) reg [1:0] areset_d; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= {areset_d[0], ARESET};
+ end
+ end
+
+ // Load storage1 with slave side data
+ always @(posedge ACLK)
+ begin
+ if (ARESET) begin
+ s_ready_i <= 1'b0;
+ m_valid_i <= 1'b0;
+ end else if (ACLKEN && areset_d == 2'b10) begin
+ s_ready_i <= 1'b1;
+ end else if (ACLKEN && areset_d == 2'b00) begin
+ if (m_valid_i & M_READY) begin
+ s_ready_i <= 1'b1;
+ m_valid_i <= 1'b0;
+ end else if (S_VALID & s_ready_i) begin
+ s_ready_i <= 1'b0;
+ m_valid_i <= 1'b1;
+ end
+ end
+ if (~m_valid_i) begin
+ storage_data1 <= S_PAYLOAD_DATA;
+ end
+ end
+ assign M_PAYLOAD_DATA = storage_data1;
+ end // if (C_REG_CONFIG == 7)
+
+ else begin : default_case
+ // Passthrough
+ assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
+ assign M_VALID = S_VALID;
+ assign S_READY = M_READY;
+ end
+
+ endgenerate
+endmodule // axisc_register_slice
+
+
+
+// (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+// Generic single-channel AXIS pipeline register on forward and/or reverse signal path.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_register_slice
+// util_axis2vector
+// axisc_register_slice
+// util_vector2axis
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_axis_register_slice #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_AXIS_TDATA_WIDTH = 8,
+ parameter integer C_AXIS_TID_WIDTH = 1,
+ parameter integer C_AXIS_TDEST_WIDTH = 1,
+ parameter integer C_AXIS_TUSER_WIDTH = 1,
+ parameter [31:0] C_AXIS_SIGNAL_SET = 32'h3,
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ parameter integer C_REG_CONFIG = 1,
+ // C_REG_CONFIG:
+ // 0 => BYPASS = The channel is just wired through the module.
+ // 1 => DEFAULT = Minimized fanout on input signals M_READY and S_TVALID
+ // 2 => FWD = The master VALID and payload signals are registrated.
+ // 3 => REV = The slave ready signal is registrated
+ // 4 => RESERVED (all outputs driven to 0).
+ // 5 => RESERVED (all outputs driven to 0).
+ // 6 => INPUTS = Slave and Master side inputs are registrated.
+ // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+ // 8 => FWD_REV = Both FWD and REV (fully-registered)
+ // 10 => NO_READY = Assume no ready signal
+ // 12 => SLR Crossing (source->dest flops, full-width payload, single clock)
+ // 13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)
+ parameter integer C_NUM_SLR_CROSSINGS = 0,
+ parameter integer C_PIPELINES_MASTER = 0,
+ parameter integer C_PIPELINES_SLAVE = 0,
+ parameter integer C_PIPELINES_MIDDLE = 0
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // System Signals
+ input wire aclk,
+ input wire aclk2x,
+ input wire aresetn,
+ input wire aclken,
+
+ // Slave side
+ input wire s_axis_tvalid,
+ output wire s_axis_tready,
+ input wire [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
+ input wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb,
+ input wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep,
+ input wire s_axis_tlast,
+ input wire [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
+ input wire [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
+ input wire [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
+
+ // Master side
+ output wire m_axis_tvalid,
+ input wire m_axis_tready,
+ output wire [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
+ output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb,
+ output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep,
+ output wire m_axis_tlast,
+ output wire [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
+ output wire [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
+ output wire [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+ localparam P_TPAYLOAD_WIDTH = f_payload_width(C_AXIS_TDATA_WIDTH, C_AXIS_TID_WIDTH,
+ C_AXIS_TDEST_WIDTH, C_AXIS_TUSER_WIDTH,
+ C_AXIS_SIGNAL_SET);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire [P_TPAYLOAD_WIDTH-1:0] s_axis_tpayload;
+wire [P_TPAYLOAD_WIDTH-1:0] m_axis_tpayload;
+
+reg areset_r;
+always @(posedge aclk) begin
+ areset_r <= ~aresetn;
+end
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+ axis_infrastructure_v1_1_0_util_axis2vector #(
+ .C_TDATA_WIDTH ( C_AXIS_TDATA_WIDTH ) ,
+ .C_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_TUSER_WIDTH ( C_AXIS_TUSER_WIDTH ) ,
+ .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_SIGNAL_SET ( C_AXIS_SIGNAL_SET )
+ )
+ util_axis2vector_0 (
+ .TDATA ( s_axis_tdata ) ,
+ .TSTRB ( s_axis_tstrb ) ,
+ .TKEEP ( s_axis_tkeep ) ,
+ .TLAST ( s_axis_tlast ) ,
+ .TID ( s_axis_tid ) ,
+ .TDEST ( s_axis_tdest ) ,
+ .TUSER ( s_axis_tuser ) ,
+ .TPAYLOAD ( s_axis_tpayload )
+ );
+
+ axis_register_slice_v1_1_17_axisc_register_slice #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_REG_CONFIG ( (C_AXIS_SIGNAL_SET[0] == 0) ? 32'hA : C_REG_CONFIG),
+ .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,
+ .C_PIPELINES_MASTER (C_PIPELINES_MASTER) ,
+ .C_PIPELINES_SLAVE (C_PIPELINES_SLAVE) ,
+ .C_PIPELINES_MIDDLE (C_PIPELINES_MIDDLE)
+ )
+ axisc_register_slice_0 (
+ .ACLK ( aclk ) ,
+ .ACLK2X ( aclk2x ) ,
+ .ARESET ( areset_r ) ,
+ .ACLKEN ( aclken ) ,
+ .S_VALID ( s_axis_tvalid ) ,
+ .S_READY ( s_axis_tready ) ,
+ .S_PAYLOAD_DATA ( s_axis_tpayload ) ,
+
+ .M_VALID ( m_axis_tvalid ) ,
+ .M_READY ( (C_AXIS_SIGNAL_SET[0] == 0) ? 1'b1 : m_axis_tready ) ,
+ .M_PAYLOAD_DATA ( m_axis_tpayload )
+ );
+
+ axis_infrastructure_v1_1_0_util_vector2axis #(
+ .C_TDATA_WIDTH ( C_AXIS_TDATA_WIDTH ) ,
+ .C_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_TUSER_WIDTH ( C_AXIS_TUSER_WIDTH ) ,
+ .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_SIGNAL_SET ( C_AXIS_SIGNAL_SET )
+ )
+ util_vector2axis_0 (
+ .TPAYLOAD ( m_axis_tpayload ) ,
+ .TDATA ( m_axis_tdata ) ,
+ .TSTRB ( m_axis_tstrb ) ,
+ .TKEEP ( m_axis_tkeep ) ,
+ .TLAST ( m_axis_tlast ) ,
+ .TID ( m_axis_tid ) ,
+ .TDEST ( m_axis_tdest ) ,
+ .TUSER ( m_axis_tuser )
+ );
+
+
+endmodule // axis_register_slice
+
+`default_nettype wire
+
+
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/sim/axis_dwidth_converter_256_64.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/sim/axis_dwidth_converter_256_64.v
new file mode 100644
index 0000000000000000000000000000000000000000..3b51c91c82633e2ddf0eced74e838ca507d4b7cf
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/sim/axis_dwidth_converter_256_64.v
@@ -0,0 +1,132 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
+// IP Revision: 16
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module axis_dwidth_converter_256_64 (
+ aclk,
+ aresetn,
+ s_axis_tvalid,
+ s_axis_tready,
+ s_axis_tdata,
+ s_axis_tkeep,
+ s_axis_tlast,
+ m_axis_tvalid,
+ m_axis_tready,
+ m_axis_tdata,
+ m_axis_tkeep,
+ m_axis_tlast
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, PHASE 0.000" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
+input wire s_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
+output wire s_axis_tready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
+input wire [255 : 0] s_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
+input wire [31 : 0] s_axis_tkeep;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
+input wire s_axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
+output wire m_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
+input wire m_axis_tready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
+output wire [63 : 0] m_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
+output wire [7 : 0] m_axis_tkeep;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
+output wire m_axis_tlast;
+
+ axis_dwidth_converter_v1_1_16_axis_dwidth_converter #(
+ .C_FAMILY("virtexuplus"),
+ .C_S_AXIS_TDATA_WIDTH(256),
+ .C_M_AXIS_TDATA_WIDTH(64),
+ .C_AXIS_TID_WIDTH(1),
+ .C_AXIS_TDEST_WIDTH(1),
+ .C_S_AXIS_TUSER_WIDTH(1),
+ .C_M_AXIS_TUSER_WIDTH(1),
+ .C_AXIS_SIGNAL_SET('B00000000000000000000000000011011)
+ ) inst (
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .aclken(1'H1),
+ .s_axis_tvalid(s_axis_tvalid),
+ .s_axis_tready(s_axis_tready),
+ .s_axis_tdata(s_axis_tdata),
+ .s_axis_tstrb(32'HFFFFFFFF),
+ .s_axis_tkeep(s_axis_tkeep),
+ .s_axis_tlast(s_axis_tlast),
+ .s_axis_tid(1'H0),
+ .s_axis_tdest(1'H0),
+ .s_axis_tuser(1'H0),
+ .m_axis_tvalid(m_axis_tvalid),
+ .m_axis_tready(m_axis_tready),
+ .m_axis_tdata(m_axis_tdata),
+ .m_axis_tstrb(),
+ .m_axis_tkeep(m_axis_tkeep),
+ .m_axis_tlast(m_axis_tlast),
+ .m_axis_tid(),
+ .m_axis_tdest(),
+ .m_axis_tuser()
+ );
+endmodule
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/synth/axis_dwidth_converter_256_64.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/synth/axis_dwidth_converter_256_64.v
new file mode 100644
index 0000000000000000000000000000000000000000..6e823117499814ccf0bba77ead79048b556bbf77
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_256_64/synth/axis_dwidth_converter_256_64.v
@@ -0,0 +1,133 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
+// IP Revision: 16
+
+(* X_CORE_INFO = "axis_dwidth_converter_v1_1_16_axis_dwidth_converter,Vivado 2018.2" *)
+(* CHECK_LICENSE_TYPE = "axis_dwidth_converter_256_64,axis_dwidth_converter_v1_1_16_axis_dwidth_converter,{}" *)
+(* CORE_GENERATION_INFO = "axis_dwidth_converter_256_64,axis_dwidth_converter_v1_1_16_axis_dwidth_converter,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_dwidth_converter,x_ipVersion=1.1,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_S_AXIS_TDATA_WIDTH=256,C_M_AXIS_TDATA_WIDTH=64,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_S_AXIS_TUSER_WIDTH=1,C_M_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000011011}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module axis_dwidth_converter_256_64 (
+ aclk,
+ aresetn,
+ s_axis_tvalid,
+ s_axis_tready,
+ s_axis_tdata,
+ s_axis_tkeep,
+ s_axis_tlast,
+ m_axis_tvalid,
+ m_axis_tready,
+ m_axis_tdata,
+ m_axis_tkeep,
+ m_axis_tlast
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, PHASE 0.000" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
+input wire s_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
+output wire s_axis_tready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
+input wire [255 : 0] s_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
+input wire [31 : 0] s_axis_tkeep;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
+input wire s_axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
+output wire m_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
+input wire m_axis_tready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
+output wire [63 : 0] m_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
+output wire [7 : 0] m_axis_tkeep;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
+output wire m_axis_tlast;
+
+ axis_dwidth_converter_v1_1_16_axis_dwidth_converter #(
+ .C_FAMILY("virtexuplus"),
+ .C_S_AXIS_TDATA_WIDTH(256),
+ .C_M_AXIS_TDATA_WIDTH(64),
+ .C_AXIS_TID_WIDTH(1),
+ .C_AXIS_TDEST_WIDTH(1),
+ .C_S_AXIS_TUSER_WIDTH(1),
+ .C_M_AXIS_TUSER_WIDTH(1),
+ .C_AXIS_SIGNAL_SET('B00000000000000000000000000011011)
+ ) inst (
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .aclken(1'H1),
+ .s_axis_tvalid(s_axis_tvalid),
+ .s_axis_tready(s_axis_tready),
+ .s_axis_tdata(s_axis_tdata),
+ .s_axis_tstrb(32'HFFFFFFFF),
+ .s_axis_tkeep(s_axis_tkeep),
+ .s_axis_tlast(s_axis_tlast),
+ .s_axis_tid(1'H0),
+ .s_axis_tdest(1'H0),
+ .s_axis_tuser(1'H0),
+ .m_axis_tvalid(m_axis_tvalid),
+ .m_axis_tready(m_axis_tready),
+ .m_axis_tdata(m_axis_tdata),
+ .m_axis_tstrb(),
+ .m_axis_tkeep(m_axis_tkeep),
+ .m_axis_tlast(m_axis_tlast),
+ .m_axis_tid(),
+ .m_axis_tdest(),
+ .m_axis_tuser()
+ );
+endmodule
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.veo b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.veo
new file mode 100644
index 0000000000000000000000000000000000000000..ca77d43b4906d01f068e7006cca85932677b4897
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.veo
@@ -0,0 +1,76 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
+// IP Revision: 16
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+axis_dwidth_converter_64_256 your_instance_name (
+ .aclk(aclk), // input wire aclk
+ .aresetn(aresetn), // input wire aresetn
+ .s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
+ .s_axis_tready(s_axis_tready), // output wire s_axis_tready
+ .s_axis_tdata(s_axis_tdata), // input wire [63 : 0] s_axis_tdata
+ .s_axis_tkeep(s_axis_tkeep), // input wire [7 : 0] s_axis_tkeep
+ .s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast
+ .m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
+ .m_axis_tready(m_axis_tready), // input wire m_axis_tready
+ .m_axis_tdata(m_axis_tdata), // output wire [255 : 0] m_axis_tdata
+ .m_axis_tkeep(m_axis_tkeep), // output wire [31 : 0] m_axis_tkeep
+ .m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file axis_dwidth_converter_64_256.v when simulating
+// the core, axis_dwidth_converter_64_256. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.vho b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.vho
new file mode 100644
index 0000000000000000000000000000000000000000..edbbf75b9a5409eb99f0c03285b5b802a88ac79e
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.vho
@@ -0,0 +1,97 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
+-- IP Revision: 16
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT axis_dwidth_converter_64_256
+ PORT (
+ aclk : IN STD_LOGIC;
+ aresetn : IN STD_LOGIC;
+ s_axis_tvalid : IN STD_LOGIC;
+ s_axis_tready : OUT STD_LOGIC;
+ s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+ s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ s_axis_tlast : IN STD_LOGIC;
+ m_axis_tvalid : OUT STD_LOGIC;
+ m_axis_tready : IN STD_LOGIC;
+ m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+ m_axis_tkeep : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ m_axis_tlast : OUT STD_LOGIC
+ );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : axis_dwidth_converter_64_256
+ PORT MAP (
+ aclk => aclk,
+ aresetn => aresetn,
+ s_axis_tvalid => s_axis_tvalid,
+ s_axis_tready => s_axis_tready,
+ s_axis_tdata => s_axis_tdata,
+ s_axis_tkeep => s_axis_tkeep,
+ s_axis_tlast => s_axis_tlast,
+ m_axis_tvalid => m_axis_tvalid,
+ m_axis_tready => m_axis_tready,
+ m_axis_tdata => m_axis_tdata,
+ m_axis_tkeep => m_axis_tkeep,
+ m_axis_tlast => m_axis_tlast
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file axis_dwidth_converter_64_256.vhd when simulating
+-- the core, axis_dwidth_converter_64_256. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.xci b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.xci
new file mode 100644
index 0000000000000000000000000000000000000000..ebb938e28fd4b85f7d5855a0f018c34eb6ce6038
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.xci
@@ -0,0 +1,102 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>axis_dwidth_converter_64_256</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_dwidth_converter" spirit:version="1.1"/>
+ <spirit:configurableElementValues>
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+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_BUSIF"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_RESET"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.FREQ_HZ">10000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RSTIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_SIGNAL_SET">0b00000000000000000000000000011011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH">256</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_TUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_TUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axis_dwidth_converter_64_256</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_MI_TKEEP">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TLAST">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TREADY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_TDATA_NUM_BYTES">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_TDATA_NUM_BYTES">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcvu3p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvc1517</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_MI_TKEEP" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TKEEP" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TLAST" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.xml b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2ae41892d08edd12cd9e87e4c0fe5243f50ad90d
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256.xml
@@ -0,0 +1,1525 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>customized_ip</spirit:library>
+ <spirit:name>axis_dwidth_converter_64_256</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>S_AXIS</spirit:name>
+ <spirit:displayName>S_AXIS</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TKEEP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tkeep</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TLAST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tlast</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDEST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tdest</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axis_tuser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
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+ <spirit:name>TDATA_NUM_BYTES</spirit:name>
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+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>TDEST_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
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+ </spirit:parameter>
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+ <spirit:name>TID_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
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+ <xilinx:parameterInfo>
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+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>TUSER_WIDTH</spirit:name>
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+ <xilinx:parameterInfo>
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+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_TREADY</spirit:name>
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+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_TSTRB</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>HAS_TKEEP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:name>HAS_TLAST</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
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+ <spirit:vendorExtensions>
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+ </spirit:vendorExtensions>
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+ <spirit:name>CLK_DOMAIN</spirit:name>
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+ <spirit:vendorExtensions>
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+ </spirit:busInterface>
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+ <spirit:name>M_AXIS</spirit:name>
+ <spirit:displayName>M_AXIS</spirit:displayName>
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+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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+ <spirit:logicalPort>
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+ </spirit:logicalPort>
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+ <spirit:name>m_axis_tready</spirit:name>
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+ <spirit:name>m_axis_tdest</spirit:name>
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+ <spirit:name>TUSER_WIDTH</spirit:name>
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+ <spirit:vendorExtensions>
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+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
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+ <spirit:name>TUSER_BITS_PER_BYTE</spirit:name>
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+ <spirit:name>HAS_TREADY</spirit:name>
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+ <spirit:name>HAS_TLAST</spirit:name>
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+ </xilinx:enablement>
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+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_TKEEP</spirit:name>
+ <spirit:displayName>Enable TKEEP</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_TKEEP" spirit:choiceRef="choice_pairs_37189c7b" spirit:order="10">1</spirit:value>
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+ <spirit:parameter>
+ <spirit:name>HAS_ACLKEN</spirit:name>
+ <spirit:displayName>Enable ACLKEN</spirit:displayName>
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+ <spirit:name>HAS_MI_TKEEP</spirit:name>
+ <spirit:displayName>Enable MI TKEEP</spirit:displayName>
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+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_dwidth_converter_64_256</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:displayName>AXI4-Stream Data Width Converter</xilinx:displayName>
+ <xilinx:xpmLibraries>
+ <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+ <xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
+ </xilinx:xpmLibraries>
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diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256_ooc.xdc b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256_ooc.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..fe7ad213da7a632d1930850f800954c298405df6
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/axis_dwidth_converter_64_256_ooc.xdc
@@ -0,0 +1,57 @@
+# (c) Copyright 2012-2022 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 100 -name aclk [get_ports aclk]
+
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/doc/axis_dwidth_converter_v1_1_changelog.txt b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/doc/axis_dwidth_converter_v1_1_changelog.txt
new file mode 100755
index 0000000000000000000000000000000000000000..c45ae2488b06b3d2d240826a0df9a7d4b8b5b874
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/doc/axis_dwidth_converter_v1_1_changelog.txt
@@ -0,0 +1,161 @@
+2018.2:
+ * Version 1.1 (Rev. 16)
+ * Revision change in one or more subcores
+
+2018.1:
+ * Version 1.1 (Rev. 15)
+ * General: Update internal register slice instantiation to tie-off unused input clock aclk2x.
+ * General: Change fsm encoding and remove unnecessary combinatorial reset tie-off on output valid/ready signals.
+ * General: Update initial values on register declarations to match reset values for reset-less operation.
+ * Revision change in one or more subcores
+
+2017.4:
+ * Version 1.1 (Rev. 14)
+ * Revision change in one or more subcores
+
+2017.3:
+ * Version 1.1 (Rev. 13)
+ * Initializing Valid/Ready Outputs to zero before reset kicks in
+ * Revision change in one or more subcores
+
+2017.2:
+ * Version 1.1 (Rev. 12)
+ * Revision change in one or more subcores
+
+2017.1:
+ * Version 1.1 (Rev. 11)
+ * Revision change in one or more subcores
+
+2016.4:
+ * Version 1.1 (Rev. 10)
+ * Revision change in one or more subcores
+
+2016.3:
+ * Version 1.1 (Rev. 9)
+ * Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Revision change in one or more subcores
+
+2016.2:
+ * Version 1.1 (Rev. 8)
+ * Revision change in one or more subcores
+
+2016.1:
+ * Version 1.1 (Rev. 7)
+ * Changes to HDL library management to support Vivado IP simulation library
+ * Revision change in one or more subcores
+
+2015.4.2:
+ * Version 1.1 (Rev. 6)
+ * No changes
+
+2015.4.1:
+ * Version 1.1 (Rev. 6)
+ * No changes
+
+2015.4:
+ * Version 1.1 (Rev. 6)
+ * Revision change in one or more subcores
+
+2015.3:
+ * Version 1.1 (Rev. 5)
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Configurations where there is non-multiple tdata width conversion (e.g., 2:3, 4:3, etc), no TKEEP and no TID, TDEST or TLAST signals present were found to be adding the TKEEP signal with all bits tied to LOW to the output M_AXIS interface. The TKEEP output can be ignored in this configuration. While the TKEEP is not needed, it has been kept to not break backwards compatibility and the vector is now being driven HIGH to produce a valid output. Configurations that require an upsizer (more than 1 input transfer is accumulated into 1 or more output transfers) and have TID/TDEST/TLAST and no TKEEP, will still produce a TKEEP. The TKEEP in this instance is not always tied HIGH and must be monitored if the input stream is not conditioned to ensure that TID/TDEST/TLAST do not toggle during accumulation.
+ * Revision change in one or more subcores
+
+2015.2.1:
+ * Version 1.1 (Rev. 4)
+ * No changes
+
+2015.2:
+ * Version 1.1 (Rev. 4)
+ * No changes
+
+2015.1:
+ * Version 1.1 (Rev. 4)
+ * The support status for Kintex UltraScale is changed from Pre-Production to Production.
+ * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF
+
+2014.4.1:
+ * Version 1.1 (Rev. 3)
+ * No changes
+
+2014.4:
+ * Version 1.1 (Rev. 3)
+ * Architecture support updated
+
+2014.3:
+ * Version 1.1 (Rev. 2)
+ * No changes
+
+2014.2:
+ * Version 1.1 (Rev. 2)
+ * No changes
+
+2014.1:
+ * Version 1.1 (Rev. 2)
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 1.1 (Rev. 1)
+ * Kintex UltraScale Pre-Production support
+
+2013.3:
+ * Version 1.1
+ * Added example design
+ * Initial default value for maximum range of TUSER bits per num TDATA bytes changed from 32 to 2048 to correspond with a TDATA number of bytes of 2. Absolute TUSER width limit is 4096 bits wide.
+ * Reduced warnings in synthesis and simulation
+
+2013.2:
+ * Version 1.0 (Rev. 1)
+ * Architecture support updated
+
+2013.1:
+ * Version 1.0
+ * Native Vivado Release
+ * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
+
+(c) Copyright 2012 - 2018 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_dwidth_converter_v1_1_vl_rfs.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_dwidth_converter_v1_1_vl_rfs.v
new file mode 100755
index 0000000000000000000000000000000000000000..cc0642eda603f420dafc4089e5a7c66dba2106d8
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_dwidth_converter_v1_1_vl_rfs.v
@@ -0,0 +1,1172 @@
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// axisc_downsizer
+// Convert from SI data width > MI datawidth.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_dwidth_converter_v1_1_16_axisc_downsizer #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_S_AXIS_TDATA_WIDTH = 96,
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ parameter integer C_AXIS_TID_WIDTH = 1,
+ parameter integer C_AXIS_TDEST_WIDTH = 1,
+ parameter integer C_S_AXIS_TUSER_WIDTH = 3,
+ parameter integer C_M_AXIS_TUSER_WIDTH = 1,
+ parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF ,
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ parameter integer C_RATIO = 3 // Should always be C_RATIO:1 (downsizer)
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // System Signals
+ input wire ACLK,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire S_AXIS_TVALID,
+ output wire S_AXIS_TREADY,
+ input wire [C_S_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TSTRB,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TKEEP,
+ input wire S_AXIS_TLAST,
+ input wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID,
+ input wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST,
+ input wire [C_S_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER,
+
+ // Master side
+ output wire M_AXIS_TVALID,
+ input wire M_AXIS_TREADY,
+ output wire [C_M_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TSTRB,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TKEEP,
+ output wire M_AXIS_TLAST,
+ output wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID,
+ output wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST,
+ output wire [C_M_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_S_AXIS_TSTRB_WIDTH = C_S_AXIS_TDATA_WIDTH/8;
+localparam P_M_AXIS_TSTRB_WIDTH = C_M_AXIS_TDATA_WIDTH/8;
+localparam P_RATIO_WIDTH = f_clogb2(C_RATIO);
+// State Machine possible states.
+localparam SM_RESET = 3'b000;
+localparam SM_IDLE = 3'b001;
+localparam SM_ACTIVE = 3'b010;
+localparam SM_END = 3'b011;
+localparam SM_END_TO_ACTIVE = 3'b110;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+(* fsm_encoding = "none" *) reg [2:0] state = SM_RESET;
+
+wire [C_RATIO-1:0] is_null;
+wire [C_RATIO-1:0] r0_is_end;
+
+wire [C_M_AXIS_TDATA_WIDTH-1:0] data_out;
+wire [P_M_AXIS_TSTRB_WIDTH-1:0] strb_out;
+wire [P_M_AXIS_TSTRB_WIDTH-1:0] keep_out;
+wire last_out;
+wire [C_AXIS_TID_WIDTH-1:0] id_out;
+wire [C_AXIS_TDEST_WIDTH-1:0] dest_out;
+wire [C_M_AXIS_TUSER_WIDTH-1:0] user_out;
+
+reg [C_S_AXIS_TDATA_WIDTH-1:0] r0_data;
+reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_strb;
+reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_keep;
+reg r0_last;
+reg [C_AXIS_TID_WIDTH-1:0] r0_id;
+reg [C_AXIS_TDEST_WIDTH-1:0] r0_dest;
+reg [C_S_AXIS_TUSER_WIDTH-1:0] r0_user;
+reg [C_RATIO-1:0] r0_is_null_r = {C_RATIO{1'b0}};
+
+wire r0_load;
+
+reg [C_M_AXIS_TDATA_WIDTH-1:0] r1_data;
+reg [P_M_AXIS_TSTRB_WIDTH-1:0] r1_strb;
+reg [P_M_AXIS_TSTRB_WIDTH-1:0] r1_keep;
+reg r1_last;
+reg [C_AXIS_TID_WIDTH-1:0] r1_id;
+reg [C_AXIS_TDEST_WIDTH-1:0] r1_dest;
+reg [C_M_AXIS_TUSER_WIDTH-1:0] r1_user;
+
+wire r1_load;
+
+reg [P_RATIO_WIDTH-1:0] r0_out_sel_r = {P_RATIO_WIDTH{1'b0}};
+wire [P_RATIO_WIDTH-1:0] r0_out_sel_ns;
+wire sel_adv;
+reg [P_RATIO_WIDTH-1:0] r0_out_sel_next_r = {P_RATIO_WIDTH{1'b0}} + 1'b1;
+wire [P_RATIO_WIDTH-1:0] r0_out_sel_next_ns;
+reg xfer_is_end;
+reg next_xfer_is_end;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+// S Ready/M Valid outputs are encoded in the current state.
+assign S_AXIS_TREADY = state[0];
+assign M_AXIS_TVALID = state[1];
+
+// State machine controls M_AXIS_TVALID and S_AXIS_TREADY, and loading
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ state <= SM_RESET;
+ end else if (ACLKEN) begin
+ case (state)
+ SM_RESET: begin
+ state <= SM_IDLE;
+ end
+
+ // No transactions
+ SM_IDLE: begin
+ if (S_AXIS_TVALID) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_IDLE;
+ end
+ end
+
+ // Active entry in holding register r0
+ SM_ACTIVE: begin
+ if (M_AXIS_TREADY & r0_is_end[0]) begin
+ state <= SM_IDLE;
+ end
+ else if (M_AXIS_TREADY & next_xfer_is_end) begin
+ state <= SM_END;
+ end
+ else begin
+ state <= SM_ACTIVE;
+ end
+ end
+
+ // Entry in last transfer register r1.
+ SM_END: begin
+ if (M_AXIS_TREADY & S_AXIS_TVALID) begin
+ state <= SM_ACTIVE;
+ end
+ else if (M_AXIS_TREADY & ~S_AXIS_TVALID) begin
+ state <= SM_IDLE;
+ end
+ else if (~M_AXIS_TREADY & S_AXIS_TVALID) begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ else begin
+ state <= SM_END;
+ end
+ end
+
+ SM_END_TO_ACTIVE: begin
+ if (M_AXIS_TREADY) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ end
+
+ default: begin
+ state <= SM_IDLE;
+ end
+
+ endcase // case (state)
+ end
+end
+
+// Algorithm to figure out which beat is the last non-null transfer. Split into 2 steps.
+// 1) Figuring out which output transfers are null before storing in r0.
+// (cycle steal to reduce critical path).
+// 2) For transfer X, if transfer X+1 to transfer C_RATIO-1 is null, then transfer
+// X is the new END transfer for the split. Transfer C_RATIO-1 is always marked
+// as END.
+genvar i;
+generate
+ if (C_AXIS_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep_is_enabled
+ for (i = 0; i < C_RATIO-1; i = i + 1) begin : gen_is_null
+ // 1)
+ assign is_null[i] = ~(|S_AXIS_TKEEP[i*P_M_AXIS_TSTRB_WIDTH +: P_M_AXIS_TSTRB_WIDTH]);
+ // 2)
+ assign r0_is_end[i] = (&r0_is_null_r[C_RATIO-1:i+1]);
+ end
+ assign is_null[C_RATIO-1] = ~(|S_AXIS_TKEEP[(C_RATIO-1)*P_M_AXIS_TSTRB_WIDTH +: P_M_AXIS_TSTRB_WIDTH]);
+ assign r0_is_end[C_RATIO-1] = 1'b1;
+ end
+ else begin : gen_tkeep_is_disabled
+ assign is_null = {C_RATIO{1'b0}};
+ assign r0_is_end = {1'b1, {C_RATIO-1{1'b0}}};
+ end
+endgenerate
+
+assign M_AXIS_TDATA = data_out[0+:C_M_AXIS_TDATA_WIDTH];
+assign M_AXIS_TSTRB = strb_out[0+:P_M_AXIS_TSTRB_WIDTH];
+assign M_AXIS_TKEEP = keep_out[0+:P_M_AXIS_TSTRB_WIDTH];
+assign M_AXIS_TLAST = last_out;
+assign M_AXIS_TID = id_out[0+:C_AXIS_TID_WIDTH];
+assign M_AXIS_TDEST = dest_out[0+:C_AXIS_TDEST_WIDTH];
+assign M_AXIS_TUSER = user_out[0+:C_M_AXIS_TUSER_WIDTH];
+
+// Select data output by shifting data right, upper most datum is always from r1
+assign data_out = {r1_data, r0_data[0+:C_M_AXIS_TDATA_WIDTH*(C_RATIO-1)]} >> (C_M_AXIS_TDATA_WIDTH*r0_out_sel_r);
+assign strb_out = {r1_strb, r0_strb[0+:P_M_AXIS_TSTRB_WIDTH*(C_RATIO-1)]} >> (P_M_AXIS_TSTRB_WIDTH*r0_out_sel_r);
+assign keep_out = {r1_keep, r0_keep[0+:P_M_AXIS_TSTRB_WIDTH*(C_RATIO-1)]} >> (P_M_AXIS_TSTRB_WIDTH*r0_out_sel_r);
+assign last_out = (state == SM_END || state == SM_END_TO_ACTIVE) ? r1_last : r0_last & r0_is_end[0];
+assign id_out = (state == SM_END || state == SM_END_TO_ACTIVE) ? r1_id : r0_id;
+assign dest_out = (state == SM_END || state == SM_END_TO_ACTIVE) ? r1_dest : r0_dest;
+assign user_out = {r1_user, r0_user[0+:C_M_AXIS_TUSER_WIDTH*(C_RATIO-1)]} >> (C_M_AXIS_TUSER_WIDTH*r0_out_sel_r);
+
+// First register stores the incoming transfer.
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ r0_data <= r0_load ? S_AXIS_TDATA : r0_data;
+ r0_strb <= r0_load ? S_AXIS_TSTRB : r0_strb;
+ r0_keep <= r0_load ? S_AXIS_TKEEP : r0_keep;
+ r0_last <= r0_load ? S_AXIS_TLAST : r0_last;
+ r0_id <= r0_load ? S_AXIS_TID : r0_id ;
+ r0_dest <= r0_load ? S_AXIS_TDEST : r0_dest;
+ r0_user <= r0_load ? S_AXIS_TUSER : r0_user;
+ end
+end
+
+// r0_is_null_r must always be set to known values to avoid x propagations.
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ r0_is_null_r <= {C_RATIO{1'b0}};
+ end
+ else if (ACLKEN) begin
+ r0_is_null_r <= r0_load & S_AXIS_TVALID ? is_null : r0_is_null_r;
+ end
+end
+
+assign r0_load = (state == SM_IDLE) || (state == SM_END);
+// Second register only stores a single slice of r0.
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ r1_data <= r1_load ? r0_data >> (C_M_AXIS_TDATA_WIDTH*r0_out_sel_next_r) : r1_data;
+ r1_strb <= r1_load ? r0_strb >> (P_M_AXIS_TSTRB_WIDTH*r0_out_sel_next_r) : r1_strb;
+ r1_keep <= r1_load ? r0_keep >> (P_M_AXIS_TSTRB_WIDTH*r0_out_sel_next_r) : r1_keep;
+ r1_last <= r1_load ? r0_last : r1_last;
+ r1_id <= r1_load ? r0_id : r1_id ;
+ r1_dest <= r1_load ? r0_dest : r1_dest;
+ r1_user <= r1_load ? r0_user >> (C_M_AXIS_TUSER_WIDTH*r0_out_sel_next_r) : r1_user;
+ end
+end
+
+assign r1_load = (state == SM_ACTIVE);
+
+// Counter to select which datum to send.
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ r0_out_sel_r <= {P_RATIO_WIDTH{1'b0}};
+ end else if (ACLKEN) begin
+ r0_out_sel_r <= r0_out_sel_ns;
+ end
+end
+
+assign r0_out_sel_ns = (xfer_is_end & sel_adv) || (state == SM_IDLE) ? {P_RATIO_WIDTH{1'b0}}
+ : next_xfer_is_end & sel_adv ? C_RATIO[P_RATIO_WIDTH-1:0]-1'b1
+ : sel_adv ? r0_out_sel_next_r : r0_out_sel_r;
+
+assign sel_adv = M_AXIS_TREADY;
+
+
+// Count ahead to the next value
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ r0_out_sel_next_r <= {P_RATIO_WIDTH{1'b0}} + 1'b1;
+ end else if (ACLKEN) begin
+ r0_out_sel_next_r <= r0_out_sel_next_ns;
+ end
+end
+
+assign r0_out_sel_next_ns = (xfer_is_end & sel_adv) || (state == SM_IDLE) ? {P_RATIO_WIDTH{1'b0}} + 1'b1
+ : ~next_xfer_is_end & sel_adv ? r0_out_sel_next_r + 1'b1
+ : r0_out_sel_next_r;
+
+always @(*) begin
+ xfer_is_end = r0_is_end[r0_out_sel_r];
+end
+
+always @(*) begin
+ next_xfer_is_end = r0_is_end[r0_out_sel_next_r];
+end
+
+endmodule // axisc_downsizer
+
+`default_nettype wire
+
+
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// axisc_downsizer
+// Convert from SI data width < MI datawidth.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_dwidth_converter_v1_1_16_axisc_upsizer #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32,
+ parameter integer C_M_AXIS_TDATA_WIDTH = 96,
+ parameter integer C_AXIS_TID_WIDTH = 1,
+ parameter integer C_AXIS_TDEST_WIDTH = 1,
+ parameter integer C_S_AXIS_TUSER_WIDTH = 1,
+ parameter integer C_M_AXIS_TUSER_WIDTH = 3,
+ parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF ,
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ parameter integer C_RATIO = 3 // Should always be 1:C_RATIO (upsizer)
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // System Signals
+ input wire ACLK,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire S_AXIS_TVALID,
+ output wire S_AXIS_TREADY,
+ input wire [C_S_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TSTRB,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TKEEP,
+ input wire S_AXIS_TLAST,
+ input wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID,
+ input wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST,
+ input wire [C_S_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER,
+
+ // Master side
+ output wire M_AXIS_TVALID,
+ input wire M_AXIS_TREADY,
+ output wire [C_M_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TSTRB,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TKEEP,
+ output wire M_AXIS_TLAST,
+ output wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID,
+ output wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST,
+ output wire [C_M_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_READY_EXIST = C_AXIS_SIGNAL_SET[0];
+localparam P_DATA_EXIST = C_AXIS_SIGNAL_SET[1];
+localparam P_STRB_EXIST = C_AXIS_SIGNAL_SET[2];
+localparam P_KEEP_EXIST = C_AXIS_SIGNAL_SET[3];
+localparam P_LAST_EXIST = C_AXIS_SIGNAL_SET[4];
+localparam P_ID_EXIST = C_AXIS_SIGNAL_SET[5];
+localparam P_DEST_EXIST = C_AXIS_SIGNAL_SET[6];
+localparam P_USER_EXIST = C_AXIS_SIGNAL_SET[7];
+localparam P_S_AXIS_TSTRB_WIDTH = C_S_AXIS_TDATA_WIDTH/8;
+localparam P_M_AXIS_TSTRB_WIDTH = C_M_AXIS_TDATA_WIDTH/8;
+
+// State Machine possible states. Bits 1:0 used to encode output signals.
+// /--- M_AXIS_TVALID state
+// |/-- S_AXIS_TREADY state
+localparam SM_RESET = 3'b000; // De-assert Ready during reset
+localparam SM_IDLE = 3'b001; // R0 reg is empty
+localparam SM_ACTIVE = 3'b101; // R0 reg is active
+localparam SM_END = 3'b011; // R0 reg is empty and ACC reg is active
+localparam SM_END_TO_ACTIVE = 3'b010; // R0/ACC reg are both active.
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+(* fsm_encoding = "none" *)
+reg [2:0] state = SM_RESET;
+
+reg [C_M_AXIS_TDATA_WIDTH-1:0] acc_data;
+reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_strb;
+reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_keep;
+reg acc_last;
+reg [C_AXIS_TID_WIDTH-1:0] acc_id;
+reg [C_AXIS_TDEST_WIDTH-1:0] acc_dest;
+reg [C_M_AXIS_TUSER_WIDTH-1:0] acc_user;
+
+wire [C_RATIO-1:0] acc_reg_en;
+reg [C_RATIO-1:0] r0_reg_sel = {{C_RATIO-1{1'b0}},1'b1}; // 1-hot
+wire next_xfer_is_end;
+
+reg [C_S_AXIS_TDATA_WIDTH-1:0] r0_data;
+reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_strb;
+reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_keep;
+reg r0_last;
+reg [C_AXIS_TID_WIDTH-1:0] r0_id;
+reg [C_AXIS_TDEST_WIDTH-1:0] r0_dest;
+reg [C_S_AXIS_TUSER_WIDTH-1:0] r0_user;
+
+wire id_match;
+wire dest_match;
+wire id_dest_mismatch;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// S Ready/M Valid outputs are encoded in the current state.
+assign S_AXIS_TREADY = state[0];
+assign M_AXIS_TVALID = state[1];
+
+// State machine controls M_AXIS_TVALID and S_AXIS_TREADY, and loading
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ state <= SM_RESET;
+ end else if (ACLKEN) begin
+ case (state)
+ SM_RESET: begin
+ state <= SM_IDLE;
+ end
+
+ SM_IDLE: begin
+ if (S_AXIS_TVALID & id_dest_mismatch & ~r0_reg_sel[0]) begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ else if (S_AXIS_TVALID & next_xfer_is_end) begin
+ state <= SM_END;
+ end
+ else if (S_AXIS_TVALID) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_IDLE;
+ end
+ end
+
+ SM_ACTIVE: begin
+ if (S_AXIS_TVALID & (id_dest_mismatch | r0_last)) begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ else if ((~S_AXIS_TVALID & r0_last) | (S_AXIS_TVALID & next_xfer_is_end)) begin
+ state <= SM_END;
+ end
+ else if (S_AXIS_TVALID & ~next_xfer_is_end) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_IDLE;
+ end
+ end
+
+ SM_END: begin
+ if (M_AXIS_TREADY & S_AXIS_TVALID) begin
+ state <= SM_ACTIVE;
+ end
+ else if ( ~M_AXIS_TREADY & S_AXIS_TVALID) begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ else if ( M_AXIS_TREADY & ~S_AXIS_TVALID) begin
+ state <= SM_IDLE;
+ end
+ else begin
+ state <= SM_END;
+ end
+ end
+
+ SM_END_TO_ACTIVE: begin
+ if (M_AXIS_TREADY) begin
+ state <= SM_ACTIVE;
+ end
+ else begin
+ state <= SM_END_TO_ACTIVE;
+ end
+ end
+
+ default: begin
+ state <= SM_IDLE;
+ end
+
+ endcase // case (state)
+ end
+end
+
+
+assign M_AXIS_TDATA = acc_data;
+assign M_AXIS_TSTRB = acc_strb;
+assign M_AXIS_TKEEP = acc_keep;
+assign M_AXIS_TUSER = acc_user;
+
+generate
+ genvar i;
+ // DATA/USER/STRB/KEEP accumulators
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[0] ? r0_data
+ : acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
+ acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[0] ? r0_user
+ : acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
+ acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_strb
+ : acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_keep
+ : acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ end
+ end
+ for (i = 1; i < C_RATIO-1; i = i + 1) begin : gen_data_accumulator
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[i] ? r0_data
+ : acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
+ acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[i] ? r0_user
+ : acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
+ acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
+ : acc_reg_en[i] ? r0_strb : acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
+ : acc_reg_en[i] ? r0_keep : acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ end
+ end
+ end
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
+ ? S_AXIS_TDATA : acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
+ acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
+ ? S_AXIS_TUSER : acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
+ acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE | state == SM_IDLE))
+ ? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
+ ? S_AXIS_TSTRB : acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE| state == SM_IDLE))
+ ? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
+ ? S_AXIS_TKEEP : acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
+ end
+ end
+
+endgenerate
+
+assign acc_reg_en = (state == SM_ACTIVE) ? r0_reg_sel : {C_RATIO{1'b0}};
+
+// Accumulator selector (1 hot left barrel shifter)
+always @(posedge ACLK) begin
+ if (ARESET) begin
+ r0_reg_sel[0] <= 1'b1;
+ r0_reg_sel[1+:C_RATIO-1] <= {C_RATIO{1'b0}};
+ end else if (ACLKEN) begin
+ r0_reg_sel[0] <= M_AXIS_TVALID & M_AXIS_TREADY ? 1'b1
+ : (state == SM_ACTIVE) ? 1'b0 : r0_reg_sel[0];
+ r0_reg_sel[1+:C_RATIO-1] <= M_AXIS_TVALID & M_AXIS_TREADY ? {C_RATIO-1{1'b0}}
+ : (state == SM_ACTIVE) ? r0_reg_sel[0+:C_RATIO-1] : r0_reg_sel[1+:C_RATIO-1];
+ end
+end
+
+assign next_xfer_is_end = (r0_reg_sel[C_RATIO-2] && (state == SM_ACTIVE)) | r0_reg_sel[C_RATIO-1];
+
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ r0_data <= S_AXIS_TREADY ? S_AXIS_TDATA : r0_data;
+ r0_strb <= S_AXIS_TREADY ? S_AXIS_TSTRB : r0_strb;
+ r0_keep <= S_AXIS_TREADY ? S_AXIS_TKEEP : r0_keep;
+ r0_last <= (!P_LAST_EXIST) ? 1'b0 : S_AXIS_TREADY ? S_AXIS_TLAST : r0_last;
+ r0_id <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TID : r0_id;
+ r0_dest <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TDEST : r0_dest;
+ r0_user <= S_AXIS_TREADY ? S_AXIS_TUSER : r0_user;
+ end
+end
+
+assign M_AXIS_TLAST = acc_last;
+
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_last <= (state == SM_END | state == SM_END_TO_ACTIVE) ? acc_last :
+ (state == SM_ACTIVE & r0_last ) ? 1'b1 :
+ (id_dest_mismatch & (state == SM_IDLE)) ? 1'b0 :
+ (id_dest_mismatch & (state == SM_ACTIVE)) ? r0_last :
+ S_AXIS_TLAST;
+ end
+end
+
+assign M_AXIS_TID = acc_id;
+assign M_AXIS_TDEST = acc_dest;
+
+always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ acc_id <= acc_reg_en[0] ? r0_id : acc_id;
+ acc_dest <= acc_reg_en[0] ? r0_dest : acc_dest;
+ end
+end
+
+assign id_match = P_ID_EXIST ? (S_AXIS_TID == r0_id) : 1'b1;
+assign dest_match = P_DEST_EXIST ? (S_AXIS_TDEST == r0_dest) : 1'b1;
+
+assign id_dest_mismatch = (~id_match | ~dest_match) ? 1'b1 : 1'b0;
+
+endmodule // axisc_upsizer
+
+`default_nettype wire
+
+
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// axis_dwidth_converter
+// Converts data when C_S_AXIS_TDATA_WIDTH != C_M_AXIS_TDATA_WIDTH.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_dwidth_converter
+// register_slice (instantiated with upsizer)
+// axisc_upsizer
+// axisc_downsizer
+// register_slice (instantiated with downsizer)
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_dwidth_converter_v1_1_16_axis_dwidth_converter #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter C_FAMILY = "virtex7",
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32,
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ parameter integer C_AXIS_TID_WIDTH = 1,
+ parameter integer C_AXIS_TDEST_WIDTH = 1,
+ parameter integer C_S_AXIS_TUSER_WIDTH = 1,
+ parameter integer C_M_AXIS_TUSER_WIDTH = 1,
+ // Ratio of C_S_AXIS_TDATA_WIDTH : C_M_AXIS_TDATA_WIDTH must be the same as
+ // the ratio of C_S_AXIS_TUSER_WIDTH : C_M_AXIS_TUSER_WIDTH if USER signals are present.
+ parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present (Required)
+ // [1] => TDATA present (Required, used to calculate ratios)
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present (Required if TLAST, TID,
+ // TDEST present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // System Signals
+ input wire aclk,
+ input wire aresetn,
+ input wire aclken,
+
+ // Slave side
+ input wire s_axis_tvalid,
+ output wire s_axis_tready,
+ input wire [C_S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb,
+ input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep,
+ input wire s_axis_tlast,
+ input wire [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
+ input wire [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
+ input wire [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
+
+ // Master side
+ output wire m_axis_tvalid,
+ input wire m_axis_tready,
+ output wire [C_M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb,
+ output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep,
+ output wire m_axis_tlast,
+ output wire [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
+ output wire [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
+ output wire [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+// TKEEP required if TID/TLAST/TDEST signals enabled
+localparam [31:0] P_SS_TKEEP_REQUIRED = (C_AXIS_SIGNAL_SET & (G_MASK_SS_TID | G_MASK_SS_TDEST | G_MASK_SS_TLAST))
+ ? G_MASK_SS_TKEEP : 32'h0;
+// TREADY/TDATA must always be present
+localparam [31:0] P_AXIS_SIGNAL_SET = C_AXIS_SIGNAL_SET | G_MASK_SS_TREADY | G_MASK_SS_TDATA | P_SS_TKEEP_REQUIRED;
+localparam P_S_RATIO = f_lcm(C_S_AXIS_TDATA_WIDTH, C_M_AXIS_TDATA_WIDTH) / C_S_AXIS_TDATA_WIDTH;
+localparam P_M_RATIO = f_lcm(C_S_AXIS_TDATA_WIDTH, C_M_AXIS_TDATA_WIDTH) / C_M_AXIS_TDATA_WIDTH;
+localparam P_D2_TDATA_WIDTH = C_S_AXIS_TDATA_WIDTH * P_S_RATIO;
+// To protect against bad TUSER M/S ratios when not using TUSER, base all
+// TUSER widths off of the calculated ratios and the slave tuser input width.
+localparam P_D1_TUSER_WIDTH = C_AXIS_SIGNAL_SET[G_INDX_SS_TUSER] ? C_S_AXIS_TUSER_WIDTH : C_S_AXIS_TDATA_WIDTH/8;
+localparam P_D2_TUSER_WIDTH = P_D1_TUSER_WIDTH * P_S_RATIO;
+localparam P_D3_TUSER_WIDTH = P_D2_TUSER_WIDTH / P_M_RATIO;
+
+localparam P_D1_REG_CONFIG = 0; // Disable
+localparam P_D3_REG_CONFIG = 0; // Disable
+
+////////////////////////////////////////////////////////////////////////////////
+// DRCs
+////////////////////////////////////////////////////////////////////////////////
+// synthesis translate_off
+integer retval;
+integer retval_all;
+initial
+begin : DRC
+ retval_all = 0;
+ t_check_tdata_width(C_S_AXIS_TDATA_WIDTH, "C_S_AXIS_TDATA_WIDTH", "axis_dwidth_converter", G_TASK_SEVERITY_ERR, retval);
+ retval_all = retval_all | retval;
+
+ t_check_tdata_width(C_M_AXIS_TDATA_WIDTH, "C_M_AXIS_TDATA_WIDTH", "axis_dwidth_converter", G_TASK_SEVERITY_ERR, retval);
+ retval_all = retval_all | retval;
+ if (C_AXIS_SIGNAL_SET[G_INDX_SS_TUSER]) begin
+ t_check_tuser_width (
+ C_S_AXIS_TUSER_WIDTH, "C_S_AXIS_TUSER_WIDTH" ,
+ C_S_AXIS_TDATA_WIDTH, "C_S_AXIS_TDATA_WIDTH" ,
+ "axis_dwidth_converter", G_TASK_SEVERITY_ERR ,
+ retval
+ );
+ retval_all = retval_all | retval;
+ t_check_tuser_width(
+ C_M_AXIS_TUSER_WIDTH, "C_M_AXIS_TUSER_WIDTH",
+ C_M_AXIS_TDATA_WIDTH, "C_M_AXIS_TDATA_WIDTH",
+ "axis_dwidth_converter", G_TASK_SEVERITY_ERR,
+ retval
+ );
+ retval_all = retval_all | retval;
+ end
+ else begin
+ // No check
+ end
+ if (retval_all > 0) begin
+ $stop;
+ end else begin
+ // Do nothing
+ end
+
+
+end
+// synthesis translate_on
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+reg areset_r = 1'b0;
+
+// Tie-offs for required signals if not present on inputs
+wire tready_in;
+wire [C_S_AXIS_TDATA_WIDTH-1:0] tdata_in;
+wire [C_S_AXIS_TDATA_WIDTH/8-1:0] tkeep_in;
+wire [P_D1_TUSER_WIDTH-1:0] tuser_in;
+
+// Output of first register stage
+wire d1_valid;
+wire d1_ready;
+wire [C_S_AXIS_TDATA_WIDTH-1:0] d1_data;
+wire [C_S_AXIS_TDATA_WIDTH/8-1:0] d1_strb;
+wire [C_S_AXIS_TDATA_WIDTH/8-1:0] d1_keep;
+wire d1_last;
+wire [C_AXIS_TID_WIDTH-1:0] d1_id;
+wire [C_AXIS_TDEST_WIDTH-1:0] d1_dest;
+wire [P_D1_TUSER_WIDTH-1:0] d1_user;
+
+// Output of upsizer stage
+wire d2_valid;
+wire d2_ready;
+wire [P_D2_TDATA_WIDTH-1:0] d2_data;
+wire [P_D2_TDATA_WIDTH/8-1:0] d2_strb;
+wire [P_D2_TDATA_WIDTH/8-1:0] d2_keep;
+wire d2_last;
+wire [C_AXIS_TID_WIDTH-1:0] d2_id;
+wire [C_AXIS_TDEST_WIDTH-1:0] d2_dest;
+wire [P_D2_TUSER_WIDTH-1:0] d2_user;
+
+// Output of downsizer stage
+wire d3_valid;
+wire d3_ready;
+wire [C_M_AXIS_TDATA_WIDTH-1:0] d3_data;
+wire [C_M_AXIS_TDATA_WIDTH/8-1:0] d3_strb;
+wire [C_M_AXIS_TDATA_WIDTH/8-1:0] d3_keep;
+wire d3_last;
+wire [C_AXIS_TID_WIDTH-1:0] d3_id;
+wire [C_AXIS_TDEST_WIDTH-1:0] d3_dest;
+wire [P_D3_TUSER_WIDTH-1:0] d3_user;
+wire [P_D3_TUSER_WIDTH-1:0] m_axis_tuser_out;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+always @(posedge aclk) begin
+ areset_r <= ~aresetn;
+end
+
+// Tie-offs for required signals if not present on inputs
+assign tready_in = C_AXIS_SIGNAL_SET[G_INDX_SS_TREADY] ? m_axis_tready : 1'b1;
+assign tdata_in = C_AXIS_SIGNAL_SET[G_INDX_SS_TDATA] ? s_axis_tdata : {C_S_AXIS_TDATA_WIDTH{1'b0}};
+assign tkeep_in = C_AXIS_SIGNAL_SET[G_INDX_SS_TKEEP] ? s_axis_tkeep : {(C_S_AXIS_TDATA_WIDTH/8){1'b1}};
+assign tuser_in = C_AXIS_SIGNAL_SET[G_INDX_SS_TUSER] ? s_axis_tuser : {P_D1_TUSER_WIDTH{1'b1}};
+
+axis_register_slice_v1_1_17_axis_register_slice #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) ,
+ .C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_AXIS_TUSER_WIDTH ( P_D1_TUSER_WIDTH ) ,
+ .C_AXIS_SIGNAL_SET ( P_AXIS_SIGNAL_SET ) ,
+ .C_REG_CONFIG ( P_D1_REG_CONFIG )
+)
+axis_register_slice_0
+(
+ .aclk ( aclk ) ,
+ .aclk2x ( 1'b1 ) ,
+ .aclken ( aclken ) ,
+ .aresetn ( aresetn ) ,
+ .s_axis_tvalid ( s_axis_tvalid ) ,
+ .s_axis_tready ( s_axis_tready ) ,
+ .s_axis_tdata ( tdata_in ) ,
+ .s_axis_tstrb ( s_axis_tstrb ) ,
+ .s_axis_tkeep ( tkeep_in ) ,
+ .s_axis_tlast ( s_axis_tlast ) ,
+ .s_axis_tid ( s_axis_tid ) ,
+ .s_axis_tdest ( s_axis_tdest ) ,
+ .s_axis_tuser ( tuser_in ) ,
+ .m_axis_tvalid ( d1_valid ) ,
+ .m_axis_tready ( d1_ready ) ,
+ .m_axis_tdata ( d1_data ) ,
+ .m_axis_tstrb ( d1_strb ) ,
+ .m_axis_tkeep ( d1_keep ) ,
+ .m_axis_tlast ( d1_last ) ,
+ .m_axis_tid ( d1_id ) ,
+ .m_axis_tdest ( d1_dest ) ,
+ .m_axis_tuser ( d1_user )
+);
+
+
+generate
+ if (P_S_RATIO > 1) begin : gen_upsizer_conversion
+ axis_dwidth_converter_v1_1_16_axisc_upsizer #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_S_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) ,
+ .C_M_AXIS_TDATA_WIDTH ( P_D2_TDATA_WIDTH ) ,
+ .C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_S_AXIS_TUSER_WIDTH ( P_D1_TUSER_WIDTH ) ,
+ .C_M_AXIS_TUSER_WIDTH ( P_D2_TUSER_WIDTH ) ,
+ .C_AXIS_SIGNAL_SET ( P_AXIS_SIGNAL_SET ) ,
+ .C_RATIO ( P_S_RATIO )
+ )
+ axisc_upsizer_0 (
+ .ACLK ( aclk ) ,
+ .ARESET ( areset_r ) ,
+ .ACLKEN ( aclken ) ,
+ .S_AXIS_TVALID ( d1_valid ) ,
+ .S_AXIS_TREADY ( d1_ready ) ,
+ .S_AXIS_TDATA ( d1_data ) ,
+ .S_AXIS_TSTRB ( d1_strb ) ,
+ .S_AXIS_TKEEP ( d1_keep ) ,
+ .S_AXIS_TLAST ( d1_last ) ,
+ .S_AXIS_TID ( d1_id ) ,
+ .S_AXIS_TDEST ( d1_dest ) ,
+ .S_AXIS_TUSER ( d1_user ) ,
+ .M_AXIS_TVALID ( d2_valid ) ,
+ .M_AXIS_TREADY ( d2_ready ) ,
+ .M_AXIS_TDATA ( d2_data ) ,
+ .M_AXIS_TSTRB ( d2_strb ) ,
+ .M_AXIS_TKEEP ( d2_keep ) ,
+ .M_AXIS_TLAST ( d2_last ) ,
+ .M_AXIS_TID ( d2_id ) ,
+ .M_AXIS_TDEST ( d2_dest ) ,
+ .M_AXIS_TUSER ( d2_user )
+ );
+ end
+ else begin : gen_no_upsizer_passthru
+ assign d2_valid = d1_valid;
+ assign d1_ready = d2_ready;
+ assign d2_data = d1_data;
+ assign d2_strb = d1_strb;
+ assign d2_keep = d1_keep;
+ assign d2_last = d1_last;
+ assign d2_id = d1_id;
+ assign d2_dest = d1_dest;
+ assign d2_user = d1_user;
+ end
+ if (P_M_RATIO > 1) begin : gen_downsizer_conversion
+ axis_dwidth_converter_v1_1_16_axisc_downsizer #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_S_AXIS_TDATA_WIDTH ( P_D2_TDATA_WIDTH ) ,
+ .C_M_AXIS_TDATA_WIDTH ( C_M_AXIS_TDATA_WIDTH ) ,
+ .C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_S_AXIS_TUSER_WIDTH ( P_D2_TUSER_WIDTH ) ,
+ .C_M_AXIS_TUSER_WIDTH ( P_D3_TUSER_WIDTH ) ,
+ .C_AXIS_SIGNAL_SET ( P_AXIS_SIGNAL_SET ) ,
+ .C_RATIO ( P_M_RATIO )
+ )
+ axisc_downsizer_0 (
+ .ACLK ( aclk ) ,
+ .ARESET ( areset_r ) ,
+ .ACLKEN ( aclken ) ,
+ .S_AXIS_TVALID ( d2_valid ) ,
+ .S_AXIS_TREADY ( d2_ready ) ,
+ .S_AXIS_TDATA ( d2_data ) ,
+ .S_AXIS_TSTRB ( d2_strb ) ,
+ .S_AXIS_TKEEP ( d2_keep ) ,
+ .S_AXIS_TLAST ( d2_last ) ,
+ .S_AXIS_TID ( d2_id ) ,
+ .S_AXIS_TDEST ( d2_dest ) ,
+ .S_AXIS_TUSER ( d2_user ) ,
+ .M_AXIS_TVALID ( d3_valid ) ,
+ .M_AXIS_TREADY ( d3_ready ) ,
+ .M_AXIS_TDATA ( d3_data ) ,
+ .M_AXIS_TSTRB ( d3_strb ) ,
+ .M_AXIS_TKEEP ( d3_keep ) ,
+ .M_AXIS_TLAST ( d3_last ) ,
+ .M_AXIS_TID ( d3_id ) ,
+ .M_AXIS_TDEST ( d3_dest ) ,
+ .M_AXIS_TUSER ( d3_user )
+ );
+ end
+ else begin : gen_no_downsizer_passthru
+ assign d3_valid = d2_valid;
+ assign d2_ready = d3_ready;
+ assign d3_data = d2_data;
+ assign d3_strb = d2_strb;
+ assign d3_keep = d2_keep;
+ assign d3_last = d2_last;
+ assign d3_id = d2_id;
+ assign d3_dest = d2_dest;
+ assign d3_user = d2_user;
+ end
+endgenerate
+
+axis_register_slice_v1_1_17_axis_register_slice #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_AXIS_TDATA_WIDTH ( C_M_AXIS_TDATA_WIDTH ) ,
+ .C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_AXIS_TUSER_WIDTH ( P_D3_TUSER_WIDTH ) ,
+ .C_AXIS_SIGNAL_SET ( P_AXIS_SIGNAL_SET ) ,
+ .C_REG_CONFIG ( P_D3_REG_CONFIG )
+)
+axis_register_slice_1
+(
+ .aclk ( aclk ) ,
+ .aclk2x ( 1'b1 ) ,
+ .aclken ( aclken ) ,
+ .aresetn ( aresetn ) ,
+ .s_axis_tvalid ( d3_valid ) ,
+ .s_axis_tready ( d3_ready ) ,
+ .s_axis_tdata ( d3_data ) ,
+ .s_axis_tstrb ( d3_strb ) ,
+ .s_axis_tkeep ( d3_keep ) ,
+ .s_axis_tlast ( d3_last ) ,
+ .s_axis_tid ( d3_id ) ,
+ .s_axis_tdest ( d3_dest ) ,
+ .s_axis_tuser ( d3_user ) ,
+ .m_axis_tvalid ( m_axis_tvalid ) ,
+ .m_axis_tready ( tready_in ) ,
+ .m_axis_tdata ( m_axis_tdata ) ,
+ .m_axis_tstrb ( m_axis_tstrb ) ,
+ .m_axis_tkeep ( m_axis_tkeep ) ,
+ .m_axis_tlast ( m_axis_tlast ) ,
+ .m_axis_tid ( m_axis_tid ) ,
+ .m_axis_tdest ( m_axis_tdest ) ,
+ .m_axis_tuser ( m_axis_tuser_out )
+);
+
+assign m_axis_tuser = C_AXIS_SIGNAL_SET[G_INDX_SS_TUSER] ? m_axis_tuser_out[P_D3_TUSER_WIDTH-1:0]
+ : {C_M_AXIS_TUSER_WIDTH{1'bx}};
+
+endmodule // axis_dwidth_converter
+
+`default_nettype wire
+
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_infrastructure_v1_1_0.vh b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_infrastructure_v1_1_0.vh
new file mode 100755
index 0000000000000000000000000000000000000000..14d3524515efbc513cd40e85a11234164beb08ca
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_infrastructure_v1_1_0.vh
@@ -0,0 +1,337 @@
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+// Global Parameters:
+//
+// Functions:
+// f_clogb2
+// f_gcd
+// f_lcm
+// f_get_tdata_indx
+// f_get_tstrb_indx
+// f_get_tkeep_indx
+// f_get_tlast_indx
+// f_get_tid_indx
+// f_get_tdest_indx
+// f_get_tuser_indx
+// f_payload_width
+// Tasks:
+// t_display_tdata_error
+//--------------------------------------------------------------------------
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Global Parameters
+///////////////////////////////////////////////////////////////////////////////
+// Define Signal Set indices
+localparam G_INDX_SS_TREADY = 0;
+localparam G_INDX_SS_TDATA = 1;
+localparam G_INDX_SS_TSTRB = 2;
+localparam G_INDX_SS_TKEEP = 3;
+localparam G_INDX_SS_TLAST = 4;
+localparam G_INDX_SS_TID = 5;
+localparam G_INDX_SS_TDEST = 6;
+localparam G_INDX_SS_TUSER = 7;
+localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
+localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA;
+localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB;
+localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP;
+localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST;
+localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ;
+localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST;
+localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER;
+
+// Task DRC error levels
+localparam G_TASK_SEVERITY_ERR = 2;
+localparam G_TASK_SEVERITY_WARNING = 1;
+localparam G_TASK_SEVERITY_INFO = 0;
+
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Functions
+///////////////////////////////////////////////////////////////////////////////
+// ceiling logb2
+ function integer f_clogb2 (input integer size);
+ integer s;
+ begin
+ s = size;
+ s = s - 1;
+ for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
+ s = s >> 1;
+ end
+ endfunction // clogb2
+
+ // Calculates the Greatest Common Divisor between two integers using the
+ // euclidean algorithm.
+ function automatic integer f_gcd (
+ input integer a,
+ input integer b
+ );
+ begin : main
+ if (a == 0) begin
+ f_gcd = b;
+ end else if (b == 0) begin
+ f_gcd = a;
+ end else if (a > b) begin
+ f_gcd = f_gcd(a % b, b);
+ end else begin
+ f_gcd = f_gcd(a, b % a);
+ end
+ end
+ endfunction
+
+ // Calculates the Lowest Common Denominator between two integers
+ function integer f_lcm (
+ input integer a,
+ input integer b
+ );
+ begin : main
+ f_lcm = ( a / f_gcd(a, b)) * b;
+ end
+ endfunction
+
+ // Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tdata_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ f_get_tdata_indx = 0;
+ end
+ endfunction
+
+ // Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tstrb_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
+ // If TDATA exists, then add its width to its base to get the tstrb index
+ f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tkeep_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tlast_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tid_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tdest_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
+ end
+ endfunction
+
+ // Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
+ // signal is not enabled.
+ function integer f_get_tuser_indx (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
+ f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
+ end
+ endfunction
+
+ // Payload is the sum of all the AXIS signals present except for
+ // TREADY/TVALID
+ function integer f_payload_width (
+ input integer DAW, // TDATA Width
+ input integer IDW, // TID Width
+ input integer DEW, // TDEST Width
+ input integer USW, // TUSER Width
+ input [31:0] SST // Signal Set
+ );
+ begin : main
+ integer cur_indx;
+ cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
+ f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
+ // Ensure that the return value is never less than 1
+ f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
+ end
+ endfunction
+
+ task t_check_tdata_width(
+ input integer data_width,
+ input [8*80-1:0] var_name,
+ input [8*80-1:0] inst_name,
+ input integer severity_lvl,
+ output integer ret_val
+ );
+ // Severity levels:
+ // 0 = INFO
+ // 1 = WARNING
+ // 2 = ERROR
+ begin : t_check_tdata_width
+ if (data_width%8 != 0) begin
+ // 000 1 2 3 4 5 6 7 8
+ // 012 0 0 0 0 0 0 0 0
+ if (severity_lvl >= 2) begin
+ $display("ERROR: %m::%s", inst_name);
+ end else if (severity_lvl == 1) begin
+ $display("WARNING: %m::%s", inst_name);
+ end else begin
+ $display("INFO: %m::%s", inst_name);
+ end
+ $display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
+ $display(" AXI4-Stream data width is only defined for byte multiples. See the ");
+ $display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
+ $display(" information.");
+ ret_val = 1;
+ end else begin
+ ret_val = 0;
+ end
+ end
+ endtask
+
+ task t_check_tuser_width(
+ input integer tuser_width,
+ input [8*80-1:0] tuser_name,
+ input integer tdata_width,
+ input [8*80-1:0] tdata_name,
+ input [8*80-1:0] inst_name,
+ input integer severity_lvl,
+ output integer ret_val
+ );
+ // Severity levels:
+ // 0 = INFO
+ // 1 = WARNING
+ // 2 = ERROR
+ begin : t_check_tuser_width
+ integer tdata_bytes;
+ tdata_bytes = tdata_width/8;
+ if ((tuser_width%tdata_bytes) != 0) begin
+ // 000 1 2 3 4 5 6 7 8
+ // 012 0 0 0 0 0 0 0 0
+ if (severity_lvl >= 2) begin
+ $display("ERROR: %m::%s", inst_name);
+ end else if (severity_lvl == 1) begin
+ $display("WARNING: %m::%s", inst_name);
+ end else begin
+ $display("INFO: %m::%s", inst_name);
+ end
+ $display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
+ $display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width);
+ $display(" TUSER width in this module is only defined when the TUSER is the");
+ $display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0");
+ $display(" Section 2.1, 2.3.3 and 2.8 for more information. ");
+ ret_val = 1;
+ end else begin
+ ret_val = 0;
+ end
+ end
+ endtask
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_infrastructure_v1_1_vl_rfs.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_infrastructure_v1_1_vl_rfs.v
new file mode 100755
index 0000000000000000000000000000000000000000..e44cf420621e47c17e00cae5f07e554fc7946430
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_infrastructure_v1_1_vl_rfs.v
@@ -0,0 +1,1324 @@
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//-----------------------------------------------------------------------------
+//
+// Description:
+// Optimized Mux using MUXF7/8.
+// Any mux ratio.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// mux_enc
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V
+`define AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_mux_enc #
+ (
+ parameter C_FAMILY = "rtl",
+ // FPGA Family. Current version: virtex6 or spartan6.
+ parameter integer C_RATIO = 4,
+ // Mux select ratio. Can be any binary value (>= 1)
+ parameter integer C_SEL_WIDTH = 2,
+ // Log2-ceiling of C_RATIO (>= 1)
+ parameter integer C_DATA_WIDTH = 1
+ // Data width for comparator (>= 1)
+ )
+ (
+ input wire [C_SEL_WIDTH-1:0] S,
+ input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
+ output wire [C_DATA_WIDTH-1:0] O,
+ input wire OE
+ );
+
+ wire [C_DATA_WIDTH-1:0] o_i;
+ genvar bit_cnt;
+
+ function [C_DATA_WIDTH-1:0] f_mux
+ (
+ input [C_SEL_WIDTH-1:0] s,
+ input [C_RATIO*C_DATA_WIDTH-1:0] a
+ );
+ integer i;
+ reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
+ begin
+ carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
+ for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
+ carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
+ carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
+ ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
+ end
+ f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
+ end
+ endfunction
+
+ function [C_DATA_WIDTH-1:0] f_mux4
+ (
+ input [1:0] s,
+ input [4*C_DATA_WIDTH-1:0] a
+ );
+ integer i;
+ reg [4*C_DATA_WIDTH-1:0] carry;
+ begin
+ carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
+ for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
+ carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
+ carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
+ ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
+ end
+ f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
+ end
+ endfunction
+
+ assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
+
+ generate
+ if ( C_RATIO < 2 ) begin : gen_bypass
+ assign o_i = A;
+ end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
+ assign o_i = f_mux(S, A);
+
+ end else begin : gen_fpga
+ wire [C_DATA_WIDTH-1:0] l;
+ wire [C_DATA_WIDTH-1:0] h;
+ wire [C_DATA_WIDTH-1:0] ll;
+ wire [C_DATA_WIDTH-1:0] lh;
+ wire [C_DATA_WIDTH-1:0] hl;
+ wire [C_DATA_WIDTH-1:0] hh;
+
+ case (C_RATIO)
+ 1, 5, 9, 13:
+ assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ 2, 6, 10, 14:
+ assign hh = S[0] ?
+ A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
+ 3, 7, 11, 15:
+ assign hh = S[1] ?
+ A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ (S[0] ?
+ A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
+ 4, 8, 12, 16:
+ assign hh = S[1] ?
+ (S[0] ?
+ A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
+ (S[0] ?
+ A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
+ 17:
+ assign hh = S[1] ?
+ (S[0] ?
+ A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
+ (S[0] ?
+ A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
+ A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
+ default:
+ assign hh = 0;
+ endcase
+
+ case (C_RATIO)
+ 5, 6, 7, 8: begin
+ assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+ for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
+ MUXF7 mux_s2_inst
+ (
+ .I0 (l[bit_cnt]),
+ .I1 (hh[bit_cnt]),
+ .S (S[2]),
+ .O (o_i[bit_cnt])
+ );
+ end
+ end
+
+ 9, 10, 11, 12: begin
+ assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+ assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
+ MUXF7 muxf_s2_low_inst
+ (
+ .I0 (ll[bit_cnt]),
+ .I1 (lh[bit_cnt]),
+ .S (S[2]),
+ .O (l[bit_cnt])
+ );
+ MUXF8 muxf_s3_inst
+ (
+ .I0 (l[bit_cnt]),
+ .I1 (hh[bit_cnt]),
+ .S (S[3]),
+ .O (o_i[bit_cnt])
+ );
+ end
+ end
+
+ 13,14,15,16: begin
+ assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+ assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
+ MUXF7 muxf_s2_low_inst
+ (
+ .I0 (ll[bit_cnt]),
+ .I1 (lh[bit_cnt]),
+ .S (S[2]),
+ .O (l[bit_cnt])
+ );
+ MUXF7 muxf_s2_hi_inst
+ (
+ .I0 (hl[bit_cnt]),
+ .I1 (hh[bit_cnt]),
+ .S (S[2]),
+ .O (h[bit_cnt])
+ );
+
+ MUXF8 muxf_s3_inst
+ (
+ .I0 (l[bit_cnt]),
+ .I1 (h[bit_cnt]),
+ .S (S[3]),
+ .O (o_i[bit_cnt])
+ );
+ end
+ end
+
+ 17: begin
+ assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
+ assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+ for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
+ MUXF7 muxf_s2_low_inst
+ (
+ .I0 (ll[bit_cnt]),
+ .I1 (lh[bit_cnt]),
+ .S (S[2]),
+ .O (l[bit_cnt])
+ );
+ MUXF7 muxf_s2_hi_inst
+ (
+ .I0 (hl[bit_cnt]),
+ .I1 (hh[bit_cnt]),
+ .S (S[2]),
+ .O (h[bit_cnt])
+ );
+ MUXF8 muxf_s3_inst
+ (
+ .I0 (l[bit_cnt]),
+ .I1 (h[bit_cnt]),
+ .S (S[3]),
+ .O (o_i[bit_cnt])
+ );
+ end
+ end
+
+ default: // If RATIO > 17, use RTL
+ assign o_i = f_mux(S, A);
+ endcase
+ end // gen_fpga
+ endgenerate
+endmodule
+
+`endif
+
+
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_infrastructure_v1_1_0_util_aclken_converter
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V
+`define AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_aclken_converter # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_PAYLOAD_WIDTH = 32,
+ parameter integer C_S_ACLKEN_CAN_TOGGLE = 1,
+ parameter integer C_M_ACLKEN_CAN_TOGGLE = 1
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // Slave side
+ input wire ACLK,
+ input wire ARESETN,
+
+ input wire S_ACLKEN,
+ input wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ input wire M_ACLKEN,
+ output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,
+ output wire M_VALID,
+ input wire M_READY
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+// State machine states
+localparam SM_NOT_READY = 3'b000;
+localparam SM_EMPTY = 3'b001;
+localparam SM_R0_NOT_READY = 3'b010;
+localparam SM_R0 = 3'b011;
+localparam SM_R1 = 3'b100;
+localparam SM_FULL = 3'b110;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire s_aclken_i;
+wire m_aclken_i;
+reg areset;
+
+reg [2:0] state = SM_NOT_READY;
+
+// r0 is the output register
+reg [C_PAYLOAD_WIDTH-1:0] r0;
+wire load_r0;
+wire load_r0_from_r1;
+
+// r1 is the overflow register
+reg [C_PAYLOAD_WIDTH-1:0] r1;
+wire load_r1;
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+assign s_aclken_i = C_S_ACLKEN_CAN_TOGGLE ? S_ACLKEN : 1'b1;
+assign m_aclken_i = C_M_ACLKEN_CAN_TOGGLE ? M_ACLKEN : 1'b1;
+
+always @(posedge ACLK) begin
+ areset <= ~ARESETN;
+end
+
+// Valid/Ready outputs encoded into state machine.
+assign S_READY = (state == SM_NOT_READY ) ? 1'b0 : state[0] ;
+assign M_VALID = (state == SM_NOT_READY ) ? 1'b0 : state[1];
+
+// State machine: Controls outputs and hold register state info
+always @(posedge ACLK) begin
+ if (areset) begin
+ state <= SM_NOT_READY;
+ end
+ else begin
+ case (state)
+ // De-assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied
+ SM_NOT_READY: begin
+ if (s_aclken_i) begin
+ state <= SM_EMPTY;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // Assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied
+ SM_EMPTY: begin
+ if (s_aclken_i & S_VALID & m_aclken_i) begin
+ state <= SM_R0;
+ end
+ else if (s_aclken_i & S_VALID & ~m_aclken_i) begin
+ state <= SM_R1;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // Assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied
+ SM_R0: begin
+ if ((m_aclken_i & M_READY) & ~(s_aclken_i & S_VALID)) begin
+ state <= SM_EMPTY;
+ end
+ else if (~(m_aclken_i & M_READY) & (s_aclken_i & S_VALID)) begin
+ state <= SM_FULL;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // De-assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied
+ SM_R0_NOT_READY: begin
+ if (s_aclken_i & m_aclken_i & M_READY) begin
+ state <= SM_EMPTY;
+ end
+ else if (~s_aclken_i & m_aclken_i & M_READY) begin
+ state <= SM_NOT_READY;
+ end
+ else if (s_aclken_i) begin
+ state <= SM_R0;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // De-assert s_ready, De-assert m_valid, R0 unoccupied, R1 occupied
+ SM_R1: begin
+ if (~s_aclken_i & m_aclken_i) begin
+ state <= SM_R0_NOT_READY;
+ end
+ else if (s_aclken_i & m_aclken_i) begin
+ state <= SM_R0;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ // De-assert s_ready, De-assert m_valid, R0 occupied, R1 occupied
+ SM_FULL: begin
+ if (~s_aclken_i & m_aclken_i & M_READY) begin
+ state <= SM_R0_NOT_READY;
+ end
+ else if (s_aclken_i & m_aclken_i & M_READY) begin
+ state <= SM_R0;
+ end
+ else begin
+ state <= state;
+ end
+ end
+
+ default: begin
+ state <= SM_NOT_READY;
+ end
+ endcase
+ end
+end
+
+assign M_PAYLOAD = r0;
+
+always @(posedge ACLK) begin
+ if (m_aclken_i) begin
+ r0 <= ~load_r0 ? r0 :
+ load_r0_from_r1 ? r1 :
+ S_PAYLOAD ;
+ end
+end
+
+assign load_r0 = (state == SM_EMPTY)
+ | (state == SM_R1)
+ | ((state == SM_R0) & M_READY)
+ | ((state == SM_FULL) & M_READY);
+
+assign load_r0_from_r1 = (state == SM_R1) | (state == SM_FULL);
+
+always @(posedge ACLK) begin
+ r1 <= ~load_r1 ? r1 : S_PAYLOAD;
+end
+
+assign load_r1 = (state == SM_EMPTY) | (state == SM_R0);
+
+
+endmodule // axis_infrastructure_v1_1_0_util_aclken_converter
+
+`default_nettype wire
+`endif
+
+
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+// Verilog-standard: Verilog 2001
+////////////////////////////////////////////////////////////
+//
+// Structure:
+// axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
+// axis_infrastructure_v1_1_0_util_axis2_vector
+// axis_infrastructure_v1_1_0_util_aclken_converter
+// axis_infrastructure_v1_1_0_util_vector2axis
+//
+////////////////////////////////////////////////////////////
+`ifndef axis_infrastructure_v1_1_0_UTIL_ACLKEN_CONVERTER_WRAPPER_V
+`define axis_infrastructure_v1_1_0_UTIL_ACLKEN_CONVERTER_WRAPPER_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_aclken_converter_wrapper # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_TDATA_WIDTH = 32,
+ parameter integer C_TID_WIDTH = 1,
+ parameter integer C_TDEST_WIDTH = 1,
+ parameter integer C_TUSER_WIDTH = 1,
+ parameter [31:0] C_SIGNAL_SET = 32'hFF,
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ parameter integer C_S_ACLKEN_CAN_TOGGLE = 1,
+ parameter integer C_M_ACLKEN_CAN_TOGGLE = 1
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // Slave side
+ input wire ACLK,
+ input wire ARESETN,
+ input wire S_ACLKEN,
+ input wire S_VALID,
+ output wire S_READY,
+ input wire [C_TDATA_WIDTH-1:0] S_TDATA,
+ input wire [C_TDATA_WIDTH/8-1:0] S_TSTRB,
+ input wire [C_TDATA_WIDTH/8-1:0] S_TKEEP,
+ input wire S_TLAST,
+ input wire [C_TID_WIDTH-1:0] S_TID,
+ input wire [C_TDEST_WIDTH-1:0] S_TDEST,
+ input wire [C_TUSER_WIDTH-1:0] S_TUSER,
+
+ input wire M_ACLKEN,
+ output wire M_VALID,
+ input wire M_READY,
+ output wire [C_TDATA_WIDTH-1:0] M_TDATA,
+ output wire [C_TDATA_WIDTH/8-1:0] M_TSTRB,
+ output wire [C_TDATA_WIDTH/8-1:0] M_TKEEP,
+ output wire M_TLAST,
+ output wire [C_TID_WIDTH-1:0] M_TID,
+ output wire [C_TDEST_WIDTH-1:0] M_TDEST,
+ output wire [C_TUSER_WIDTH-1:0] M_TUSER
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+localparam integer P_TPAYLOAD_WIDTH = f_payload_width(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire [P_TPAYLOAD_WIDTH-1:0] s_tpayload;
+wire [P_TPAYLOAD_WIDTH-1:0] m_tpayload;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+axis_infrastructure_v1_1_0_util_axis2vector #(
+ .C_TDATA_WIDTH ( C_TDATA_WIDTH ) ,
+ .C_TID_WIDTH ( C_TID_WIDTH ) ,
+ .C_TDEST_WIDTH ( C_TDEST_WIDTH ) ,
+ .C_TUSER_WIDTH ( C_TUSER_WIDTH ) ,
+ .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_SIGNAL_SET ( C_SIGNAL_SET )
+)
+util_axis2vector_0 (
+ .TDATA ( S_TDATA ) ,
+ .TSTRB ( S_TSTRB ) ,
+ .TKEEP ( S_TKEEP ) ,
+ .TLAST ( S_TLAST ) ,
+ .TID ( S_TID ) ,
+ .TDEST ( S_TDEST ) ,
+ .TUSER ( S_TUSER ) ,
+ .TPAYLOAD ( s_tpayload )
+);
+
+generate
+if (C_S_ACLKEN_CAN_TOGGLE | C_M_ACLKEN_CAN_TOGGLE) begin : gen_aclken_converter
+ axis_infrastructure_v1_1_0_util_aclken_converter #(
+ .C_PAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_S_ACLKEN_CAN_TOGGLE ( C_S_ACLKEN_CAN_TOGGLE ) ,
+ .C_M_ACLKEN_CAN_TOGGLE ( C_M_ACLKEN_CAN_TOGGLE )
+ )
+ s_util_aclken_converter_0 (
+ .ACLK ( ACLK ) ,
+ .ARESETN ( ARESETN ) ,
+ .S_ACLKEN ( S_ACLKEN ) ,
+ .S_PAYLOAD ( s_tpayload ) ,
+ .S_VALID ( S_VALID ) ,
+ .S_READY ( S_READY ) ,
+ .M_ACLKEN ( M_ACLKEN ) ,
+ .M_PAYLOAD ( m_tpayload ) ,
+ .M_VALID ( M_VALID ) ,
+ .M_READY ( M_READY )
+ );
+end
+else begin : gen_aclken_passthru
+ assign m_tpayload = s_tpayload;
+ assign M_VALID = S_VALID;
+ assign S_READY = M_READY;
+end
+endgenerate
+
+axis_infrastructure_v1_1_0_util_vector2axis #(
+ .C_TDATA_WIDTH ( C_TDATA_WIDTH ) ,
+ .C_TID_WIDTH ( C_TID_WIDTH ) ,
+ .C_TDEST_WIDTH ( C_TDEST_WIDTH ) ,
+ .C_TUSER_WIDTH ( C_TUSER_WIDTH ) ,
+ .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_SIGNAL_SET ( C_SIGNAL_SET )
+)
+util_vector2axis_0 (
+ .TPAYLOAD ( m_tpayload ) ,
+ .TDATA ( M_TDATA ) ,
+ .TSTRB ( M_TSTRB ) ,
+ .TKEEP ( M_TKEEP ) ,
+ .TLAST ( M_TLAST ) ,
+ .TID ( M_TID ) ,
+ .TDEST ( M_TDEST ) ,
+ .TUSER ( M_TUSER )
+);
+
+endmodule // axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
+
+`default_nettype wire
+`endif
+
+
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+// axis to vector
+// A generic module to merge all axis 'data' signals into one signal called payload.
+// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_infrastructure_v1_1_0_util_axis2vector
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
+`define AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_axis2vector #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_TDATA_WIDTH = 32,
+ parameter integer C_TID_WIDTH = 1,
+ parameter integer C_TDEST_WIDTH = 1,
+ parameter integer C_TUSER_WIDTH = 1,
+ parameter integer C_TPAYLOAD_WIDTH = 44,
+ parameter [31:0] C_SIGNAL_SET = 32'hFF
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // inputs
+ input wire [C_TDATA_WIDTH-1:0] TDATA,
+ input wire [C_TDATA_WIDTH/8-1:0] TSTRB,
+ input wire [C_TDATA_WIDTH/8-1:0] TKEEP,
+ input wire TLAST,
+ input wire [C_TID_WIDTH-1:0] TID,
+ input wire [C_TDEST_WIDTH-1:0] TDEST,
+ input wire [C_TUSER_WIDTH-1:0] TUSER,
+
+ // outputs
+ output wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+generate
+ if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
+ assign TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] = TDATA;
+ end else begin : no_gen_tdata
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
+ assign TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8] = TSTRB;
+ end else begin : no_gen_tstrb
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
+ assign TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8] = TKEEP;
+ end else begin : no_gen_tkeep
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
+ assign TPAYLOAD[P_TLAST_INDX+:1] = TLAST;
+ end else begin : no_gen_tlast
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
+ assign TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] = TID;
+ end else begin : no_gen_tid
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
+ assign TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] = TDEST;
+ end else begin : no_gen_tdest
+ // Do nothing
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
+ assign TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] = TUSER;
+ end else begin : no_gen_tuser
+ // Do nothing
+ end
+endgenerate
+endmodule
+
+`default_nettype wire
+`endif
+
+
+// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+// axis to vector
+// A generic module to unmerge all axis 'data' signals from payload.
+// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_infrastructure_v1_1_0_util_vector2axis
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
+`define AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_vector2axis #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_TDATA_WIDTH = 32,
+ parameter integer C_TID_WIDTH = 1,
+ parameter integer C_TDEST_WIDTH = 1,
+ parameter integer C_TUSER_WIDTH = 1,
+ parameter integer C_TPAYLOAD_WIDTH = 44,
+ parameter [31:0] C_SIGNAL_SET = 32'hFF
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // outputs
+ input wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD,
+
+ // inputs
+ output wire [C_TDATA_WIDTH-1:0] TDATA,
+ output wire [C_TDATA_WIDTH/8-1:0] TSTRB,
+ output wire [C_TDATA_WIDTH/8-1:0] TKEEP,
+ output wire TLAST,
+ output wire [C_TID_WIDTH-1:0] TID,
+ output wire [C_TDEST_WIDTH-1:0] TDEST,
+ output wire [C_TUSER_WIDTH-1:0] TUSER
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+ C_TDEST_WIDTH, C_TUSER_WIDTH,
+ C_SIGNAL_SET);
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+generate
+ if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
+ assign TDATA = TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] ;
+ end
+ else begin : no_gen_tdata
+ assign TDATA = {C_TDATA_WIDTH{1'b0}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
+ assign TSTRB = TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8];
+ end
+ else begin : no_gen_tstrb
+ assign TSTRB = {(C_TDATA_WIDTH/8){1'b0}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
+ assign TKEEP = TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8];
+ end
+ else begin : no_gen_tkeep
+ assign TKEEP = {(C_TDATA_WIDTH/8){1'b1}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
+ assign TLAST = TPAYLOAD[P_TLAST_INDX+:1] ;
+ end
+ else begin : no_gen_tlast
+ assign TLAST = 1'b0;
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
+ assign TID = TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] ;
+ end
+ else begin : no_gen_tid
+ assign TID = {C_TID_WIDTH{1'b0}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
+ assign TDEST = TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] ;
+ end
+ else begin : no_gen_tdest
+ assign TDEST = {C_TDEST_WIDTH{1'b0}};
+ end
+ if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
+ assign TUSER = TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] ;
+ end
+ else begin : no_gen_tuser
+ assign TUSER = {C_TUSER_WIDTH{1'b0}};
+ end
+endgenerate
+endmodule
+
+`default_nettype wire
+`endif
+
+
+//*****************************************************************************
+// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+// Description
+// This module instantiates the clock synchronization logic. It passes the
+// incoming signal through two flops to ensure metastability.
+//
+//*****************************************************************************
+`timescale 1ps / 1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_clock_synchronizer # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_NUM_STAGES = 4
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ input wire clk,
+ input wire synch_in ,
+ output wire synch_out
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Local Parameters
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+xpm_cdc_single #(
+ .DEST_SYNC_FF ( C_NUM_STAGES ) ,
+ .SRC_INPUT_REG ( 0 ) ,
+ .SIM_ASSERT_CHK ( 0 )
+)
+inst_xpm_cdc_single (
+ .src_clk ( 1'b0 ) ,
+ .src_in ( synch_in ) ,
+ .dest_out ( synch_out ) ,
+ .dest_clk ( clk )
+);
+
+endmodule
+
+`default_nettype wire
+
+
+// (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axis_infrastructure_v1_1_0_cdc_handshake
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
+`default_nettype none
+
+module axis_infrastructure_v1_1_0_cdc_handshake #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter integer C_WIDTH = 32,
+ parameter integer C_NUM_SYNCHRONIZER_STAGES = 2
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ input wire from_clk,
+ input wire req,
+ output wire ack,
+ input wire [C_WIDTH-1:0] data_in,
+
+ input wire to_clk,
+ output wire data_valid,
+ output wire [C_WIDTH-1:0] data_out
+);
+
+/////////////////////////////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+///////////////////////////////////////////////////////////////////////////////
+xpm_cdc_handshake #(
+ .WIDTH ( C_WIDTH ) ,
+ .DEST_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) ,
+ .SRC_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) ,
+ .DEST_EXT_HSK ( 0 ) ,
+ .SIM_ASSERT_CHK ( 0 )
+)
+inst_xpm_cdc_handshake (
+ .src_in ( data_in ) ,
+ .src_send ( req ) ,
+ .src_rcv ( ack ) ,
+ .src_clk ( from_clk ) ,
+ .dest_out ( data_out ) ,
+ .dest_req ( data_valid ) ,
+ .dest_ack ( 1'b0 ) ,
+ .dest_clk ( to_clk )
+);
+
+endmodule // axis_infrastructure_v1_1_0_cdc_handshake
+
+`default_nettype wire
+
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_register_slice_v1_1_vl_rfs.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_register_slice_v1_1_vl_rfs.v
new file mode 100755
index 0000000000000000000000000000000000000000..93a196e91ffad2e74c6b60ec2572fc1554e32fe6
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/hdl/axis_register_slice_v1_1_vl_rfs.v
@@ -0,0 +1,2425 @@
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+module axis_register_slice_v1_1_17_tdm_sample (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ input wire slow_clk,
+ input wire fast_clk,
+ output wire sample_cycle
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+reg slow_clk_div2 = 1'b0;
+reg posedge_finder_first;
+reg posedge_finder_second;
+wire first_edge;
+wire second_edge;
+reg sample_cycle_d;
+(* shreg_extract = "no" *) reg sample_cycle_r;
+
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+ always @(posedge slow_clk) begin
+ slow_clk_div2 <= ~slow_clk_div2;
+ end
+
+ // Find matching rising edges by clocking slow_clk_div2 onto faster clock
+ always @(posedge fast_clk) begin
+ posedge_finder_first <= slow_clk_div2;
+ end
+ always @(posedge fast_clk) begin
+ posedge_finder_second <= ~slow_clk_div2;
+ end
+
+ assign first_edge = slow_clk_div2 & ~posedge_finder_first;
+ assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;
+
+ always @(*) begin
+ sample_cycle_d = first_edge | second_edge;
+ end
+
+ always @(posedge fast_clk) begin
+ sample_cycle_r <= sample_cycle_d;
+ end
+
+ assign sample_cycle = sample_cycle_r;
+
+endmodule // tdm_sample
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2010 - 2018 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+// Generic single-channel AXI pipeline register on forward and/or reverse signal path
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axic_register_slice_slr
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_multi_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_NUM_SLR_CROSSINGS = 0,
+ parameter integer C_PIPELINES_MASTER = 0,
+ parameter integer C_PIPELINES_SLAVE = 0,
+ parameter integer C_PIPELINES_MIDDLE = 0
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLKEN,
+ input wire ARESET,
+
+ // Slave side
+ input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
+ output wire M_VALID,
+ input wire M_READY
+ );
+
+ localparam integer P_MULTI_SLR = 15;
+ localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;
+ localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;
+ localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);
+
+ generate
+
+ if (C_NUM_SLR_CROSSINGS==0) begin : single_slr
+
+ axis_register_slice_v1_1_17_single_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_PIPELINES (C_PIPELINES_MASTER)
+ )
+ slr_master (
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+ .M_PAYLOAD_DATA (M_PAYLOAD_DATA),
+ .M_VALID (M_VALID),
+ .M_READY (M_READY)
+ );
+
+ end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr
+
+ wire [C_DATA_WIDTH-1:0] src_payload;
+ wire src_handshake;
+ wire src_reset;
+ wire src_ready;
+
+ axis_register_slice_v1_1_17_source_region_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES ( C_PIPELINES_MASTER) ,
+ .C_REG_CONFIG ( P_MULTI_SLR )
+ )
+ slr_master (
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+ .laguna_m_reset_out ( src_reset ) ,
+ .laguna_m_payload ( src_payload ) ,
+ .laguna_m_handshake ( src_handshake ) ,
+ .laguna_m_ready ( src_ready )
+ );
+
+ axis_register_slice_v1_1_17_dest_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( P_MULTI_SLR ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_SLAVE),
+ .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)
+ )
+ slr_slave (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( src_reset ) ,
+ .laguna_s_payload ( src_payload ) ,
+ .laguna_s_handshake ( src_handshake ) ,
+ .laguna_s_ready ( src_ready ) ,
+ .M_PAYLOAD_DATA (M_PAYLOAD_DATA),
+ .M_VALID (M_VALID),
+ .M_READY (M_READY)
+ );
+
+ end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr
+
+ wire [C_DATA_WIDTH-1:0] src_payload;
+ wire src_handshake;
+ wire src_ready;
+ wire src_reset;
+ wire [C_DATA_WIDTH-1:0] dest_payload;
+ wire dest_handshake;
+ wire dest_ready;
+ wire dest_reset;
+
+ axis_register_slice_v1_1_17_source_region_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_MASTER) ,
+ .C_REG_CONFIG ( P_MULTI_SLR )
+ )
+ slr_master (
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+ .laguna_m_reset_out ( src_reset ) ,
+ .laguna_m_payload ( src_payload ) ,
+ .laguna_m_handshake ( src_handshake ) ,
+ .laguna_m_ready ( src_ready )
+ );
+
+ axis_register_slice_v1_1_17_middle_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_PIPELINES (C_PIPELINES_MIDDLE),
+ .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)
+ )
+ slr_middle (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( src_reset ) ,
+ .laguna_s_payload ( src_payload ) ,
+ .laguna_s_handshake ( src_handshake ) ,
+ .laguna_s_ready ( src_ready ) ,
+ .laguna_m_reset_out ( dest_reset ) ,
+ .laguna_m_payload ( dest_payload ) ,
+ .laguna_m_handshake ( dest_handshake ) ,
+ .laguna_m_ready ( dest_ready )
+ );
+
+ axis_register_slice_v1_1_17_dest_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( P_MULTI_SLR ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_SLAVE),
+ .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)
+ )
+ slr_slave (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( dest_reset ) ,
+ .laguna_s_payload ( dest_payload ) ,
+ .laguna_s_handshake ( dest_handshake ) ,
+ .laguna_s_ready ( dest_ready ) ,
+ .M_PAYLOAD_DATA (M_PAYLOAD_DATA),
+ .M_VALID (M_VALID),
+ .M_READY (M_READY)
+ );
+
+ end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr
+
+ wire [C_DATA_WIDTH-1:0] src_payload;
+ wire src_handshake;
+ wire src_ready;
+ wire src_reset;
+ wire [C_DATA_WIDTH-1:0] mid_payload;
+ wire mid_handshake;
+ wire mid_ready;
+ wire mid_reset;
+ wire [C_DATA_WIDTH-1:0] dest_payload;
+ wire dest_handshake;
+ wire dest_ready;
+ wire dest_reset;
+
+ axis_register_slice_v1_1_17_source_region_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_MASTER) ,
+ .C_REG_CONFIG ( P_MULTI_SLR )
+ )
+ slr_master (
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+ .laguna_m_reset_out ( src_reset ) ,
+ .laguna_m_payload ( src_payload ) ,
+ .laguna_m_handshake ( src_handshake ) ,
+ .laguna_m_ready ( src_ready )
+ );
+
+ axis_register_slice_v1_1_17_middle_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_PIPELINES (C_PIPELINES_MIDDLE),
+ .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)
+ )
+ slr_middle_master (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( src_reset ) ,
+ .laguna_s_payload ( src_payload ) ,
+ .laguna_s_handshake ( src_handshake ) ,
+ .laguna_s_ready ( src_ready ) ,
+ .laguna_m_reset_out ( mid_reset ) ,
+ .laguna_m_payload ( mid_payload ) ,
+ .laguna_m_handshake ( mid_handshake ) ,
+ .laguna_m_ready ( mid_ready )
+ );
+
+ axis_register_slice_v1_1_17_middle_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_PIPELINES (C_PIPELINES_MIDDLE),
+ .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)
+ )
+ slr_middle_slave (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( mid_reset ) ,
+ .laguna_s_payload ( mid_payload ) ,
+ .laguna_s_handshake ( mid_handshake ) ,
+ .laguna_s_ready ( mid_ready ) ,
+ .laguna_m_reset_out ( dest_reset ) ,
+ .laguna_m_payload ( dest_payload ) ,
+ .laguna_m_handshake ( dest_handshake ) ,
+ .laguna_m_ready ( dest_ready )
+ );
+
+ axis_register_slice_v1_1_17_dest_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( P_MULTI_SLR ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( C_DATA_WIDTH ),
+ .C_PIPELINES (C_PIPELINES_SLAVE),
+ .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)
+ )
+ slr_slave (
+ .ACLK ( ACLK ) ,
+ .ACLKEN (ACLKEN) ,
+ .ACLK2X (1'b0),
+ .ARESET (ARESET),
+ .laguna_s_reset_in ( dest_reset ) ,
+ .laguna_s_payload ( dest_payload ) ,
+ .laguna_s_handshake ( dest_handshake ) ,
+ .laguna_s_ready ( dest_ready ) ,
+ .M_PAYLOAD_DATA (M_PAYLOAD_DATA),
+ .M_VALID (M_VALID),
+ .M_READY (M_READY)
+ );
+
+ end
+
+endgenerate
+endmodule // multi_slr
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_middle_region_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_PIPELINES = 0,
+ parameter integer C_SOURCE_LATENCY = 1
+ // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLKEN,
+ input wire ARESET,
+
+ // Slave side
+ input wire laguna_s_reset_in,
+ input wire [C_DATA_WIDTH-1:0] laguna_s_payload,
+ input wire laguna_s_handshake,
+ output wire laguna_s_ready,
+
+ // Master side
+ output wire laguna_m_reset_out,
+ output wire [C_DATA_WIDTH-1:0] laguna_m_payload,
+ output wire laguna_m_handshake,
+ input wire laguna_m_ready
+ );
+
+ localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;
+ localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;
+
+ generate
+
+ (* keep="true" *) reg s_reset_dd = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_s_reset_in_d = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_m_reset_out_i = 1'b0;
+
+ assign laguna_m_reset_out = laguna_m_reset_out_i;
+
+ always @(posedge ACLK) begin
+ laguna_s_reset_in_d <= laguna_s_reset_in;
+ s_reset_dd <= laguna_s_reset_in_d;
+ laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;
+ end
+
+ wire ACLEAR;
+ assign ACLEAR = ARESET;
+
+ if (1) begin : common
+ (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;
+ (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;
+ wire laguna_s_handshake_q;
+ wire m_handshake_d;
+ wire laguna_m_handshake_q;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_m_ready_d = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_s_ready_i = 1'b0;
+ (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};
+ wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;
+ wire [(C_PIPELINES+2)-1:0] handshake_i;
+ genvar p;
+
+ assign laguna_m_payload = laguna_m_payload_i;
+ assign m_handshake_d = handshake_i[C_PIPELINES];
+ assign laguna_m_handshake = laguna_m_handshake_q;
+ assign laguna_s_ready = laguna_s_ready_i;
+
+ always @(posedge ACLK) begin
+ laguna_m_ready_d <= laguna_m_ready;
+ laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];
+ ready_d <= {ready_d, laguna_m_ready_d};
+ end
+
+ for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data;
+ wire payload_valid_d;
+ wire payload_valid_q;
+
+ assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;
+ assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;
+ assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];
+
+ always @(posedge ACLK) begin
+ if (p==0) begin
+ laguna_s_payload_d <= laguna_s_payload;
+ end else if (p==C_PIPELINES+1) begin
+ laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end else begin
+ payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ FDCE #(
+ .INIT(1'b0)
+ ) payload_valid_asyncclear_inst (
+ .Q (payload_valid_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (payload_valid_d)
+ );
+ end // loop p
+
+ (* USER_SLL_REG="true" *)
+ FDCE #(
+ .INIT(1'b0)
+ ) laguna_m_handshake_asyncclear_inst (
+ .Q (laguna_m_handshake_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (m_handshake_d)
+ );
+
+ (* USER_SLL_REG="true" *)
+ FDCE #(
+ .INIT(1'b0)
+ ) laguna_s_handshake_asyncclear_inst (
+ .Q (laguna_s_handshake_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (laguna_s_handshake)
+ );
+
+ end // gen_slr
+ endgenerate
+endmodule // middle_region_slr
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_source_region_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_REG_CONFIG = 12,
+ parameter integer C_PIPELINES = 0,
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_SLR_WIDTH = 32
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLK2X,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ output wire laguna_m_reset_out,
+ output wire [C_SLR_WIDTH-1:0] laguna_m_payload,
+ output wire laguna_m_handshake,
+ input wire laguna_m_ready
+ );
+
+ generate
+
+ if (C_REG_CONFIG == 13) begin : gen_slr_tdm
+ localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;
+
+ (* keep="true" *) reg areset_d = 1'b0;
+ always @(posedge ACLK) begin
+ areset_d <= ARESET;
+ end
+
+ assign laguna_m_reset_out = 1'b0;
+
+ (* shreg_extract = "no" *) reg [P_EVEN_WIDTH-1:0] payload_d1;
+ (* shreg_extract = "no" *) reg [C_SLR_WIDTH-1:0] laguna_payload_tdm_d2;
+ (* shreg_extract = "no" *) reg laguna_handshake_d1 = 1'b0;
+ reg s_ready_d2 = 1'b0;
+ wire sample_cycle;
+ integer i;
+
+ assign laguna_m_payload = laguna_payload_tdm_d2;
+ assign laguna_m_handshake = laguna_handshake_d1;
+ assign S_READY = s_ready_d2;
+
+ always @(posedge ACLK) begin
+ if (s_ready_d2) begin
+ payload_d1 <= S_PAYLOAD_DATA; // ACLK cycle 1
+ end
+ end
+
+ always @(posedge ACLK2X) begin
+ for (i=0;i<C_SLR_WIDTH;i=i+1) begin
+ if (s_ready_d2) begin
+ if (~sample_cycle) begin // First (high) phase of ACLK cycle 2
+ laguna_payload_tdm_d2[i] <= payload_d1[2*i+1]; // Mux odd bits
+ end else begin // Second (low) phase of ACLK cycle 2
+ laguna_payload_tdm_d2[i] <= payload_d1[2*i]; // Mux even bits
+ end
+ end
+ end
+ end
+
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ laguna_handshake_d1 <= 1'b0;
+ s_ready_d2 <= 1'b0;
+ end else begin
+ if (s_ready_d2) begin
+ laguna_handshake_d1 <= S_VALID & ACLKEN;
+ end
+ s_ready_d2 <= laguna_m_ready; // Half-cycle setup from dest_region.s_ready_d1
+ end
+ end
+
+ axis_register_slice_v1_1_17_tdm_sample tdm_sample_inst (
+ .slow_clk (ACLK),
+ .fast_clk (ACLK2X),
+ .sample_cycle (sample_cycle)
+ );
+
+ end else begin : gen_slr_common
+
+ localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;
+
+ (* keep="true" *) reg areset_r = 1'b0;
+ (* keep="true" *) reg areset_d = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_m_reset_out_i = 1'b0;
+ reg [15:0] areset_dly = 16'b0;
+
+ assign laguna_m_reset_out = laguna_m_reset_out_i;
+
+ always @(posedge ACLK) begin
+ areset_r <= ARESET;
+ areset_dly <= {16{areset_r}} | (areset_dly<<1);
+ areset_d <= C_REG_CONFIG == 12 ? ARESET : areset_dly[15];
+ laguna_m_reset_out_i <= areset_d; // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.
+ end
+
+ wire ACLEAR;
+ assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ARESET;
+
+ (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;
+ wire m_handshake_d;
+ wire laguna_m_handshake_q;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_m_ready_d = 1'b0;
+ (* keep="true" *) reg s_ready_i = 1'b0;
+ (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};
+ wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;
+ wire [(C_PIPELINES+1)-1:0] handshake_i;
+ genvar p;
+
+ assign laguna_m_payload = laguna_m_payload_i;
+ assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & ACLKEN & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];
+ assign laguna_m_handshake = laguna_m_handshake_q;
+ assign S_READY = s_ready_i;
+
+ always @(posedge ACLK) begin
+ laguna_m_ready_d <= laguna_m_ready;
+ ready_d <= {ready_d, laguna_m_ready_d};
+ if (areset_d) begin
+ s_ready_i <= 1'b0;
+ end else begin
+ s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];
+ end
+ end
+
+ for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data;
+ wire payload_valid_d;
+ wire payload_valid_q;
+
+ assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;
+ assign handshake_i[p] = payload_valid_q;
+ assign payload_valid_d = (p==0) ? (S_VALID & ACLKEN & s_ready_i) : handshake_i[((p>0)?(p-1):0)];
+
+ always @(posedge ACLK) begin
+ if (p==C_PIPELINES) begin
+ laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end else if (p==0) begin
+ payload_data <= S_PAYLOAD_DATA;
+ end else begin
+ payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ FDCE #(
+ .INIT(1'b0)
+ ) payload_valid_asyncclear_inst (
+ .Q (payload_valid_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (payload_valid_d)
+ );
+ end // loop p
+
+ (* USER_SLL_REG="true" *)
+ FDCE #(
+ .INIT(1'b0)
+ ) laguna_m_handshake_asyncclear_inst (
+ .Q (laguna_m_handshake_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (m_handshake_d)
+ );
+
+ end // gen_slr
+endgenerate
+endmodule // source_region_slr
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_dest_region_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_REG_CONFIG = 12,
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_SLR_WIDTH = 32,
+ parameter integer C_PIPELINES = 0,
+ parameter integer C_SOURCE_LATENCY = 1
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLK2X,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire laguna_s_reset_in,
+ input wire [C_SLR_WIDTH-1:0] laguna_s_payload,
+ input wire laguna_s_handshake,
+ output wire laguna_s_ready,
+
+ // Master side
+ output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
+ output wire M_VALID,
+ input wire M_READY
+ );
+
+ generate
+
+ if (C_REG_CONFIG == 13) begin : gen_slr_tdm
+ (* keep="true" *) reg areset_d = 1'b0;
+ always @(posedge ACLK) begin
+ areset_d <= ARESET;
+ end
+
+ localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;
+
+ (* shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] laguna_payload_tdm_d3;
+ (* shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] payload_tdm_d4;
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] fifo_out;
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;
+ (* shreg_extract="no" *) reg laguna_handshake_d2 = 1'b0;
+ (* shreg_extract="no" *) reg s_ready_d1 = 1'b0;
+ (* shreg_extract="no" *) reg s_ready_d2 = 1'b0;
+ reg [P_EVEN_WIDTH-1:0] payload_demux;
+ reg m_valid_r = 1'b0;
+ wire push;
+ wire pop;
+ reg [1:0] fifo_cnt = 2'h0;
+ integer i;
+
+ assign laguna_s_ready = s_ready_d1;
+ assign M_VALID = m_valid_r;
+ assign M_PAYLOAD_DATA = fifo_out; // Registered outputs
+ assign pop = M_READY & ACLKEN & m_valid_r;
+ assign push = laguna_handshake_d2 & s_ready_d2;
+
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ laguna_handshake_d2 <= 1'b0;
+ end else if (s_ready_d2) begin
+ laguna_handshake_d2 <= laguna_s_handshake;
+ end
+ end
+
+ always @(posedge ACLK2X) begin
+ if (s_ready_d2) begin
+ payload_tdm_d4 <= laguna_payload_tdm_d3;
+ laguna_payload_tdm_d3 <= laguna_s_payload;
+ end
+ end
+
+ always @ * begin
+ for (i=0;i<C_SLR_WIDTH;i=i+1) begin
+ payload_demux[2*i+1] = payload_tdm_d4[i]; // Odd bits captured during second (low) phase of ACLK cycle 2
+ payload_demux[2*i] = laguna_payload_tdm_d3[i]; // Even bits captured during first (high) phase of ACLK cycle 3
+ // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)
+ end
+ end
+
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ fifo_cnt <= 2'h0;
+ m_valid_r <= 1'b0;
+ s_ready_d2 <= 1'b0;
+ end else begin
+ s_ready_d2 <= s_ready_d1; // Half-cycle setup from s_ready_d1
+ if (push & ~pop) begin
+ fifo_cnt <= fifo_cnt + 2'h1;
+ m_valid_r <= 1'b1;
+ end else if (~push & pop) begin
+ fifo_cnt <= fifo_cnt - 2'h1;
+ m_valid_r <= fifo_cnt[1]; // fifo_cnt >= 2
+ end
+ end
+ end
+
+ always @(negedge ACLK) begin
+ if (areset_d) begin
+ s_ready_d1 <= 1'b0;
+ end else begin
+ s_ready_d1 <= (M_READY & ACLKEN) | ~m_valid_r; // Half-cycle setup
+ end
+ end
+
+ always @(posedge ACLK) begin
+ case (fifo_cnt)
+ 2'h0: begin // EMPTY
+ fifo_out <= payload_demux;
+ end
+
+ 2'h1: begin
+ fifo_out_n1 <= payload_demux;
+ if (pop) begin
+ fifo_out <= payload_demux;
+ end
+ end
+
+ default: begin // fifo_cnt == 2
+ if (pop) begin
+ fifo_out <= fifo_out_n1;
+ fifo_out_n1 <= payload_demux;
+ end
+ end
+ endcase
+ end
+
+ end else begin : gen_slr_common
+
+ localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;
+ localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;
+
+ (* keep="true" *) reg areset_d = 1'b0;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_s_reset_in_d = 1'b0;
+
+ always @(posedge ACLK) begin
+ laguna_s_reset_in_d <= laguna_s_reset_in;
+ areset_d <= C_REG_CONFIG == 12 ? ARESET : laguna_s_reset_in_d;
+ end
+
+ wire ACLEAR;
+ assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ARESET;
+
+ (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;
+ wire laguna_s_handshake_q;
+ (* USER_SLL_REG="true", keep="true" *) reg laguna_s_ready_i = 1'b0;
+ (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};
+ wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;
+ wire [(C_PIPELINES+1)-1:0] handshake_i;
+ wire m_valid_i;
+ wire push;
+ wire pop;
+ genvar p;
+
+ assign laguna_s_ready = laguna_s_ready_i;
+ assign pop = M_READY & ACLKEN & m_valid_i;
+ assign push = handshake_i[C_PIPELINES];
+ assign M_VALID = m_valid_i;
+
+ always @(posedge ACLK) begin
+ laguna_s_ready_i <= (C_PIPELINES==0) ? ((M_READY & ACLKEN) | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];
+ ready_d <= {ready_d, ((M_READY & ACLKEN) | ~m_valid_i)};
+ end
+
+ for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data;
+ wire payload_valid_d;
+ wire payload_valid_q;
+
+ assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;
+ assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;
+ assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];
+
+ always @(posedge ACLK) begin
+ if (p==0) begin
+ laguna_s_payload_d <= laguna_s_payload;
+ end else begin
+ payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ FDCE #(
+ .INIT(1'b0)
+ ) payload_valid_asyncclear_inst (
+ .Q (payload_valid_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (payload_valid_d)
+ );
+ end // loop p
+
+ (* USER_SLL_REG="true" *)
+ FDCE #(
+ .INIT(1'b0)
+ ) laguna_s_handshake_asyncclear_inst (
+ .Q (laguna_s_handshake_q),
+ .C (ACLK),
+ .CE (1'b1),
+ .CLR (ACLEAR),
+ .D (laguna_s_handshake)
+ );
+
+ axis_register_slice_v1_1_17_axic_reg_srl_fifo #
+ (
+ .C_FIFO_WIDTH (C_DATA_WIDTH),
+ .C_FIFO_SIZE ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)
+ )
+ srl_fifo_0
+ (
+ .aclk (ACLK),
+ .areset (areset_d),
+ .aclear (ACLEAR),
+ .s_mesg (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),
+ .s_valid (push),
+ .m_mesg (M_PAYLOAD_DATA),
+ .m_valid (m_valid_i),
+ .m_ready (pop)
+ );
+
+ end // gen_slr
+endgenerate
+endmodule // dest_region_slr
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_single_slr #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_DATA_WIDTH = 32,
+ parameter integer C_PIPELINES = 0
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLKEN,
+ input wire ARESET,
+
+ // Slave side
+ input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
+ output wire M_VALID,
+ input wire M_READY
+ );
+
+ generate
+
+ localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;
+
+ reg areset_d = 1'b0;
+ reg [3:0] areset_dly = 4'b0;
+ always @(posedge ACLK) begin
+ areset_dly <= {4{ARESET}} | (areset_dly<<1);
+ areset_d <= areset_dly[3];
+ end
+
+ if (1) begin : common
+ reg s_ready_i = 1'b0;
+ (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};
+ wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;
+ wire [(C_PIPELINES+1)-1:0] handshake_i;
+ wire m_valid_i;
+ wire push;
+ wire pop;
+ genvar p;
+
+ assign pop = M_READY & ACLKEN & m_valid_i;
+ assign push = handshake_i[C_PIPELINES];
+ assign M_VALID = m_valid_i;
+ assign S_READY = s_ready_i;
+
+ always @(posedge ACLK) begin
+ ready_d <= {ready_d, ((M_READY & ACLKEN) | ~m_valid_i)};
+ if (areset_d) begin
+ s_ready_i <= 1'b0;
+ end else begin
+ s_ready_i <= (C_PIPELINES==0) ? ((M_READY & ACLKEN) | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];
+ end
+ end
+
+ assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;
+ assign handshake_i[0] = S_VALID & ACLKEN & s_ready_i;
+
+ for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe
+ (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data;
+ (* keep="true" *) reg payload_valid = 1'b0;
+
+ assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;
+ assign handshake_i[p] = payload_valid;
+
+ always @(posedge ACLK) begin
+ if (p==1) begin
+ payload_data <= S_PAYLOAD_DATA;
+ payload_valid <= S_VALID & ACLKEN & s_ready_i & ~areset_d;
+ end else begin
+ payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];
+ payload_valid <= handshake_i[((p>0)?(p-1):0)];
+ end
+ end
+ end
+
+ if (C_PIPELINES==0) begin : ff_fifo
+
+ (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out;
+ (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;
+ (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;
+ reg [1:0] fifo_cnt = 2'h0;
+ reg m_valid_r = 1'b0;
+
+ assign M_PAYLOAD_DATA = fifo_out;
+ assign m_valid_i = m_valid_r;
+
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ fifo_cnt <= 2'h0;
+ m_valid_r <= 1'b0;
+ end else begin
+ if (push & ~pop) begin
+ fifo_cnt <= fifo_cnt + 2'h1;
+ m_valid_r <= 1'b1;
+ end else if (~push & pop) begin
+ fifo_cnt <= fifo_cnt - 2'h1;
+ m_valid_r <= fifo_cnt[1]; // fifo_cnt >= 2
+ end
+ end
+ end
+
+ always @(posedge ACLK) begin
+ case (fifo_cnt)
+ 2'h0: begin // EMPTY
+ fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+
+ 2'h1: begin
+ fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ if (pop) begin
+ fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ 2'h2: begin
+ fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ if (pop) begin
+ fifo_out <= fifo_out_n1;
+ fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+
+ default: begin // fifo_cnt == 3
+ if (pop) begin
+ fifo_out <= fifo_out_n1;
+ fifo_out_n1 <= fifo_out_n2;
+ fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];
+ end
+ end
+ endcase
+ end
+
+ end else begin : srl_fifo
+
+ axis_register_slice_v1_1_17_axic_reg_srl_fifo #
+ (
+ .C_FIFO_WIDTH (C_DATA_WIDTH),
+ .C_FIFO_SIZE ((C_PIPELINES>12) ? 5 : 4)
+ )
+ srl_fifo_0
+ (
+ .aclk (ACLK),
+ .areset (areset_d),
+ .aclear (1'b0),
+ .s_mesg (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),
+ .s_valid (push),
+ .m_mesg (M_PAYLOAD_DATA),
+ .m_valid (m_valid_i),
+ .m_ready (pop)
+ );
+
+ end // gen_fifo
+ end // gen_slr
+ endgenerate
+endmodule // single_slr
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_axic_reg_srl_fifo #
+ // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full
+ (
+ parameter integer C_FIFO_WIDTH = 1, // Width of s_mesg/m_mesg.
+ parameter integer C_FIFO_SIZE = 5 // Depth of FIFO is 2**C_FIFO_SIZE.
+ )
+ (
+ input wire aclk, // Clock
+ input wire areset, // Reset
+ input wire aclear, // Async clear
+ input wire [C_FIFO_WIDTH-1:0] s_mesg, // Input data
+ input wire s_valid, // Input data valid
+ output wire [C_FIFO_WIDTH-1:0] m_mesg, // Output data
+ output wire m_valid, // Output data valid
+ input wire m_ready // Output data ready
+ );
+
+ genvar i;
+
+ generate
+
+ localparam integer P_FIFO_DEPTH = 2**C_FIFO_SIZE;
+ localparam [C_FIFO_SIZE-1:0] P_EMPTY = {C_FIFO_SIZE{1'b1}};
+ localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};
+
+ localparam M_VALID_0 = 1'b0;
+ localparam M_VALID_1 = 1'b1;
+ localparam SRL_VALID_0 = 1'b0;
+ localparam SRL_VALID_1 = 1'b1;
+ localparam S_VALID_0 = 1'b0;
+ localparam S_VALID_1 = 1'b1;
+ localparam M_READY_0 = 1'b0;
+ localparam M_READY_1 = 1'b1;
+
+ localparam [1:0] K_EMPTY = {SRL_VALID_0, M_VALID_0};
+ localparam [1:0] K_HAS1 = {SRL_VALID_0, M_VALID_1};
+ localparam [1:0] K_MIN2 = {SRL_VALID_1, M_VALID_1};
+
+ reg push; // SRL push
+ reg pop; // SRL pop
+ wire [C_FIFO_WIDTH-1:0] srl_reg;
+ reg [C_FIFO_SIZE-1:0] fifoaddr = P_EMPTY;
+
+ wire [1:0] state; // State vector register
+ reg [1:0] next; // Next state value
+ wire [1:0] next_qual; // Next state value
+
+ reg load_mesg; // Load output register
+ reg srl2mesg; // Output reg loads from SRL (else from s_mesg)
+ reg [C_FIFO_WIDTH-1:0] mesg_reg; // No initial state
+ reg m_valid_d;
+ wire m_valid_q;
+
+ assign m_valid = m_valid_q;
+ assign next_qual = areset ? K_EMPTY : next;
+ assign m_mesg = mesg_reg;
+
+ FDCE #(
+ .INIT(1'b0)
+ ) asyncclear_mvalid_inst (
+ .Q (m_valid_q),
+ .C (aclk),
+ .CE (1'b1),
+ .CLR (aclear),
+ .D (m_valid_d)
+ );
+
+ FDCE #(
+ .INIT(1'b0)
+ ) asyncclear_state0_inst (
+ .Q (state[0]),
+ .C (aclk),
+ .CE (1'b1),
+ .CLR (aclear),
+ .D (next_qual[0])
+ );
+
+ FDCE #(
+ .INIT(1'b0)
+ ) asyncclear_state1_inst (
+ .Q (state[1]),
+ .C (aclk),
+ .CE (1'b1),
+ .CLR (aclear),
+ .D (next_qual[1])
+ );
+
+ always @ * begin
+ next = state; // Default: hold state unless re-assigned
+ m_valid_d = m_valid_q & ~areset;
+ load_mesg = 1'b1;
+ srl2mesg = 1'b0;
+ push = 1'b0;
+ pop = 1'b0;
+ case (state)
+ K_EMPTY: begin // FIFO Empty; pre-assert s_ready
+ load_mesg = s_valid;
+ srl2mesg = 1'b0;
+ push = 1'b0;
+ pop = 1'b0;
+ if (s_valid & ~areset) begin
+ next = K_HAS1;
+ m_valid_d = 1'b0;
+ end
+ end // EMPTY
+
+ K_HAS1: begin // FIFO contains 1 item in the output register (SRL empty)
+ srl2mesg = 1'b0;
+ pop = 1'b0;
+ casex ({s_valid,m_ready})
+ {S_VALID_1,M_READY_0}: begin // Receive a 2nd item, push into SRL
+ next = K_MIN2;
+ load_mesg = 1'b0;
+ push = 1'b1;
+ m_valid_d = 1'b1;
+ end
+
+ {S_VALID_0,M_READY_1}: begin // Pop to empty
+ next = K_EMPTY;
+ load_mesg = 1'b1; // Inconsequential
+ push = 1'b0;
+ m_valid_d = 1'b0;
+ end
+
+ {S_VALID_1,M_READY_1}: begin // Push a new item while popping; replace contents of output reg
+ next = K_HAS1;
+ load_mesg = 1'b1;
+ push = 1'b0;
+ m_valid_d = 1'b1;
+ end
+
+ default: begin // s_valid=0, m_ready=0: hold state
+ next = K_HAS1;
+ load_mesg = 1'b0;
+ push = 1'b0;
+ m_valid_d = 1'b1;
+ end
+ endcase
+ end // HAS1
+
+ K_MIN2: begin // FIFO contains >1 item, some in SRL
+ srl2mesg = 1'b1;
+ m_valid_d = 1'b1;
+ casex ({s_valid,m_ready})
+ {S_VALID_1,M_READY_0}: begin // Receive a new item, push into SRL
+ next = K_MIN2;
+ load_mesg = 1'b0;
+ push = 1'b1;
+ pop = 1'b0;
+ end
+
+ {S_VALID_0,M_READY_1}: begin // Pop SRL to replace output reg
+ next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;
+ load_mesg = 1'b1;
+ push = 1'b0;
+ pop = 1'b1;
+ end
+
+ {S_VALID_1,M_READY_1}: begin // Push a new item while popping
+ next = K_MIN2;
+ load_mesg = 1'b1;
+ push = 1'b1;
+ pop = 1'b1;
+ end
+
+ default: begin // s_valid=0, m_ready=0: hold state
+ next = K_MIN2;
+ load_mesg = 1'b0;
+ push = 1'b0;
+ pop = 1'b0;
+ end
+ endcase
+ end // MIN2
+
+ default: begin // Same as RESET
+ next = K_EMPTY;
+ end // default
+ endcase
+ end
+
+ always @(posedge aclk) begin // Payload reg needs no reset
+ if (load_mesg) begin
+ mesg_reg <= srl2mesg ? srl_reg : s_mesg;
+ end
+ end
+
+ // SRL FIFO address pointer
+ always @(posedge aclk) begin
+ if (areset) begin
+ fifoaddr <= P_EMPTY;
+ end else begin
+ if (push & ~pop) begin
+ fifoaddr <= fifoaddr + 1;
+ end else if (~push & pop) begin
+ fifoaddr <= fifoaddr - 1;
+ end
+ end
+ end
+
+ //---------------------------------------------------------------------------
+ // Instantiate SRLs
+ //---------------------------------------------------------------------------
+ for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl
+ (* keep_hierarchy = "yes" *) axis_register_slice_v1_1_17_srl_rtl #
+ (
+ .C_A_WIDTH (C_FIFO_SIZE)
+ )
+ srl_nx1
+ (
+ .clk (aclk),
+ .a (fifoaddr),
+ .ce (s_valid),
+ .d (s_mesg[i]),
+ .q (srl_reg[i])
+ );
+ end
+ endgenerate
+
+endmodule // axic_reg_srl_fifo
+
+`timescale 1ps/1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_srl_rtl #
+ (
+ parameter C_A_WIDTH = 2 // Address Width (>= 1)
+ )
+ (
+ input wire clk, // Clock
+ input wire [C_A_WIDTH-1:0] a, // Address
+ input wire ce, // Clock Enable
+ input wire d, // Input Data
+ output wire q // Output Data
+ );
+
+ localparam integer P_SRLDEPTH = 2**C_A_WIDTH;
+
+ reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
+ always @(posedge clk)
+ if (ce)
+ shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};
+ assign q = shift_reg[a];
+
+endmodule // srl_rtl
+
+
+// (c) Copyright 2010-2011, 2013-2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+// Generic single-channel AXI pipeline register on forward and/or reverse signal path
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axic_register_slice
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_axisc_register_slice #
+ (
+ parameter C_FAMILY = "virtex6",
+ parameter C_DATA_WIDTH = 32,
+ parameter C_REG_CONFIG = 32'h00000001,
+ // C_REG_CONFIG:
+ // 0 => BYPASS = The channel is just wired through the module.
+ // 1 => DEFAULT = Minimized fanout on input signals M_READY and S_TVALID
+ // 2 => FWD = The master VALID and payload signals are registrated.
+ // 3 => REV = The slave ready signal is registrated
+ // 4 => RESERVED (all outputs driven to 0).
+ // 5 => RESERVED (all outputs driven to 0).
+ // 6 => INPUTS = Slave and Master side inputs are registrated.
+ // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+ // 8 => FWD_REV = Both FWD and REV (fully-registered)
+ // 10 => NO_READY = Assume no ready signal
+ // 12 => SLR Crossing (source->dest flops, full-width payload, single clock)
+ // 13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)
+ parameter integer C_NUM_SLR_CROSSINGS = 0,
+ parameter integer C_PIPELINES_MASTER = 0,
+ parameter integer C_PIPELINES_SLAVE = 0,
+ parameter integer C_PIPELINES_MIDDLE = 0
+ )
+ (
+ // System Signals
+ input wire ACLK,
+ input wire ACLK2X,
+ input wire ARESET,
+ input wire ACLKEN,
+
+ // Slave side
+ input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+ input wire S_VALID,
+ output wire S_READY,
+
+ // Master side
+ output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
+ output wire M_VALID,
+ input wire M_READY
+ );
+
+ generate
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 0
+ // Bypass mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ if (C_REG_CONFIG == 32'h00000000)
+ begin
+ assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
+ assign M_VALID = S_VALID;
+ assign S_READY = M_READY;
+ end
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 15
+ // Multi SLR Crossing
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 15) begin : gen_multi_slr
+
+ axis_register_slice_v1_1_17_multi_slr # (
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,
+ .C_PIPELINES_MASTER (C_PIPELINES_MASTER) ,
+ .C_PIPELINES_SLAVE (C_PIPELINES_SLAVE) ,
+ .C_PIPELINES_MIDDLE (C_PIPELINES_MIDDLE)
+ )
+ multi (
+ // System Signals
+ .ACLK (ACLK),
+ .ACLKEN (ACLKEN) ,
+ .ARESET (ARESET),
+
+ // Slave side
+ .S_PAYLOAD_DATA (S_PAYLOAD_DATA),
+ .S_VALID (S_VALID),
+ .S_READY (S_READY),
+
+ // Master side
+ .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) ,
+ .M_VALID ( M_VALID ) ,
+ .M_READY ( M_READY )
+ );
+ end
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 12 or 13
+ // TDM SLR Crossing
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if ((C_REG_CONFIG == 32'h0000000C) || (C_REG_CONFIG == 32'h0000000D))
+ begin : gen_slr_crossing
+ localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;
+ localparam integer P_TDM_WIDTH = P_EVEN_WIDTH/2;
+ localparam integer P_SLR_WIDTH = (C_REG_CONFIG == 13) ? P_TDM_WIDTH : C_DATA_WIDTH;
+
+ wire [P_SLR_WIDTH-1:0] slr_payload;
+ wire slr_handshake;
+ wire slr_ready;
+
+ axis_register_slice_v1_1_17_source_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( C_REG_CONFIG ) ,
+ .C_PIPELINES (0),
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( P_SLR_WIDTH )
+ )
+ slr_source_0 (
+ .ACLK ( ACLK ) ,
+ .ACLK2X ( ACLK2X ) ,
+ .ARESET (ARESET),
+ .ACLKEN ( ACLKEN ) ,
+ .laguna_m_reset_out ( ) ,
+ .S_PAYLOAD_DATA ( S_PAYLOAD_DATA ) ,
+ .S_VALID ( S_VALID ) ,
+ .S_READY ( S_READY ) ,
+ .laguna_m_payload ( slr_payload ) ,
+ .laguna_m_handshake ( slr_handshake ) ,
+ .laguna_m_ready ( slr_ready )
+ );
+
+ axis_register_slice_v1_1_17_dest_region_slr #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_REG_CONFIG ( C_REG_CONFIG ) ,
+ .C_PIPELINES (0),
+ .C_DATA_WIDTH ( C_DATA_WIDTH ) ,
+ .C_SLR_WIDTH ( P_SLR_WIDTH )
+ )
+ slr_dest_0 (
+ .ACLK ( ACLK ) ,
+ .ACLK2X ( ACLK2X ) ,
+ .ARESET (ARESET),
+ .ACLKEN ( ACLKEN ) ,
+ .laguna_s_reset_in ( 1'b0 ) ,
+ .laguna_s_payload ( slr_payload ) ,
+ .laguna_s_handshake ( slr_handshake ) ,
+ .laguna_s_ready ( slr_ready ) ,
+ .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) ,
+ .M_VALID ( M_VALID ) ,
+ .M_READY ( M_READY )
+ );
+
+ end // if (C_REG_CONFIG == 12 or 13 )
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 10
+ // No ready, single stage register
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h0000000A)
+ begin : NO_READY
+
+ reg [C_DATA_WIDTH-1:0] storage_data1;
+ reg m_valid_r = 1'b0; //local signal of output
+
+ // assign local signal to its output signal
+ assign S_READY = 1'b1;
+ assign M_VALID = m_valid_r;
+
+ // Load storage1 with slave side data
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN) begin
+ storage_data1 <= S_PAYLOAD_DATA;
+ m_valid_r <= S_VALID;
+ end
+ end
+
+ assign M_PAYLOAD_DATA = storage_data1;
+
+
+ end // if (C_REG_CONFIG == 10 )
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 1
+ // Minimized fanout on input signals M_READY and S_TVALID
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000001) begin : gen_AB_reg_slice
+ // /----------S_READY
+ // |/---------M_VALID
+ localparam SM_RESET = 2'b00;
+ localparam SM_IDLE = 2'b10;
+ localparam SM_ONE = 2'b11;
+ localparam SM_FULL = 2'b01;
+
+ (* fsm_encoding = "none" *) reg [1:0] state = SM_RESET;
+ reg [C_DATA_WIDTH-1:0] payload_a;
+ reg [C_DATA_WIDTH-1:0] payload_b;
+ reg sel_rd = 1'b0;
+ reg sel_wr = 1'b0;
+ wire sel;
+ wire load_a;
+ wire load_b;
+
+ assign M_VALID = state[0];
+ assign S_READY = state[1];
+
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ state <= SM_RESET;
+ end
+ else if (ACLKEN) begin
+ case (state)
+ SM_IDLE:
+ if (S_VALID)
+ state <= SM_ONE;
+ SM_ONE:
+ if (S_VALID & ~M_READY)
+ state <= SM_FULL;
+ else if (~S_VALID & M_READY)
+ state <= SM_IDLE;
+ SM_FULL:
+ if (M_READY)
+ state <= SM_ONE;
+ // SM_RESET:
+ default:
+ state <= SM_IDLE;
+ endcase
+ end
+ end
+
+ assign sel = sel_rd;
+
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ sel_rd <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ sel_rd <= (M_READY & M_VALID) ? ~sel_rd : sel_rd;
+ end
+ end
+
+ assign load_a = ~sel_wr & (state != SM_FULL);
+ assign load_b = sel_wr & (state != SM_FULL);
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ sel_wr <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ sel_wr <= (S_READY & S_VALID) ? ~sel_wr : sel_wr;
+ end
+ end
+
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ payload_a <= load_a ? S_PAYLOAD_DATA : payload_a;
+ end
+ end
+
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ payload_b <= load_b ? S_PAYLOAD_DATA : payload_b;
+ end
+ end
+
+ assign M_PAYLOAD_DATA = sel ? payload_b : payload_a;
+
+ end // if (C_REG_CONFIG == 1 )
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 8
+ // Both FWD and REV mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if ((C_REG_CONFIG == 32'h00000008))
+ begin
+ localparam [1:0]
+ ZERO = 2'b10,
+ ONE = 2'b11,
+ TWO = 2'b01;
+ (* fsm_encoding = "none" *) reg [1:0] state = ZERO;
+
+ reg [C_DATA_WIDTH-1:0] storage_data1;
+ reg [C_DATA_WIDTH-1:0] storage_data2;
+ reg load_s1;
+ wire load_s2;
+ wire load_s1_from_s2;
+ reg s_ready_i = 1'b0; //local signal of output
+ wire m_valid_i; //local signal of output
+
+ // assign local signal to its output signal
+ assign S_READY = s_ready_i;
+ assign M_VALID = m_valid_i;
+
+ (* equivalent_register_removal = "no" *) reg [1:0] areset_d = 2'b11; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= {areset_d[0], ARESET};
+ end
+ end
+
+ // Load storage1 with either slave side data or from storage2
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN) begin
+ storage_data1 <= ~load_s1 ? storage_data1 :
+ load_s1_from_s2 ? storage_data2 :
+ S_PAYLOAD_DATA;
+ end
+ end
+
+ // Load storage2 with slave side data
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN) begin
+ storage_data2 <= load_s2 ? S_PAYLOAD_DATA : storage_data2;
+ end
+ end
+
+ assign M_PAYLOAD_DATA = storage_data1;
+
+ // Always load s2 on a valid transaction even if it's unnecessary
+ assign load_s2 = S_VALID & s_ready_i;
+
+ // Loading s1
+ always @ *
+ begin
+ if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
+ // Load when ONE if we both have read and write at the same time
+ ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
+ // Load when TWO and we have a transaction on Master side
+ ((state == TWO) && (M_READY == 1)))
+ load_s1 = 1'b1;
+ else
+ load_s1 = 1'b0;
+ end // always @ *
+
+ assign load_s1_from_s2 = (state == TWO);
+
+ // State Machine for handling output signals
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ s_ready_i <= 1'b0;
+ state <= ZERO;
+ end else if (ACLKEN && areset_d == 2'b10) begin
+ s_ready_i <= 1'b1;
+ state <= ZERO;
+ end else if (ACLKEN && areset_d == 2'b00) begin
+ case (state)
+ // No transaction stored locally
+ ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
+
+ // One transaction stored locally
+ ONE: begin
+ if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
+ if (~M_READY & S_VALID) begin
+ state <= TWO; // Got another one so move to TWO
+ s_ready_i <= 1'b0;
+ end
+ end
+
+ // TWO transaction stored locally
+ TWO: if (M_READY) begin
+ state <= ONE; // Read out one so move to ONE
+ s_ready_i <= 1'b1;
+ end
+
+ default:
+ state <= ZERO;
+
+ endcase // case (state)
+ end
+ end // always @ (posedge ACLK)
+
+ assign m_valid_i = state[0];
+
+ end // if (C_REG_CONFIG == 8)
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 2
+ // Only FWD mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000002)
+ begin
+ reg [C_DATA_WIDTH-1:0] storage_data;
+ wire s_ready_i; //local signal of output
+ reg m_valid_i = 1'b0; //local signal of output
+
+ // assign local signal to its output signal
+ assign S_READY = s_ready_i;
+ assign M_VALID = m_valid_i;
+
+ (* equivalent_register_removal = "no" *) reg [1:0] areset_d; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= {areset_d[0], ARESET};
+ end
+ end
+
+ // Save payload data whenever we have a transaction on the slave side
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN)
+ storage_data <= (S_VALID & s_ready_i) ? S_PAYLOAD_DATA : storage_data;
+ end
+
+ assign M_PAYLOAD_DATA = storage_data;
+
+ // M_Valid set to high when we have a completed transfer on slave side
+ // Is removed on a M_READY except if we have a new transfer on the slave side
+ always @(posedge ACLK) begin
+ if (areset_d) begin
+ m_valid_i <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ m_valid_i <= S_VALID ? 1'b1 : // Always set m_valid_i when slave side is valid
+ M_READY ? 1'b0 : // Clear (or keep) when no slave side is valid but master side is ready
+ m_valid_i;
+ end
+ end // always @ (posedge ACLK)
+
+ // Slave Ready is either when Master side drives M_Ready or we have space in our storage data
+ assign s_ready_i = (M_READY | ~m_valid_i) & ~|areset_d;
+
+ end // if (C_REG_CONFIG == 2)
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 3
+ // Only REV mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000003)
+ begin
+ reg [C_DATA_WIDTH-1:0] storage_data;
+ reg s_ready_i = 1'b0; //local signal of output
+ reg has_valid_storage_i;
+ reg has_valid_storage;
+
+ (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= ARESET;
+ end
+ end
+
+ // Save payload data whenever we have a transaction on the slave side
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN)
+ storage_data <= (S_VALID & s_ready_i) ? S_PAYLOAD_DATA : storage_data;
+ end
+
+ assign M_PAYLOAD_DATA = has_valid_storage ? storage_data : S_PAYLOAD_DATA;
+
+ // Need to determine when we need to save a payload
+ // Need a combinatorial signals since it will also effect S_READY
+ always @ *
+ begin
+ // Set the value if we have a slave transaction but master side is not ready
+ if (S_VALID & s_ready_i & ~M_READY)
+ has_valid_storage_i = 1'b1;
+
+ // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
+ // transaction
+ else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
+ has_valid_storage_i = 1'b0;
+ else
+ has_valid_storage_i = has_valid_storage;
+ end // always @ *
+
+ always @(posedge ACLK)
+ begin
+ if (ARESET) begin
+ has_valid_storage <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ has_valid_storage <= has_valid_storage_i;
+ end
+ end
+
+ // S_READY is either clocked M_READY or that we have room in local storage
+ always @(posedge ACLK) begin
+ if (ARESET) begin
+ s_ready_i <= 1'b0;
+ end
+ else if (ACLKEN) begin
+ s_ready_i <= M_READY | ~has_valid_storage_i;
+ end
+ end
+
+ // assign local signal to its output signal
+ assign S_READY = s_ready_i;
+
+ // M_READY is either combinatorial S_READY or that we have valid data in local storage
+ assign M_VALID = (S_VALID | has_valid_storage) & ~areset_d;
+
+ end // if (C_REG_CONFIG == 3)
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
+ begin
+// synthesis translate_off
+ initial begin
+ $display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
+ end
+// synthesis translate_on
+ assign M_PAYLOAD_DATA = 0;
+ assign M_VALID = 1'b0;
+ assign S_READY = 1'b0;
+ end
+
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 6
+ // INPUTS mode
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000006)
+ begin
+ localparam [1:0]
+ ZERO = 2'b00,
+ ONE = 2'b01,
+ TWO = 2'b11;
+ reg [1:0] state = ZERO;
+ reg [1:0] next_state;
+
+ reg [C_DATA_WIDTH-1:0] storage_data1;
+ reg [C_DATA_WIDTH-1:0] storage_data2;
+ reg s_valid_d = 1'b0;
+ reg s_ready_d = 1'b0;
+ reg m_ready_d = 1'b0;
+ reg m_valid_d = 1'b0;
+ reg load_s2;
+ reg sel_s2;
+ wire new_access;
+ wire access_done;
+ wire s_ready_i; //local signal of output
+ reg s_ready_ii;
+ reg m_valid_i; //local signal of output
+
+ (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= ARESET;
+ end
+ end
+
+ // assign local signal to its output signal
+ assign S_READY = (state == ZERO) ? 1'b0 : s_ready_i;
+ assign M_VALID = (state == ZERO) ? 1'b0 : m_valid_i;
+ assign s_ready_i = s_ready_ii & ~areset_d;
+
+ // Registrate input control signals
+ always @(posedge ACLK)
+ begin
+ if (ARESET) begin
+ s_valid_d <= 1'b0;
+ s_ready_d <= 1'b0;
+ m_ready_d <= 1'b0;
+ end else if (ACLKEN) begin
+ s_valid_d <= S_VALID;
+ s_ready_d <= s_ready_i;
+ m_ready_d <= M_READY;
+ end
+ end // always @ (posedge ACLK)
+
+ // Load storage1 with slave side payload data when slave side ready is high
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN)
+ storage_data1 <= (s_ready_i) ? S_PAYLOAD_DATA : storage_data1;
+ end
+
+ // Load storage2 with storage data
+ always @(posedge ACLK)
+ begin
+ if (ACLKEN)
+ storage_data2 <= load_s2 ? storage_data1 : storage_data2;
+ end
+
+ always @(posedge ACLK)
+ begin
+ if (ARESET)
+ m_valid_d <= 1'b0;
+ else if (ACLKEN)
+ m_valid_d <= m_valid_i;
+ end
+
+ // Local help signals
+ assign new_access = s_ready_d & s_valid_d;
+ assign access_done = m_ready_d & m_valid_d;
+
+
+ // State Machine for handling output signals
+ always @*
+ begin
+ next_state = state; // Stay in the same state unless we need to move to another state
+ load_s2 = 0;
+ sel_s2 = 0;
+ m_valid_i = 0;
+ s_ready_ii = 0;
+ case (state)
+ // No transaction stored locally
+ ZERO: begin
+ load_s2 = 0;
+ sel_s2 = 0;
+ m_valid_i = 0;
+ s_ready_ii = 1;
+ if (new_access) begin
+ next_state = ONE; // Got one so move to ONE
+ load_s2 = 1;
+ m_valid_i = 0;
+ end
+ else begin
+ next_state = next_state;
+ load_s2 = load_s2;
+ m_valid_i = m_valid_i;
+ end
+
+ end // case: ZERO
+
+ // One transaction stored locally
+ ONE: begin
+ load_s2 = 0;
+ sel_s2 = 1;
+ m_valid_i = 1;
+ s_ready_ii = 1;
+ if (~new_access & access_done) begin
+ next_state = ZERO; // Read out one so move to ZERO
+ m_valid_i = 0;
+ end
+ else if (new_access & ~access_done) begin
+ next_state = TWO; // Got another one so move to TWO
+ s_ready_ii = 0;
+ end
+ else if (new_access & access_done) begin
+ load_s2 = 1;
+ sel_s2 = 0;
+ end
+ else begin
+ load_s2 = load_s2;
+ sel_s2 = sel_s2;
+ end
+
+
+ end // case: ONE
+
+ // TWO transaction stored locally
+ TWO: begin
+ load_s2 = 0;
+ sel_s2 = 1;
+ m_valid_i = 1;
+ s_ready_ii = 0;
+ if (access_done) begin
+ next_state = ONE; // Read out one so move to ONE
+ s_ready_ii = 1;
+ load_s2 = 1;
+ sel_s2 = 0;
+ end
+ else begin
+ next_state = next_state;
+ s_ready_ii = s_ready_ii;
+ load_s2 = load_s2;
+ sel_s2 = sel_s2;
+ end
+ end // case: TWO
+ endcase // case (state)
+ end // always @ *
+
+
+ // State Machine for handling output signals
+ always @(posedge ACLK)
+ begin
+ if (ARESET)
+ state <= ZERO;
+ else if (ACLKEN)
+ state <= next_state; // Stay in the same state unless we need to move to another state
+ end
+
+ // Master Payload mux
+ assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
+
+ end // if (C_REG_CONFIG == 6)
+ ////////////////////////////////////////////////////////////////////
+ //
+ // C_REG_CONFIG = 7
+ // Light-weight mode.
+ // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+ // Operates same as 1-deep FIFO
+ //
+ ////////////////////////////////////////////////////////////////////
+ else if (C_REG_CONFIG == 32'h00000007)
+ begin
+ reg [C_DATA_WIDTH-1:0] storage_data1;
+ reg s_ready_i = 1'b0; //local signal of output
+ reg m_valid_i = 1'b0; //local signal of output
+
+ // assign local signal to its output signal
+ assign S_READY = s_ready_i;
+ assign M_VALID = m_valid_i;
+
+ (* equivalent_register_removal = "no" *) reg [1:0] areset_d; // Reset delay register
+ always @(posedge ACLK) begin
+ if (ACLKEN) begin
+ areset_d <= {areset_d[0], ARESET};
+ end
+ end
+
+ // Load storage1 with slave side data
+ always @(posedge ACLK)
+ begin
+ if (ARESET) begin
+ s_ready_i <= 1'b0;
+ m_valid_i <= 1'b0;
+ end else if (ACLKEN && areset_d == 2'b10) begin
+ s_ready_i <= 1'b1;
+ end else if (ACLKEN && areset_d == 2'b00) begin
+ if (m_valid_i & M_READY) begin
+ s_ready_i <= 1'b1;
+ m_valid_i <= 1'b0;
+ end else if (S_VALID & s_ready_i) begin
+ s_ready_i <= 1'b0;
+ m_valid_i <= 1'b1;
+ end
+ end
+ if (~m_valid_i) begin
+ storage_data1 <= S_PAYLOAD_DATA;
+ end
+ end
+ assign M_PAYLOAD_DATA = storage_data1;
+ end // if (C_REG_CONFIG == 7)
+
+ else begin : default_case
+ // Passthrough
+ assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
+ assign M_VALID = S_VALID;
+ assign S_READY = M_READY;
+ end
+
+ endgenerate
+endmodule // axisc_register_slice
+
+
+
+// (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+// Generic single-channel AXIS pipeline register on forward and/or reverse signal path.
+//
+// Verilog-standard: Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+// axis_register_slice
+// util_axis2vector
+// axisc_register_slice
+// util_vector2axis
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_register_slice_v1_1_17_axis_register_slice #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+ parameter C_FAMILY = "virtex6",
+ parameter integer C_AXIS_TDATA_WIDTH = 8,
+ parameter integer C_AXIS_TID_WIDTH = 1,
+ parameter integer C_AXIS_TDEST_WIDTH = 1,
+ parameter integer C_AXIS_TUSER_WIDTH = 1,
+ parameter [31:0] C_AXIS_SIGNAL_SET = 32'h3,
+ // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+ // [0] => TREADY present
+ // [1] => TDATA present
+ // [2] => TSTRB present, TDATA must be present
+ // [3] => TKEEP present, TDATA must be present
+ // [4] => TLAST present
+ // [5] => TID present
+ // [6] => TDEST present
+ // [7] => TUSER present
+ parameter integer C_REG_CONFIG = 1,
+ // C_REG_CONFIG:
+ // 0 => BYPASS = The channel is just wired through the module.
+ // 1 => DEFAULT = Minimized fanout on input signals M_READY and S_TVALID
+ // 2 => FWD = The master VALID and payload signals are registrated.
+ // 3 => REV = The slave ready signal is registrated
+ // 4 => RESERVED (all outputs driven to 0).
+ // 5 => RESERVED (all outputs driven to 0).
+ // 6 => INPUTS = Slave and Master side inputs are registrated.
+ // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+ // 8 => FWD_REV = Both FWD and REV (fully-registered)
+ // 10 => NO_READY = Assume no ready signal
+ // 12 => SLR Crossing (source->dest flops, full-width payload, single clock)
+ // 13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)
+ parameter integer C_NUM_SLR_CROSSINGS = 0,
+ parameter integer C_PIPELINES_MASTER = 0,
+ parameter integer C_PIPELINES_SLAVE = 0,
+ parameter integer C_PIPELINES_MIDDLE = 0
+ )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+ // System Signals
+ input wire aclk,
+ input wire aclk2x,
+ input wire aresetn,
+ input wire aclken,
+
+ // Slave side
+ input wire s_axis_tvalid,
+ output wire s_axis_tready,
+ input wire [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
+ input wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb,
+ input wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep,
+ input wire s_axis_tlast,
+ input wire [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
+ input wire [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
+ input wire [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
+
+ // Master side
+ output wire m_axis_tvalid,
+ input wire m_axis_tready,
+ output wire [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
+ output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb,
+ output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep,
+ output wire m_axis_tlast,
+ output wire [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
+ output wire [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
+ output wire [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser
+ );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+ localparam P_TPAYLOAD_WIDTH = f_payload_width(C_AXIS_TDATA_WIDTH, C_AXIS_TID_WIDTH,
+ C_AXIS_TDEST_WIDTH, C_AXIS_TUSER_WIDTH,
+ C_AXIS_SIGNAL_SET);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire [P_TPAYLOAD_WIDTH-1:0] s_axis_tpayload;
+wire [P_TPAYLOAD_WIDTH-1:0] m_axis_tpayload;
+
+reg areset_r;
+always @(posedge aclk) begin
+ areset_r <= ~aresetn;
+end
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+ axis_infrastructure_v1_1_0_util_axis2vector #(
+ .C_TDATA_WIDTH ( C_AXIS_TDATA_WIDTH ) ,
+ .C_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_TUSER_WIDTH ( C_AXIS_TUSER_WIDTH ) ,
+ .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_SIGNAL_SET ( C_AXIS_SIGNAL_SET )
+ )
+ util_axis2vector_0 (
+ .TDATA ( s_axis_tdata ) ,
+ .TSTRB ( s_axis_tstrb ) ,
+ .TKEEP ( s_axis_tkeep ) ,
+ .TLAST ( s_axis_tlast ) ,
+ .TID ( s_axis_tid ) ,
+ .TDEST ( s_axis_tdest ) ,
+ .TUSER ( s_axis_tuser ) ,
+ .TPAYLOAD ( s_axis_tpayload )
+ );
+
+ axis_register_slice_v1_1_17_axisc_register_slice #(
+ .C_FAMILY ( C_FAMILY ) ,
+ .C_DATA_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_REG_CONFIG ( (C_AXIS_SIGNAL_SET[0] == 0) ? 32'hA : C_REG_CONFIG),
+ .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,
+ .C_PIPELINES_MASTER (C_PIPELINES_MASTER) ,
+ .C_PIPELINES_SLAVE (C_PIPELINES_SLAVE) ,
+ .C_PIPELINES_MIDDLE (C_PIPELINES_MIDDLE)
+ )
+ axisc_register_slice_0 (
+ .ACLK ( aclk ) ,
+ .ACLK2X ( aclk2x ) ,
+ .ARESET ( areset_r ) ,
+ .ACLKEN ( aclken ) ,
+ .S_VALID ( s_axis_tvalid ) ,
+ .S_READY ( s_axis_tready ) ,
+ .S_PAYLOAD_DATA ( s_axis_tpayload ) ,
+
+ .M_VALID ( m_axis_tvalid ) ,
+ .M_READY ( (C_AXIS_SIGNAL_SET[0] == 0) ? 1'b1 : m_axis_tready ) ,
+ .M_PAYLOAD_DATA ( m_axis_tpayload )
+ );
+
+ axis_infrastructure_v1_1_0_util_vector2axis #(
+ .C_TDATA_WIDTH ( C_AXIS_TDATA_WIDTH ) ,
+ .C_TID_WIDTH ( C_AXIS_TID_WIDTH ) ,
+ .C_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) ,
+ .C_TUSER_WIDTH ( C_AXIS_TUSER_WIDTH ) ,
+ .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) ,
+ .C_SIGNAL_SET ( C_AXIS_SIGNAL_SET )
+ )
+ util_vector2axis_0 (
+ .TPAYLOAD ( m_axis_tpayload ) ,
+ .TDATA ( m_axis_tdata ) ,
+ .TSTRB ( m_axis_tstrb ) ,
+ .TKEEP ( m_axis_tkeep ) ,
+ .TLAST ( m_axis_tlast ) ,
+ .TID ( m_axis_tid ) ,
+ .TDEST ( m_axis_tdest ) ,
+ .TUSER ( m_axis_tuser )
+ );
+
+
+endmodule // axis_register_slice
+
+`default_nettype wire
+
+
+
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/sim/axis_dwidth_converter_64_256.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/sim/axis_dwidth_converter_64_256.v
new file mode 100644
index 0000000000000000000000000000000000000000..1fba344c04fb57a3a35c72634bfbfd04f8fdc35e
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/sim/axis_dwidth_converter_64_256.v
@@ -0,0 +1,132 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
+// IP Revision: 16
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module axis_dwidth_converter_64_256 (
+ aclk,
+ aresetn,
+ s_axis_tvalid,
+ s_axis_tready,
+ s_axis_tdata,
+ s_axis_tkeep,
+ s_axis_tlast,
+ m_axis_tvalid,
+ m_axis_tready,
+ m_axis_tdata,
+ m_axis_tkeep,
+ m_axis_tlast
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, PHASE 0.000" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
+input wire s_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
+output wire s_axis_tready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
+input wire [63 : 0] s_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
+input wire [7 : 0] s_axis_tkeep;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
+input wire s_axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
+output wire m_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
+input wire m_axis_tready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
+output wire [255 : 0] m_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
+output wire [31 : 0] m_axis_tkeep;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
+output wire m_axis_tlast;
+
+ axis_dwidth_converter_v1_1_16_axis_dwidth_converter #(
+ .C_FAMILY("virtexuplus"),
+ .C_S_AXIS_TDATA_WIDTH(64),
+ .C_M_AXIS_TDATA_WIDTH(256),
+ .C_AXIS_TID_WIDTH(1),
+ .C_AXIS_TDEST_WIDTH(1),
+ .C_S_AXIS_TUSER_WIDTH(1),
+ .C_M_AXIS_TUSER_WIDTH(1),
+ .C_AXIS_SIGNAL_SET('B00000000000000000000000000011011)
+ ) inst (
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .aclken(1'H1),
+ .s_axis_tvalid(s_axis_tvalid),
+ .s_axis_tready(s_axis_tready),
+ .s_axis_tdata(s_axis_tdata),
+ .s_axis_tstrb(8'HFF),
+ .s_axis_tkeep(s_axis_tkeep),
+ .s_axis_tlast(s_axis_tlast),
+ .s_axis_tid(1'H0),
+ .s_axis_tdest(1'H0),
+ .s_axis_tuser(1'H0),
+ .m_axis_tvalid(m_axis_tvalid),
+ .m_axis_tready(m_axis_tready),
+ .m_axis_tdata(m_axis_tdata),
+ .m_axis_tstrb(),
+ .m_axis_tkeep(m_axis_tkeep),
+ .m_axis_tlast(m_axis_tlast),
+ .m_axis_tid(),
+ .m_axis_tdest(),
+ .m_axis_tuser()
+ );
+endmodule
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/synth/axis_dwidth_converter_64_256.v b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/synth/axis_dwidth_converter_64_256.v
new file mode 100644
index 0000000000000000000000000000000000000000..af567305169814210a89ed8a294214f27b2c8a10
--- /dev/null
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_dwidth_converter_64_256/synth/axis_dwidth_converter_64_256.v
@@ -0,0 +1,133 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
+// IP Revision: 16
+
+(* X_CORE_INFO = "axis_dwidth_converter_v1_1_16_axis_dwidth_converter,Vivado 2018.2" *)
+(* CHECK_LICENSE_TYPE = "axis_dwidth_converter_64_256,axis_dwidth_converter_v1_1_16_axis_dwidth_converter,{}" *)
+(* CORE_GENERATION_INFO = "axis_dwidth_converter_64_256,axis_dwidth_converter_v1_1_16_axis_dwidth_converter,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_dwidth_converter,x_ipVersion=1.1,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_S_AXIS_TDATA_WIDTH=64,C_M_AXIS_TDATA_WIDTH=256,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_S_AXIS_TUSER_WIDTH=1,C_M_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000011011}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module axis_dwidth_converter_64_256 (
+ aclk,
+ aresetn,
+ s_axis_tvalid,
+ s_axis_tready,
+ s_axis_tdata,
+ s_axis_tkeep,
+ s_axis_tlast,
+ m_axis_tvalid,
+ m_axis_tready,
+ m_axis_tdata,
+ m_axis_tkeep,
+ m_axis_tlast
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, PHASE 0.000" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
+input wire s_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
+output wire s_axis_tready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
+input wire [63 : 0] s_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
+input wire [7 : 0] s_axis_tkeep;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
+input wire s_axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
+output wire m_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
+input wire m_axis_tready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
+output wire [255 : 0] m_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
+output wire [31 : 0] m_axis_tkeep;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
+output wire m_axis_tlast;
+
+ axis_dwidth_converter_v1_1_16_axis_dwidth_converter #(
+ .C_FAMILY("virtexuplus"),
+ .C_S_AXIS_TDATA_WIDTH(64),
+ .C_M_AXIS_TDATA_WIDTH(256),
+ .C_AXIS_TID_WIDTH(1),
+ .C_AXIS_TDEST_WIDTH(1),
+ .C_S_AXIS_TUSER_WIDTH(1),
+ .C_M_AXIS_TUSER_WIDTH(1),
+ .C_AXIS_SIGNAL_SET('B00000000000000000000000000011011)
+ ) inst (
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .aclken(1'H1),
+ .s_axis_tvalid(s_axis_tvalid),
+ .s_axis_tready(s_axis_tready),
+ .s_axis_tdata(s_axis_tdata),
+ .s_axis_tstrb(8'HFF),
+ .s_axis_tkeep(s_axis_tkeep),
+ .s_axis_tlast(s_axis_tlast),
+ .s_axis_tid(1'H0),
+ .s_axis_tdest(1'H0),
+ .s_axis_tuser(1'H0),
+ .m_axis_tvalid(m_axis_tvalid),
+ .m_axis_tready(m_axis_tready),
+ .m_axis_tdata(m_axis_tdata),
+ .m_axis_tstrb(),
+ .m_axis_tkeep(m_axis_tkeep),
+ .m_axis_tlast(m_axis_tlast),
+ .m_axis_tid(),
+ .m_axis_tdest(),
+ .m_axis_tuser()
+ );
+endmodule
diff --git a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_width_converter.tcl b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_width_converter.tcl
index c26877dc51ec3d1f33b5456bf67a81e988ba8ed4..f8695f5d3e896542a12ca6127b81dc3a2c5fddbe 100644
--- a/example/ADM_PCIE_9V3/fpga_25g/ip/axis_width_converter.tcl
+++ b/example/ADM_PCIE_9V3/fpga_25g/ip/axis_width_converter.tcl
@@ -1,8 +1,8 @@
create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_dwidth_converter_256_64
-set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {256} CONFIG.M_TDATA_NUM_BYTES {64} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {0}] [get_ips axis_dwidth_converter_256_64]
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {32} CONFIG.M_TDATA_NUM_BYTES {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {0}] [get_ips axis_dwidth_converter_256_64]
generate_target {all} [get_ips axis_dwidth_converter_256_64]
create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_dwidth_converter_64_256
-set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {64} CONFIG.M_TDATA_NUM_BYTES {256} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {0}] [get_ips axis_dwidth_converter_64_256]
+set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {8} CONFIG.M_TDATA_NUM_BYTES {32} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {0}] [get_ips axis_dwidth_converter_64_256]
generate_target {all} [get_ips axis_dwidth_converter_64_256]
diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
index 9dae4fa9b87c3732a58d6d1f16ddd4d49ad3990a..9294b54c8e848a4ff1a382d8288d0511e7e8a607 100644
--- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
+++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
@@ -98,17 +98,17 @@ module fpga
input wire qsfp_int_l,
//input and output payload
- output wire [255:0] rx_payload_axis_tdata_256,
- output wire [7:0] rx_payload_axis_tkeep_256,
- output wire rx_payload_axis_tvalid_256,
- input wire rx_payload_axis_tready_256,
- output wire rx_payload_axis_tlast_256,
-
- input wire [255:0] tx_payload_axis_tdata_256,
- input wire [7:0] tx_payload_axis_tkeep_256,
- input wire tx_payload_axis_tvalid_256,
- output wire tx_payload_axis_tready_256,
- input wire tx_payload_axis_tlast_256,
+ output wire [255:0] rx_payload_axis_tdata,
+ output wire [7:0] rx_payload_axis_tkeep,
+ output wire rx_payload_axis_tvalid,
+ input wire rx_payload_axis_tready,
+ output wire rx_payload_axis_tlast,
+
+ input wire [255:0] tx_payload_axis_tdata,
+ input wire [7:0] tx_payload_axis_tkeep,
+ input wire tx_payload_axis_tvalid,
+ output wire tx_payload_axis_tready,
+ input wire tx_payload_axis_tlast,
//networking parameter
// Configuration
@@ -137,17 +137,6 @@ wire mmcm_rst = 1'b0;
wire mmcm_locked;
wire mmcm_clkfb;
-// 256bit to 64bit convertion
-wire [255:0] rx_payload_axis_tdata_64,
-wire [7:0] rx_payload_axis_tkeep_64,
-wire rx_payload_axis_tvalid_64,
-wire rx_payload_axis_tready_64,
-wire rx_payload_axis_tlast_64,
-wire [255:0] tx_payload_axis_tdata_64,
-wire [7:0] tx_payload_axis_tkeep_64,
-wire tx_payload_axis_tvalid_64,
-wire tx_payload_axis_tready_64,
-wire tx_payload_axis_tlast_64,
IBUFGDS #(
.DIFF_TERM("FALSE"),
@@ -771,37 +760,6 @@ qsfp_1_phy_3_inst (
assign front_led[0] = qsfp_0_rx_block_lock_0;
assign front_led[1] = qsfp_1_rx_block_lock_0;
-axis_dwidth_converter_256_64 (
- aclk(clk_390mhz_int),
- aresetn(rst_390mhz_int),
- s_axis_tvalid(rx_payload_axis_tvalid_256),
- s_axis_tready(rx_payload_axis_tready_256),
- s_axis_tdata(rx_payload_axis_tdata_256),
- s_axis_tkeep(rx_payload_axis_tkeep_256),
- s_axis_tlast(rx_payload_axis_tlast_256),
- m_axis_tvalid(rx_payload_axis_tdata_64),
- m_axis_tready(rx_payload_axis_tready_64),
- m_axis_tdata(rx_payload_axis_tdata_64),
- m_axis_tkeep(rx_payload_axis_tkeep_64),
- m_axis_tlast(rx_payload_axis_tlast_64)
-);
-
-axis_dwidth_converter_64_256 (
- aclk(clk_390mhz_int),
- aresetn(rst_390mhz_int),
- s_axis_tvalid(tx_payload_axis_tdata_64),
- s_axis_tready(tx_payload_axis_tready_64),
- s_axis_tdata(tx_payload_axis_tdata_64),
- s_axis_tkeep(tx_payload_axis_tkeep_64),
- s_axis_tlast(tx_payload_axis_tlast_64),
- m_axis_tvalid(tx_payload_axis_tvalid_256),
- m_axis_tready(tx_payload_axis_tready_256),
- m_axis_tdata(tx_payload_axis_tdata_256),
- m_axis_tkeep(tx_payload_axis_tkeep_256),
- m_axis_tlast(tx_payload_axis_tlast_256)
-);
-
-
fpga_core
core_inst (
/*
@@ -896,17 +854,17 @@ core_inst (
//input and output payload
- .rx_payload_axis_tdata(rx_payload_axis_tdata_64),
- .rx_payload_axis_tkeep(rx_payload_axis_tkeep_64),
- .rx_payload_axis_tvalid(rx_payload_axis_tvalid_64),
- .rx_payload_axis_tready(rx_payload_axis_tready_64),
- .rx_payload_axis_tlast(rx_payload_axis_tlast_64),
-
- .tx_payload_axis_tdata(tx_payload_axis_tdata_64),
- .tx_payload_axis_tkeep(tx_payload_axis_tkeep_64),
- .tx_payload_axis_tvalid(tx_payload_axis_tvalid_64),
- .tx_payload_axis_tready(tx_payload_axis_tready_64),
- .tx_payload_axis_tlast(tx_payload_axis_tlast_64)
+ .rx_payload_axis_tdata(rx_payload_axis_tdata),
+ .rx_payload_axis_tkeep(rx_payload_axis_tkeep),
+ .rx_payload_axis_tvalid(rx_payload_axis_tvalid),
+ .rx_payload_axis_tready(rx_payload_axis_tready),
+ .rx_payload_axis_tlast(rx_payload_axis_tlast),
+
+ .tx_payload_axis_tdata(tx_payload_axis_tdata),
+ .tx_payload_axis_tkeep(tx_payload_axis_tkeep),
+ .tx_payload_axis_tvalid(tx_payload_axis_tvalid),
+ .tx_payload_axis_tready(tx_payload_axis_tready),
+ .tx_payload_axis_tlast(tx_payload_axis_tlast)
);
endmodule
diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
index e398618e200db095d3269da868227c45ab093ba7..6c483bb748ce539ff9697f121a2973caaa7a9d0c 100644
--- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
+++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
@@ -120,14 +120,13 @@ module fpga_core #
input wire [7:0] qsfp_1_rxc_3,
//input and output payload
-
- output wire [63:0] rx_payload_axis_tdata,
+ output wire [255:0] rx_payload_axis_tdata,
output wire [7:0] rx_payload_axis_tkeep,
output wire rx_payload_axis_tvalid,
input wire rx_payload_axis_tready,
output wire rx_payload_axis_tlast,
- input wire [63:0] tx_payload_axis_tdata,
+ input wire [255:0] tx_payload_axis_tdata,
input wire [7:0] tx_payload_axis_tkeep,
input wire tx_payload_axis_tvalid,
output wire tx_payload_axis_tready,
@@ -150,6 +149,50 @@ initial begin
#1;
end
+// 256bit to 64bit convertion
+wire [255:0] rx_payload_axis_tdata_64,
+wire [7:0] rx_payload_axis_tkeep_64,
+wire rx_payload_axis_tvalid_64,
+wire rx_payload_axis_tready_64,
+wire rx_payload_axis_tlast_64,
+wire [255:0] tx_payload_axis_tdata_64,
+wire [7:0] tx_payload_axis_tkeep_64,
+wire tx_payload_axis_tvalid_64,
+wire tx_payload_axis_tready_64,
+wire tx_payload_axis_tlast_64,
+
+
+axis_dwidth_converter_256_64 (
+ aclk(clk_390mhz_int),
+ aresetn(rst_390mhz_int),
+ s_axis_tvalid(tx_payload_axis_tvalid),
+ s_axis_tready(tx_payload_axis_tready),
+ s_axis_tdata(tx_payload_axis_tdata),
+ s_axis_tkeep(tx_payload_axis_tkeep),
+ s_axis_tlast(tx_payload_axis_tlast),
+ m_axis_tvalid(tx_payload_axis_tdata_64),
+ m_axis_tready(tx_payload_axis_tready_64),
+ m_axis_tdata(tx_payload_axis_tdata_64),
+ m_axis_tkeep(tx_payload_axis_tkeep_64),
+ m_axis_tlast(tx_payload_axis_tlast_64)
+);
+
+axis_dwidth_converter_64_256 (
+ aclk(clk_390mhz_int),
+ aresetn(rst_390mhz_int),
+ s_axis_tvalid(rx_payload_axis_tdata_64),
+ s_axis_tready(rx_payload_axis_tready_64),
+ s_axis_tdata(rx_payload_axis_tdata_64),
+ s_axis_tkeep(rx_payload_axis_tkeep_64),
+ s_axis_tlast(rx_payload_axis_tlast_64),
+ m_axis_tvalid(rx_payload_axis_tvalid),
+ m_axis_tready(rx_payload_axis_tready),
+ m_axis_tdata(rx_payload_axis_tdata),
+ m_axis_tkeep(rx_payload_axis_tkeep),
+ m_axis_tlast(rx_payload_axis_tlast)
+);
+
+
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
@@ -196,6 +239,16 @@ assign tx_eth_src_mac = local_mac;
assign tx_eth_type = 16'h800; //hardcoded to be ipv4
*/
+assign rx_payload_axis_tdata_64,
+wire [7:0] rx_payload_axis_tkeep_64,
+wire rx_payload_axis_tvalid_64,
+wire rx_payload_axis_tready_64,
+wire rx_payload_axis_tlast_64,
+wire [255:0] tx_payload_axis_tdata_64,
+wire [7:0] tx_payload_axis_tkeep_64,
+wire tx_payload_axis_tvalid_64,
+wire tx_payload_axis_tready_64,
+wire tx_payload_axis_tlast_64,
// IP frame connections
wire rx_ip_hdr_valid;
@@ -679,11 +732,11 @@ rx_payload_fifo (
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
- .m_axis_tdata(rx_payload_axis_tdata),
- .m_axis_tkeep(rx_payload_axis_tkeep),
- .m_axis_tvalid(rx_payload_axis_tvalid),
- .m_axis_tready(rx_payload_axis_tready),
- .m_axis_tlast(rx_payload_axis_tlast),
+ .m_axis_tdata(rx_payload_axis_tdata_64),
+ .m_axis_tkeep(rx_payload_axis_tkeep_64),
+ .m_axis_tvalid(rx_payload_axis_tvalid_64),
+ .m_axis_tready(rx_payload_axis_tready_64),
+ .m_axis_tlast(rx_payload_axis_tlast_64),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
@@ -710,11 +763,11 @@ tx_payload_fifo (
.rst(rst),
// AXI input
- .s_axis_tdata(tx_payload_axis_tdata),
- .s_axis_tkeep(tx_payload_axis_tkeep),
- .s_axis_tvalid(tx_payload_axis_tvalid),
- .s_axis_tready(tx_payload_axis_tready),
- .s_axis_tlast(tx_payload_axis_tlast),
+ .s_axis_tdata(tx_payload_axis_tdata_64),
+ .s_axis_tkeep(tx_payload_axis_tkeep_64),
+ .s_axis_tvalid(tx_payload_axis_tvalid_64),
+ .s_axis_tready(tx_payload_axis_tready_64),
+ .s_axis_tlast(tx_payload_axis_tlast_64),
.s_axis_tid(8'b0),
.s_axis_tdest(8'b0),
.s_axis_tuser(1'b0),
diff --git a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
index 7fd877bdc2ef247445e8577b05c18922438b13f9..29426fb6b238276fb5d72e8a42952a2fa5a53eaa 100644
--- a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
+++ b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
@@ -58,6 +58,17 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+VERILOG_SOURCES += ../../ip/axis_dwidth_converter_64_256/sim/axis_dwidth_converter_64_256.v
+VERILOG_SOURCES += ../../ip/axis_dwidth_converter_64_256/hdl/axis_dwidth_converter_v1_1_vl_rfs.v
+VERILOG_SOURCES += ../../ip/axis_dwidth_converter_64_256/hdl/axis_infrastructure_v1_1_vl_rfs.v
+VERILOG_SOURCES += ../../ip/axis_dwidth_converter_64_256/hdl/axis_register_slice_v1_1_vl_rfs.v
+VHDL_SOURCES += ../../ip/axis_dwidth_converter_64_256/hdl/axis_infrastructure_v1_1_0.vh
+
+VERILOG_SOURCES += ../../ip/axis_dwidth_converter_256_64/sim/axis_dwidth_converter_64_256.v
+VERILOG_SOURCES += ../../ip/axis_dwidth_converter_256_64/hdl/axis_dwidth_converter_v1_1_vl_rfs.v
+VERILOG_SOURCES += ../../ip/axis_dwidth_converter_256_64/hdl/axis_infrastructure_v1_1_vl_rfs.v
+VERILOG_SOURCES += ../../ip/axis_dwidth_converter_256_64/hdl/axis_register_slice_v1_1_vl_rfs.v
+VHDL_SOURCES += ../../ip/axis_dwidth_converter_256_64/hdl/axis_infrastructure_v1_1_0.vh
# module parameters
#export PARAM_A ?= value