diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 0f56f27c946fe29fa648bf64bd0f15c532240383..4ee71dc047c3c5df6b87ee563cae2311bb628e0f 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -93,6 +93,28 @@ module fpga ( output wire qsfp_reset_l, input wire qsfp_int_l + + //input and output payload + output wire [63:0] rx_payload_axis_tdata, + output wire [7:0] rx_payload_axis_tkeep, + output wire rx_payload_axis_tvalid, + input wire rx_payload_axis_tready, + output wire rx_payload_axis_tlast, + + input wire [63:0] tx_payload_axis_tdata, + input wire [7:0] tx_payload_axis_tkeep, + input wire tx_payload_axis_tvalid, + output wire tx_payload_axis_tready, + input wire tx_payload_axis_tlast, + + //networking parameter + // Configuration + input wire [47:0] local_mac, + input wire [31:0] local_ip, + input wire [31:0] gateway_ip, + input wire [31:0] subnet_mask, + input wire [47:0] dest_mac, // is not used, discovered by arp instead + input wire [31:0] dest_ip ); // Clock and reset @@ -814,26 +836,27 @@ core_inst ( .qsfp_1_rxd_3(qsfp_1_rxd_3_int), .qsfp_1_rxc_3(qsfp_1_rxc_3_int), - // - .rx_payload_axis_tdata(), - .rx_udp_payload_axis_tkeep(), - .rx_udp_payload_axis_tvalid(), - .rx_udp_payload_axis_tready(1), - .rx_udp_payload_axis_tlast(), - - .tx_payload_axis_tdata(0), - .tx_udp_payload_axis_tkeep(0), - .tx_udp_payload_axis_tvalid(1), - .tx_udp_payload_axis_tready(), - .tx_udp_payload_axis_tlast(0), - //network config - .local_mac(48'h02_00_00_00_00_00), - .local_ip({8'd192, 8'd168, 8'd1, 8'd128}) , - .gateway_ip({8'd192, 8'd168, 8'd1, 8'd1}) , - .subnet_mask({8'd255, 8'd255, 8'd255, 8'd0}), - .dest_mac(48'h02_00_00_00_00_01), - .dest_ip({8'd192, 8'd168, 8'd1, 8'd129}) + .local_mac, + .local_ip , + .gateway_ip , + .subnet_mask, + .dest_mac, + .dest_ip, + + //input and output payload + + .rx_payload_axis_tdata, + .rx_payload_axis_tkeep, + .rx_payload_axis_tvalid, + .rx_payload_axis_tready, + .rx_payload_axis_tlast, + + .tx_payload_axis_tdata, + .tx_payload_axis_tkeep, + .tx_payload_axis_tvalid, + .tx_payload_axis_tready, + .tx_payload_axis_tlast ); endmodule diff --git a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/results.xml b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/results.xml index 68b8e5fea1f97c331d71741280506d7de1dc1c7d..83a089b7c0f101ab76e988a5055ecce6dbe04128 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/results.xml +++ b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/results.xml @@ -1,6 +1,6 @@ <testsuites name="results"> <testsuite name="all" package="all"> - <property name="random_seed" value="1651005841" /> - <testcase name="run_test" classname="test_fpga_core" file="/home/haiyang3/verilog-ethernet/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py" lineno="187" time="1.4983394145965576" sim_time_ns="1751.041" ratio_time="1168.6544336628058" /> + <property name="random_seed" value="1651012294" /> + <testcase name="run_test" classname="test_fpga_core" file="/home/haiyang3/verilog-ethernet/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py" lineno="187" time="1.5084054470062256" sim_time_ns="1751.041" ratio_time="1160.8556595147147" /> </testsuite> </testsuites> diff --git a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index bafb7454c9f670f554a5450f36636723a768daff..1119ff01f81712594db90a765fec3e158837c984 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -273,12 +273,12 @@ async def run_test(dut): assert rx_pkt.dst == test_pkt.src assert rx_pkt.src == test_pkt.dst - ''' + assert rx_pkt[IP].dst == test_pkt[IP].src assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - ''' + #assert rx_pkt[UDP].dport == test_pkt[UDP].sport + #assert rx_pkt[UDP].sport == test_pkt[UDP].dport + assert bytes(rx_pkt[UDP].payload) == payload