From 23fb9d0bd8811b3feb7ec318e67e4809834280be Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 16 Mar 2022 18:43:36 -0700
Subject: [PATCH] Remove deprecated assignments

---
 tb/arp/test_arp.py                            | 12 ++---
 tb/arp_cache/test_arp_cache.py                |  8 ++--
 tb/arp_eth_rx/test_arp_eth_rx.py              |  4 +-
 tb/arp_eth_tx/test_arp_eth_tx.py              |  4 +-
 tb/axis_baser_rx_64/test_axis_baser_rx_64.py  |  4 +-
 tb/axis_baser_tx_64/test_axis_baser_tx_64.py  |  8 ++--
 tb/axis_gmii_rx/test_axis_gmii_rx.py          |  8 ++--
 tb/axis_gmii_tx/test_axis_gmii_tx.py          | 10 ++--
 tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py  |  4 +-
 tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py  |  4 +-
 tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py  |  8 ++--
 tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py  |  8 ++--
 tb/baser.py                                   |  4 +-
 tb/eth_axis_rx/test_eth_axis_rx.py            |  4 +-
 tb/eth_axis_tx/test_eth_axis_tx.py            |  4 +-
 tb/eth_mac_10g/test_eth_mac_10g.py            | 14 +++---
 tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py  | 18 ++++----
 tb/eth_mac_1g/test_eth_mac_1g.py              | 24 +++++-----
 tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py    | 28 +++++------
 tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py    |  8 ++--
 .../test_eth_mac_1g_gmii_fifo.py              | 12 ++---
 tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py  | 16 +++----
 .../test_eth_mac_1g_rgmii_fifo.py             | 20 ++++----
 tb/eth_mac_mii/test_eth_mac_mii.py            |  8 ++--
 tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py  |  8 ++--
 tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py    | 14 +++---
 .../test_eth_mac_phy_10g_fifo.py              | 18 ++++----
 tb/eth_phy_10g/test_eth_phy_10g.py            |  8 ++--
 tb/ptp_clock/test_ptp_clock.py                | 46 +++++++++----------
 tb/ptp_clock_cdc/test_ptp_clock_cdc.py        | 12 ++---
 tb/ptp_perout/test_ptp_perout.py              | 42 ++++++++---------
 .../test_xgmii_baser_dec_64.py                |  4 +-
 .../test_xgmii_baser_enc_64.py                |  4 +-
 33 files changed, 199 insertions(+), 199 deletions(-)

diff --git a/tb/arp/test_arp.py b/tb/arp/test_arp.py
index 49569820..a8ebb8f5 100644
--- a/tb/arp/test_arp.py
+++ b/tb/arp/test_arp.py
@@ -93,10 +93,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -138,10 +138,10 @@ async def run_test(dut, idle_inserter=None, backpressure_inserter=None):
     gateway_ip = '192.168.1.1'
     subnet_mask = '255.255.255.0'
 
-    dut.local_mac <= int.from_bytes(mac2str(local_mac), 'big')
-    dut.local_ip <= atol(local_ip)
-    dut.gateway_ip <= atol(gateway_ip)
-    dut.subnet_mask <= atol(subnet_mask)
+    dut.local_mac.value = int.from_bytes(mac2str(local_mac), 'big')
+    dut.local_ip.value = atol(local_ip)
+    dut.gateway_ip.value = atol(gateway_ip)
+    dut.subnet_mask.value = atol(subnet_mask)
 
     for k in range(10):
         await RisingEdge(dut.clk)
diff --git a/tb/arp_cache/test_arp_cache.py b/tb/arp_cache/test_arp_cache.py
index 4e3a6dae..d157b5ee 100644
--- a/tb/arp_cache/test_arp_cache.py
+++ b/tb/arp_cache/test_arp_cache.py
@@ -62,10 +62,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -195,9 +195,9 @@ async def run_test(dut):
     tb.log.info("Clear cache")
 
     await RisingEdge(dut.clk)
-    dut.clear_cache <= 1
+    dut.clear_cache.value = 1
     await RisingEdge(dut.clk)
-    dut.clear_cache <= 0
+    dut.clear_cache.value = 0
 
     await tb.query_request_source.send(CacheOpTransaction(ip=0xc0a80111))
 
diff --git a/tb/arp_eth_rx/test_arp_eth_rx.py b/tb/arp_eth_rx/test_arp_eth_rx.py
index 0bde8634..e294910b 100644
--- a/tb/arp_eth_rx/test_arp_eth_rx.py
+++ b/tb/arp_eth_rx/test_arp_eth_rx.py
@@ -79,10 +79,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
diff --git a/tb/arp_eth_tx/test_arp_eth_tx.py b/tb/arp_eth_tx/test_arp_eth_tx.py
index fb071acb..9506680a 100644
--- a/tb/arp_eth_tx/test_arp_eth_tx.py
+++ b/tb/arp_eth_tx/test_arp_eth_tx.py
@@ -79,10 +79,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
diff --git a/tb/axis_baser_rx_64/test_axis_baser_rx_64.py b/tb/axis_baser_rx_64/test_axis_baser_rx_64.py
index 46bbab59..ddc05e3e 100644
--- a/tb/axis_baser_rx_64/test_axis_baser_rx_64.py
+++ b/tb/axis_baser_rx_64/test_axis_baser_rx_64.py
@@ -67,10 +67,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
diff --git a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py
index 078559ec..e19adfc1 100644
--- a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py
+++ b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py
@@ -68,10 +68,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -80,7 +80,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
 
     tb = TB(dut)
 
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -109,7 +109,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
 
     byte_width = tb.source.width // 8
 
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     for length in range(60, 92):
 
diff --git a/tb/axis_gmii_rx/test_axis_gmii_rx.py b/tb/axis_gmii_rx/test_axis_gmii_rx.py
index 9072852f..ade49c5a 100644
--- a/tb/axis_gmii_rx/test_axis_gmii_rx.py
+++ b/tb/axis_gmii_rx/test_axis_gmii_rx.py
@@ -62,10 +62,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -84,7 +84,7 @@ class TB:
 
     async def _run_enable(self):
         for val in self._enable_generator:
-            self.dut.clk_enable <= val
+            self.dut.clk_enable.value = val
             await RisingEdge(self.dut.clk)
 
 
@@ -93,7 +93,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
     tb = TB(dut)
 
     tb.source.ifg = ifg
-    tb.dut.mii_select <= mii_sel
+    tb.dut.mii_select.value = mii_sel
 
     if enable_gen is not None:
         tb.set_enable_generator(enable_gen())
diff --git a/tb/axis_gmii_tx/test_axis_gmii_tx.py b/tb/axis_gmii_tx/test_axis_gmii_tx.py
index ad42e8a2..b4b5a196 100644
--- a/tb/axis_gmii_tx/test_axis_gmii_tx.py
+++ b/tb/axis_gmii_tx/test_axis_gmii_tx.py
@@ -63,10 +63,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -85,7 +85,7 @@ class TB:
 
     async def _run_enable(self):
         for val in self._enable_generator:
-            self.dut.clk_enable <= val
+            self.dut.clk_enable.value = val
             await RisingEdge(self.dut.clk)
 
 
@@ -93,8 +93,8 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
 
     tb = TB(dut)
 
-    tb.dut.ifg_delay <= ifg
-    tb.dut.mii_select <= mii_sel
+    tb.dut.ifg_delay.value = ifg
+    tb.dut.mii_select.value = mii_sel
 
     if enable_gen is not None:
         tb.set_enable_generator(enable_gen())
diff --git a/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py b/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py
index 7ac45db5..5677c55e 100644
--- a/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py
+++ b/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py
@@ -56,10 +56,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
diff --git a/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py b/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py
index bce6e15f..2a7ec214 100644
--- a/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py
+++ b/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py
@@ -56,10 +56,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
diff --git a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py
index 1a7f3359..91a47453 100644
--- a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py
+++ b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py
@@ -58,10 +58,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -70,7 +70,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
 
     tb = TB(dut)
 
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -99,7 +99,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
 
     byte_width = tb.source.width // 8
 
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     for length in range(60, 92):
 
diff --git a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py
index f36d77bc..cbcf7bb2 100644
--- a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py
+++ b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py
@@ -58,10 +58,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -70,7 +70,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
 
     tb = TB(dut)
 
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -99,7 +99,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
 
     byte_width = tb.source.width // 8
 
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     for length in range(60, 92):
 
diff --git a/tb/baser.py b/tb/baser.py
index 2a9c9320..7024b595 100644
--- a/tb/baser.py
+++ b/tb/baser.py
@@ -358,8 +358,8 @@ class BaseRSerdesSource():
                     data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
                     header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1)
 
-                self.data <= data
-                self.header <= header
+                self.data.value = data
+                self.header.value = header
 
 
 class BaseRSerdesSink:
diff --git a/tb/eth_axis_rx/test_eth_axis_rx.py b/tb/eth_axis_rx/test_eth_axis_rx.py
index 0b8abc5b..d31e4f24 100644
--- a/tb/eth_axis_rx/test_eth_axis_rx.py
+++ b/tb/eth_axis_rx/test_eth_axis_rx.py
@@ -73,10 +73,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
diff --git a/tb/eth_axis_tx/test_eth_axis_tx.py b/tb/eth_axis_tx/test_eth_axis_tx.py
index 66a2c2b4..8a2358c3 100644
--- a/tb/eth_axis_tx/test_eth_axis_tx.py
+++ b/tb/eth_axis_tx/test_eth_axis_tx.py
@@ -74,10 +74,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
diff --git a/tb/eth_mac_10g/test_eth_mac_10g.py b/tb/eth_mac_10g/test_eth_mac_10g.py
index 4fcdf07c..92f0baca 100644
--- a/tb/eth_mac_10g/test_eth_mac_10g.py
+++ b/tb/eth_mac_10g/test_eth_mac_10g.py
@@ -67,12 +67,12 @@ class TB:
         self.dut.tx_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.rx_clk)
         await RisingEdge(self.dut.rx_clk)
-        self.dut.rx_rst <= 1
-        self.dut.tx_rst <= 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
         await RisingEdge(self.dut.rx_clk)
         await RisingEdge(self.dut.rx_clk)
-        self.dut.rx_rst <= 0
-        self.dut.tx_rst <= 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
         await RisingEdge(self.dut.rx_clk)
         await RisingEdge(self.dut.rx_clk)
 
@@ -82,7 +82,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
     tb = TB(dut)
 
     tb.xgmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -109,7 +109,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
     tb = TB(dut)
 
     tb.xgmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -139,7 +139,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
     byte_width = tb.axis_source.width // 8
 
     tb.xgmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     for length in range(60, 92):
 
diff --git a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py
index 53f9f57f..1aa7357a 100644
--- a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py
+++ b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py
@@ -71,14 +71,14 @@ class TB:
         self.dut.tx_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.logic_clk)
         await RisingEdge(self.dut.logic_clk)
-        self.dut.logic_rst <= 1
-        self.dut.rx_rst <= 1
-        self.dut.tx_rst <= 1
+        self.dut.logic_rst.value = 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
         await RisingEdge(self.dut.logic_clk)
         await RisingEdge(self.dut.logic_clk)
-        self.dut.logic_rst <= 0
-        self.dut.rx_rst <= 0
-        self.dut.tx_rst <= 0
+        self.dut.logic_rst.value = 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
         await RisingEdge(self.dut.logic_clk)
         await RisingEdge(self.dut.logic_clk)
 
@@ -88,7 +88,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
     tb = TB(dut)
 
     tb.xgmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -115,7 +115,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
     tb = TB(dut)
 
     tb.xgmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -145,7 +145,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
     byte_width = tb.axis_source.width // 8
 
     tb.xgmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     for length in range(60, 92):
 
diff --git a/tb/eth_mac_1g/test_eth_mac_1g.py b/tb/eth_mac_1g/test_eth_mac_1g.py
index e5104633..24b15ed2 100644
--- a/tb/eth_mac_1g/test_eth_mac_1g.py
+++ b/tb/eth_mac_1g/test_eth_mac_1g.py
@@ -74,12 +74,12 @@ class TB:
         self.dut.tx_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.rx_rst <= 1
-        self.dut.tx_rst <= 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.rx_rst <= 0
-        self.dut.tx_rst <= 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
 
@@ -111,12 +111,12 @@ class TB:
 
     async def _run_enable_rx(self):
         for val in self._enable_generator_rx:
-            self.dut.rx_clk_enable <= val
+            self.dut.rx_clk_enable.value = val
             await RisingEdge(self.dut.rx_clk)
 
     async def _run_enable_tx(self):
         for val in self._enable_generator_tx:
-            self.dut.tx_clk_enable <= val
+            self.dut.tx_clk_enable.value = val
             await RisingEdge(self.dut.tx_clk)
 
 
@@ -125,9 +125,9 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
     tb = TB(dut)
 
     tb.gmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
-    tb.dut.rx_mii_select <= mii_sel
-    tb.dut.tx_mii_select <= mii_sel
+    tb.dut.ifg_delay.value = ifg
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
 
     if enable_gen is not None:
         tb.set_enable_generator_rx(enable_gen())
@@ -158,9 +158,9 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
     tb = TB(dut)
 
     tb.gmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
-    tb.dut.rx_mii_select <= mii_sel
-    tb.dut.tx_mii_select <= mii_sel
+    tb.dut.ifg_delay.value = ifg
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
 
     if enable_gen is not None:
         tb.set_enable_generator_rx(enable_gen())
diff --git a/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py b/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py
index eead2068..8cb333bb 100644
--- a/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py
+++ b/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py
@@ -74,14 +74,14 @@ class TB:
         self.dut.tx_rst.setimmediatevalue(0)
         for k in range(10):
             await RisingEdge(self.dut.logic_clk)
-        self.dut.logic_rst <= 1
-        self.dut.rx_rst <= 1
-        self.dut.tx_rst <= 1
+        self.dut.logic_rst.value = 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
         for k in range(10):
             await RisingEdge(self.dut.logic_clk)
-        self.dut.logic_rst <= 0
-        self.dut.rx_rst <= 0
-        self.dut.tx_rst <= 0
+        self.dut.logic_rst.value = 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
         for k in range(10):
             await RisingEdge(self.dut.logic_clk)
 
@@ -113,12 +113,12 @@ class TB:
 
     async def _run_enable_rx(self):
         for val in self._enable_generator_rx:
-            self.dut.rx_clk_enable <= val
+            self.dut.rx_clk_enable.value = val
             await RisingEdge(self.dut.rx_clk)
 
     async def _run_enable_tx(self):
         for val in self._enable_generator_tx:
-            self.dut.tx_clk_enable <= val
+            self.dut.tx_clk_enable.value = val
             await RisingEdge(self.dut.tx_clk)
 
 
@@ -127,9 +127,9 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
     tb = TB(dut)
 
     tb.gmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
-    tb.dut.rx_mii_select <= mii_sel
-    tb.dut.tx_mii_select <= mii_sel
+    tb.dut.ifg_delay.value = ifg
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
 
     if enable_gen is not None:
         tb.set_enable_generator_rx(enable_gen())
@@ -160,9 +160,9 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
     tb = TB(dut)
 
     tb.gmii_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
-    tb.dut.rx_mii_select <= mii_sel
-    tb.dut.tx_mii_select <= mii_sel
+    tb.dut.ifg_delay.value = ifg
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
 
     if enable_gen is not None:
         tb.set_enable_generator_rx(enable_gen())
diff --git a/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py b/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py
index f50136bd..295427ef 100644
--- a/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py
+++ b/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py
@@ -59,10 +59,10 @@ class TB:
         self.dut.gtx_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.gtx_rst <= 1
+        self.dut.gtx_rst.value = 1
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.gtx_rst <= 0
+        self.dut.gtx_rst.value = 0
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
 
@@ -75,7 +75,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.gmii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     tb.set_speed(speed)
 
@@ -114,7 +114,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.gmii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     tb.set_speed(speed)
 
diff --git a/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py b/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py
index 106c4fb3..7ed984a0 100644
--- a/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py
+++ b/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py
@@ -61,12 +61,12 @@ class TB:
         self.dut.logic_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.gtx_rst <= 1
-        self.dut.logic_rst <= 1
+        self.dut.gtx_rst.value = 1
+        self.dut.logic_rst.value = 1
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.gtx_rst <= 0
-        self.dut.logic_rst <= 0
+        self.dut.gtx_rst.value = 0
+        self.dut.logic_rst.value = 0
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
 
@@ -79,7 +79,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.gmii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     tb.set_speed(speed)
 
@@ -118,7 +118,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.gmii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     tb.set_speed(speed)
 
diff --git a/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py b/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py
index c0896e94..52328b87 100644
--- a/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py
+++ b/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py
@@ -61,23 +61,23 @@ class TB:
         self.dut.gtx_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.gtx_clk)
         await RisingEdge(self.dut.gtx_clk)
-        self.dut.gtx_rst <= 1
+        self.dut.gtx_rst.value = 1
         await RisingEdge(self.dut.gtx_clk)
         await RisingEdge(self.dut.gtx_clk)
-        self.dut.gtx_rst <= 0
+        self.dut.gtx_rst.value = 0
         await RisingEdge(self.dut.gtx_clk)
         await RisingEdge(self.dut.gtx_clk)
 
     async def _run_gtx_clk(self):
         t = Timer(2, 'ns')
         while True:
-            self.dut.gtx_clk <= 1
+            self.dut.gtx_clk.value = 1
             await t
-            self.dut.gtx_clk90 <= 1
+            self.dut.gtx_clk90.value = 1
             await t
-            self.dut.gtx_clk <= 0
+            self.dut.gtx_clk.value = 0
             await t
-            self.dut.gtx_clk90 <= 0
+            self.dut.gtx_clk90.value = 0
             await t
 
 
@@ -86,7 +86,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.rgmii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -123,7 +123,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.rgmii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
diff --git a/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py b/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py
index fb935d04..3e162174 100644
--- a/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py
+++ b/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py
@@ -65,25 +65,25 @@ class TB:
         self.dut.logic_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.gtx_clk)
         await RisingEdge(self.dut.gtx_clk)
-        self.dut.gtx_rst <= 1
-        self.dut.logic_rst <= 1
+        self.dut.gtx_rst.value = 1
+        self.dut.logic_rst.value = 1
         await RisingEdge(self.dut.gtx_clk)
         await RisingEdge(self.dut.gtx_clk)
-        self.dut.gtx_rst <= 0
-        self.dut.logic_rst <= 0
+        self.dut.gtx_rst.value = 0
+        self.dut.logic_rst.value = 0
         await RisingEdge(self.dut.gtx_clk)
         await RisingEdge(self.dut.gtx_clk)
 
     async def _run_gtx_clk(self):
         t = Timer(2, 'ns')
         while True:
-            self.dut.gtx_clk <= 1
+            self.dut.gtx_clk.value = 1
             await t
-            self.dut.gtx_clk90 <= 1
+            self.dut.gtx_clk90.value = 1
             await t
-            self.dut.gtx_clk <= 0
+            self.dut.gtx_clk.value = 0
             await t
-            self.dut.gtx_clk90 <= 0
+            self.dut.gtx_clk90.value = 0
             await t
 
 
@@ -92,7 +92,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.rgmii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -129,7 +129,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.rgmii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
diff --git a/tb/eth_mac_mii/test_eth_mac_mii.py b/tb/eth_mac_mii/test_eth_mac_mii.py
index f973863f..b144a509 100644
--- a/tb/eth_mac_mii/test_eth_mac_mii.py
+++ b/tb/eth_mac_mii/test_eth_mac_mii.py
@@ -56,10 +56,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
 
@@ -69,7 +69,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.mii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -96,7 +96,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.mii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
diff --git a/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py b/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py
index babeb117..d154fb85 100644
--- a/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py
+++ b/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py
@@ -59,10 +59,10 @@ class TB:
         self.dut.logic_rst.setimmediatevalue(0)
         for k in range(10):
             await RisingEdge(self.dut.logic_clk)
-        self.dut.logic_rst <= 1
+        self.dut.logic_rst.value = 1
         for k in range(10):
             await RisingEdge(self.dut.logic_clk)
-        self.dut.logic_rst <= 0
+        self.dut.logic_rst.value = 0
         for k in range(10):
             await RisingEdge(self.dut.logic_clk)
 
@@ -72,7 +72,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.mii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -99,7 +99,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
     tb = TB(dut, speed)
 
     tb.mii_phy.rx.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
diff --git a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py
index 3276ed47..93d7724a 100644
--- a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py
+++ b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py
@@ -81,12 +81,12 @@ class TB:
         self.dut.tx_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.rx_clk)
         await RisingEdge(self.dut.rx_clk)
-        self.dut.rx_rst <= 1
-        self.dut.tx_rst <= 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
         await RisingEdge(self.dut.rx_clk)
         await RisingEdge(self.dut.rx_clk)
-        self.dut.rx_rst <= 0
-        self.dut.tx_rst <= 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
         await RisingEdge(self.dut.rx_clk)
         await RisingEdge(self.dut.rx_clk)
 
@@ -96,7 +96,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
     tb = TB(dut)
 
     tb.serdes_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -130,7 +130,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
     tb = TB(dut)
 
     tb.serdes_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -160,7 +160,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
     byte_width = tb.axis_source.width // 8
 
     tb.serdes_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     for length in range(60, 92):
 
diff --git a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py
index 057395e1..c7019830 100644
--- a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py
+++ b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py
@@ -85,14 +85,14 @@ class TB:
         self.dut.tx_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.logic_clk)
         await RisingEdge(self.dut.logic_clk)
-        self.dut.logic_rst <= 1
-        self.dut.rx_rst <= 1
-        self.dut.tx_rst <= 1
+        self.dut.logic_rst.value = 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
         await RisingEdge(self.dut.logic_clk)
         await RisingEdge(self.dut.logic_clk)
-        self.dut.logic_rst <= 0
-        self.dut.rx_rst <= 0
-        self.dut.tx_rst <= 0
+        self.dut.logic_rst.value = 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
         await RisingEdge(self.dut.logic_clk)
         await RisingEdge(self.dut.logic_clk)
 
@@ -102,7 +102,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
     tb = TB(dut)
 
     tb.serdes_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -136,7 +136,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
     tb = TB(dut)
 
     tb.serdes_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     await tb.reset()
 
@@ -166,7 +166,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
     byte_width = tb.axis_source.width // 8
 
     tb.serdes_source.ifg = ifg
-    tb.dut.ifg_delay <= ifg
+    tb.dut.ifg_delay.value = ifg
 
     for length in range(60, 92):
 
diff --git a/tb/eth_phy_10g/test_eth_phy_10g.py b/tb/eth_phy_10g/test_eth_phy_10g.py
index d6742289..73275f61 100644
--- a/tb/eth_phy_10g/test_eth_phy_10g.py
+++ b/tb/eth_phy_10g/test_eth_phy_10g.py
@@ -72,12 +72,12 @@ class TB:
         self.dut.rx_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.tx_rst <= 1
-        self.dut.rx_rst <= 1
+        self.dut.tx_rst.value = 1
+        self.dut.rx_rst.value = 1
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.tx_rst <= 0
-        self.dut.rx_rst <= 0
+        self.dut.tx_rst.value = 0
+        self.dut.rx_rst.value = 0
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
 
diff --git a/tb/ptp_clock/test_ptp_clock.py b/tb/ptp_clock/test_ptp_clock.py
index 4bed978d..988aea37 100644
--- a/tb/ptp_clock/test_ptp_clock.py
+++ b/tb/ptp_clock/test_ptp_clock.py
@@ -66,10 +66,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -122,15 +122,15 @@ async def run_load_timestamps(dut):
 
     await RisingEdge(dut.clk)
 
-    dut.input_ts_96 <= 12345678
-    dut.input_ts_96_valid <= 1
-    dut.input_ts_64 <= 12345678
-    dut.input_ts_64_valid <= 1
+    dut.input_ts_96.value = 12345678
+    dut.input_ts_96_valid.value = 1
+    dut.input_ts_64.value = 12345678
+    dut.input_ts_64_valid.value = 1
 
     await RisingEdge(dut.clk)
 
-    dut.input_ts_96_valid <= 0
-    dut.input_ts_64_valid <= 0
+    dut.input_ts_96_valid.value = 0
+    dut.input_ts_64_valid.value = 0
 
     await RisingEdge(dut.clk)
 
@@ -178,15 +178,15 @@ async def run_seconds_increment(dut):
 
     await RisingEdge(dut.clk)
 
-    dut.input_ts_96 <= 999990000*2**16
-    dut.input_ts_96_valid <= 1
-    dut.input_ts_64 <= 999990000*2**16
-    dut.input_ts_64_valid <= 1
+    dut.input_ts_96.value = 999990000*2**16
+    dut.input_ts_96_valid.value = 1
+    dut.input_ts_64.value = 999990000*2**16
+    dut.input_ts_64_valid.value = 1
 
     await RisingEdge(dut.clk)
 
-    dut.input_ts_96_valid <= 0
-    dut.input_ts_64_valid <= 0
+    dut.input_ts_96_valid.value = 0
+    dut.input_ts_64_valid.value = 0
 
     await RisingEdge(dut.clk)
 
@@ -239,13 +239,13 @@ async def run_frequency_adjustment(dut):
 
     await RisingEdge(dut.clk)
 
-    dut.input_period_ns <= 0x6
-    dut.input_period_fns <= 0x6624
-    dut.input_period_valid <= 1
+    dut.input_period_ns.value = 0x6
+    dut.input_period_fns.value = 0x6624
+    dut.input_period_valid.value = 1
 
     await RisingEdge(dut.clk)
 
-    dut.input_period_valid <= 0
+    dut.input_period_valid.value = 0
 
     await RisingEdge(dut.clk)
     await RisingEdge(dut.clk)
@@ -290,14 +290,14 @@ async def run_drift_adjustment(dut):
 
     await tb.reset()
 
-    dut.input_drift_ns <= 0
-    dut.input_drift_fns <= 20
-    dut.input_drift_rate <= 5
-    dut.input_drift_valid <= 1
+    dut.input_drift_ns.value = 0
+    dut.input_drift_fns.value = 20
+    dut.input_drift_rate.value = 5
+    dut.input_drift_valid.value = 1
 
     await RisingEdge(dut.clk)
 
-    dut.input_drift_valid <= 0
+    dut.input_drift_valid.value = 0
 
     await RisingEdge(dut.clk)
     await RisingEdge(dut.clk)
diff --git a/tb/ptp_clock_cdc/test_ptp_clock_cdc.py b/tb/ptp_clock_cdc/test_ptp_clock_cdc.py
index 3b9d7482..f3a26f95 100644
--- a/tb/ptp_clock_cdc/test_ptp_clock_cdc.py
+++ b/tb/ptp_clock_cdc/test_ptp_clock_cdc.py
@@ -73,12 +73,12 @@ class TB:
         self.dut.output_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.input_clk)
         await RisingEdge(self.dut.input_clk)
-        self.dut.input_rst <= 1
-        self.dut.output_rst <= 1
+        self.dut.input_rst.value = 1
+        self.dut.output_rst.value = 1
         for k in range(10):
             await RisingEdge(self.dut.input_clk)
-        self.dut.input_rst <= 0
-        self.dut.output_rst <= 0
+        self.dut.input_rst.value = 0
+        self.dut.output_rst.value = 0
         for k in range(10):
             await RisingEdge(self.dut.input_clk)
 
@@ -94,9 +94,9 @@ class TB:
 
         while True:
             await t
-            self.dut.output_clk <= 1
+            self.dut.output_clk.value = 1
             await t
-            self.dut.output_clk <= 0
+            self.dut.output_clk.value = 0
 
     def get_input_ts_ns(self):
         ts = self.dut.input_ts.value.integer
diff --git a/tb/ptp_perout/test_ptp_perout.py b/tb/ptp_perout/test_ptp_perout.py
index 13a126f9..32698907 100644
--- a/tb/ptp_perout/test_ptp_perout.py
+++ b/tb/ptp_perout/test_ptp_perout.py
@@ -64,10 +64,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -79,39 +79,39 @@ async def run_test(dut):
 
     await tb.reset()
 
-    dut.enable <= 1
+    dut.enable.value = 1
 
     await RisingEdge(dut.clk)
 
-    dut.input_start <= 100 << 16
-    dut.input_start_valid <= 1
-    dut.input_period <= 100 << 16
-    dut.input_period_valid <= 1
-    dut.input_width <= 50 << 16
-    dut.input_width_valid <= 1
+    dut.input_start.value = 100 << 16
+    dut.input_start_valid.value = 1
+    dut.input_period.value = 100 << 16
+    dut.input_period_valid.value = 1
+    dut.input_width.value = 50 << 16
+    dut.input_width_valid.value = 1
 
     await RisingEdge(dut.clk)
 
-    dut.input_start_valid <= 0
-    dut.input_period_valid <= 0
-    dut.input_width_valid <= 0
+    dut.input_start_valid.value = 0
+    dut.input_period_valid.value = 0
+    dut.input_width_valid.value = 0
 
     await Timer(10000, 'ns')
 
     await RisingEdge(dut.clk)
 
-    dut.input_start <= 0 << 16
-    dut.input_start_valid <= 1
-    dut.input_period <= 100 << 16
-    dut.input_period_valid <= 1
-    dut.input_width <= 50 << 16
-    dut.input_width_valid <= 1
+    dut.input_start.value = 0 << 16
+    dut.input_start_valid.value = 1
+    dut.input_period.value = 100 << 16
+    dut.input_period_valid.value = 1
+    dut.input_width.value = 50 << 16
+    dut.input_width_valid.value = 1
 
     await RisingEdge(dut.clk)
 
-    dut.input_start_valid <= 0
-    dut.input_period_valid <= 0
-    dut.input_width_valid <= 0
+    dut.input_start_valid.value = 0
+    dut.input_period_valid.value = 0
+    dut.input_width_valid.value = 0
 
     await Timer(10000, 'ns')
 
diff --git a/tb/xgmii_baser_dec_64/test_xgmii_baser_dec_64.py b/tb/xgmii_baser_dec_64/test_xgmii_baser_dec_64.py
index bfeb226f..5b6c32be 100644
--- a/tb/xgmii_baser_dec_64/test_xgmii_baser_dec_64.py
+++ b/tb/xgmii_baser_dec_64/test_xgmii_baser_dec_64.py
@@ -64,10 +64,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
diff --git a/tb/xgmii_baser_enc_64/test_xgmii_baser_enc_64.py b/tb/xgmii_baser_enc_64/test_xgmii_baser_enc_64.py
index 6b25d26a..677a2270 100644
--- a/tb/xgmii_baser_enc_64/test_xgmii_baser_enc_64.py
+++ b/tb/xgmii_baser_enc_64/test_xgmii_baser_enc_64.py
@@ -64,10 +64,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
-- 
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