diff --git a/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc b/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc
index 5718ae810fd65a610dea9d0c248595f13f50b697..19eeb010887f99d02544e702b5e9e340c12c991e 100644
--- a/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc
+++ b/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc
@@ -13,9 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone}     [current_design]
 set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 300 MHz system clock
-set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
-set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
-create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
+ 
+create_clock -period 3.333 -name clk_300mhz [get_ports clk]
 
 # LEDs
 set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}]
diff --git a/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
index d4db9f3701c931ed9256b9b0059614068706b717..3fccbbd1728a4a1c1f7b326daf27c6e199e314c5 100644
--- a/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
+++ b/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
@@ -48,6 +48,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
 SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
 SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
 SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_adapter.v
 
 # XDC files
 XDC_FILES = fpga.xdc
diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
index f28a6c083eaf0f8a02bd3fb5b87b20b93312e9f7..c5ccea3f5112c17561dc601d89f396be6f490b57 100644
--- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
+++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
@@ -69,7 +69,7 @@ module fpga
     input  wire       qsfp_0_mgt_refclk_n,
     input  wire       qsfp_0_modprs_l,
     output wire       qsfp_0_sel_l,
-    output wire qsfp_0_mgt_refclk,
+    output wire qsfp_0_usr_clk,
 
 
     output wire       qsfp_1_tx_0_p,
@@ -92,7 +92,7 @@ module fpga
     input  wire       qsfp_1_mgt_refclk_n,
     input  wire       qsfp_1_modprs_l,
     output wire       qsfp_1_sel_l,
-    output wire qsfp_1_mgt_refclk,
+    output wire qsfp_1_usr_clk,
 
     output wire       qsfp_reset_l,
     input  wire       qsfp_int_l,
@@ -129,6 +129,9 @@ wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
+assign qsfp_0_usr_clk = clk_125mhz_int;
+assign qsfp_1_usr_clk = clk_125mhz_int;
+
 // Internal 390.625 MHz clock
 wire clk_390mhz_int;
 wire rst_390mhz_int;
@@ -137,13 +140,13 @@ wire mmcm_rst = 1'b0;
 wire mmcm_locked;
 wire mmcm_clkfb;
 
+/*
 
 IBUFGDS #(
    .DIFF_TERM("FALSE"),
    .IBUF_LOW_PWR("FALSE")   
 )
 
-/*
 clk_300mhz_ibufg_inst (
    .O   (clk_300mhz_ibufg),
    .I   (clk_300mhz_p),
@@ -178,12 +181,7 @@ MMCME3_BASE #(
     .CLKOUT5_DIVIDE(1),
     .CLKOUT5_DUTY_CYCLE(0.5),
     .CLKOUT5_PHASE(0),
-    .CLKOUT6_DIVIDE(1),
-    .CLKOUT6_DUTY_CYCLE(0.5),
-    .CLKOUT6_PHASE(0),
-    .CLKFBOUT_MULT_F(10),
-    .CLKFBOUT_PHASE(0),
-    .DIVCLK_DIVIDE(3),
+    .CLKOUT6_DIVIDE(1),opencapi
     .REF_JITTER1(0.010),
     .CLKIN1_PERIOD(3.333),
     .STARTUP_WAIT("FALSE"),
@@ -287,7 +285,7 @@ wire qsfp_0_rx_block_lock_0;
 wire qsfp_0_rx_block_lock_1;
 wire qsfp_0_rx_block_lock_2;
 wire qsfp_0_rx_block_lock_3;
-
+ 
 wire qsfp_0_mgt_refclk;
 
 IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
@@ -845,12 +843,12 @@ core_inst (
     .qsfp_1_rxc_3(qsfp_1_rxc_3_int),
     
     //network config
-    .local_mac,
-    .local_ip  ,
-    .gateway_ip ,
-    .subnet_mask,
-    .dest_mac,   
-    .dest_ip,
+    .local_mac(local_mac),
+    .local_ip(local_ip),
+    .gateway_ip(gateway_ip) ,
+    .subnet_mask(subnet_mask),
+    .dest_mac(dest_mac),   
+    .dest_ip(dest_ip),
 
     //input and output payload
 
diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
index 36bc7b1e50c6cc1bd89fdbb510626bf71c308eb2..075d22e0e64230cd273cfaab262b06066eb084e5 100644
--- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
+++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
@@ -172,8 +172,8 @@ axis_adapter #
     .USER_ENABLE(0)
 ) axis_dwidth_converter_256_64_inst
 (
-    .clk,
-    .rst,
+    .clk(clk),
+    .rst(rst),
     .s_axis_tdata(tx_payload_axis_tdata),
     .s_axis_tkeep(tx_payload_axis_tkeep),
     .s_axis_tvalid(tx_payload_axis_tvalid),
@@ -194,8 +194,8 @@ axis_adapter #
     .USER_ENABLE(0)
 ) axis_dwidth_converter_64_256_inst
 (
-    .clk,
-    .rst,
+    .clk(clk),
+    .rst(rst),
 
     .s_axis_tdata(rx_payload_axis_tdata_64),
     .s_axis_tkeep(rx_payload_axis_tkeep_64),