From 0f2db26a8ec336ba1220036fef4cb5ab11ff6dd5 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 16 Mar 2022 19:01:00 -0700
Subject: [PATCH] Simplify logic in PTP clock module
---
rtl/ptp_clock.v | 26 +++++++++++++++-----------
tb/ptp_clock/test_ptp_clock.py | 3 +++
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/rtl/ptp_clock.v b/rtl/ptp_clock.v
index 0e89277a..b1bebbff 100644
--- a/rtl/ptp_clock.v
+++ b/rtl/ptp_clock.v
@@ -184,15 +184,7 @@ always @(posedge clk) begin
end
// 96 bit timestamp
- if (input_ts_96_valid) begin
- // load timestamp
- {ts_96_ns_inc_reg, ts_96_fns_inc_reg} <= (FNS_WIDTH > 16 ? input_ts_96[45:0] << (FNS_WIDTH-16) : input_ts_96[45:0] >> (16-FNS_WIDTH)) + {ts_inc_ns_reg, ts_inc_fns_reg};
- {ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} <= (FNS_WIDTH > 16 ? input_ts_96[45:0] << (FNS_WIDTH-16) : input_ts_96[45:0] >> (16-FNS_WIDTH)) + {ts_inc_ns_reg, ts_inc_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}};
- ts_96_s_reg <= input_ts_96[95:48];
- ts_96_ns_reg <= input_ts_96[45:16];
- ts_96_fns_reg <= FNS_WIDTH > 16 ? input_ts_96[15:0] << (FNS_WIDTH-16) : input_ts_96[15:0] >> (16-FNS_WIDTH);
- ts_step_reg <= 1;
- end else if (!ts_96_ns_ovf_reg[30]) begin
+ if (!ts_96_ns_ovf_reg[30]) begin
// if the overflow lookahead did not borrow, one second has elapsed
// increment seconds field, pre-compute both normal increment and overflow values
{ts_96_ns_inc_reg, ts_96_fns_inc_reg} <= {ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
@@ -207,13 +199,25 @@ always @(posedge clk) begin
ts_96_s_reg <= ts_96_s_reg;
end
+ if (input_ts_96_valid) begin
+ // load timestamp
+ ts_96_s_reg <= input_ts_96[95:48];
+ ts_96_ns_reg <= input_ts_96[45:16];
+ ts_96_ns_inc_reg <= input_ts_96[45:16];
+ ts_96_ns_ovf_reg <= 31'h7fffffff;
+ ts_96_fns_reg <= FNS_WIDTH > 16 ? input_ts_96[15:0] << (FNS_WIDTH-16) : input_ts_96[15:0] >> (16-FNS_WIDTH);
+ ts_96_fns_inc_reg <= FNS_WIDTH > 16 ? input_ts_96[15:0] << (FNS_WIDTH-16) : input_ts_96[15:0] >> (16-FNS_WIDTH);
+ ts_96_fns_ovf_reg <= {FNS_WIDTH{1'b1}};
+ ts_step_reg <= 1;
+ end
+
// 64 bit timestamp
+ {ts_64_ns_reg, ts_64_fns_reg} <= {ts_64_ns_reg, ts_64_fns_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
+
if (input_ts_64_valid) begin
// load timestamp
{ts_64_ns_reg, ts_64_fns_reg} <= input_ts_64;
ts_step_reg <= 1;
- end else begin
- {ts_64_ns_reg, ts_64_fns_reg} <= {ts_64_ns_reg, ts_64_fns_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
end
pps_reg <= !ts_96_ns_ovf_reg[30];
diff --git a/tb/ptp_clock/test_ptp_clock.py b/tb/ptp_clock/test_ptp_clock.py
index 988aea37..1166d182 100644
--- a/tb/ptp_clock/test_ptp_clock.py
+++ b/tb/ptp_clock/test_ptp_clock.py
@@ -138,6 +138,8 @@ async def run_load_timestamps(dut):
assert dut.output_ts_64.value.integer == 12345678
assert dut.output_ts_step.value.integer == 1
+ await RisingEdge(dut.clk)
+
start_time = get_sim_time('sec')
start_ts_96 = (dut.output_ts_96.value.integer >> 48) + ((dut.output_ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
start_ts_64 = dut.output_ts_64.value.integer/2**16*1e-9
@@ -188,6 +190,7 @@ async def run_seconds_increment(dut):
dut.input_ts_96_valid.value = 0
dut.input_ts_64_valid.value = 0
+ await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
start_time = get_sim_time('sec')
--
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