From 073d50d9dc0423c495db15d238e1933dcc9caa80 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 30 Mar 2022 16:02:17 -0700
Subject: [PATCH] Round up default KEEP_WIDTH settings when DATA_WIDTH is not a
multiple of 8
---
README.md | 2 +-
rtl/axis_adapter.v | 4 ++--
rtl/axis_arb_mux.v | 2 +-
rtl/axis_arb_mux_wrap.py | 2 +-
rtl/axis_async_fifo.v | 2 +-
rtl/axis_async_fifo_adapter.v | 4 ++--
rtl/axis_broadcast.v | 2 +-
rtl/axis_broadcast_wrap.py | 2 +-
rtl/axis_crosspoint.v | 2 +-
rtl/axis_crosspoint_wrap.py | 2 +-
rtl/axis_demux.v | 2 +-
rtl/axis_demux_wrap.py | 2 +-
rtl/axis_fifo.v | 2 +-
rtl/axis_fifo_adapter.v | 4 ++--
rtl/axis_frame_len.v | 2 +-
rtl/axis_frame_length_adjust.v | 2 +-
rtl/axis_frame_length_adjust_fifo.v | 2 +-
rtl/axis_mux.v | 2 +-
rtl/axis_mux_wrap.py | 2 +-
rtl/axis_pipeline_fifo.v | 2 +-
rtl/axis_pipeline_register.v | 2 +-
rtl/axis_ram_switch.v | 4 ++--
rtl/axis_ram_switch_wrap.py | 4 ++--
rtl/axis_rate_limit.v | 2 +-
rtl/axis_register.v | 2 +-
rtl/axis_srl_fifo.v | 2 +-
rtl/axis_srl_register.v | 2 +-
rtl/axis_stat_counter.v | 2 +-
rtl/axis_switch.v | 2 +-
rtl/axis_switch_wrap.py | 2 +-
rtl/axis_tap.v | 2 +-
tb/axis_adapter/Makefile | 4 ++--
tb/axis_adapter/test_axis_adapter.py | 4 ++--
tb/axis_arb_mux/Makefile | 2 +-
tb/axis_arb_mux/test_axis_arb_mux.py | 2 +-
tb/axis_async_fifo/Makefile | 2 +-
tb/axis_async_fifo/test_axis_async_fifo.py | 2 +-
tb/axis_async_fifo_adapter/Makefile | 4 ++--
tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py | 4 ++--
tb/axis_broadcast/Makefile | 2 +-
tb/axis_broadcast/test_axis_broadcast.py | 2 +-
tb/axis_demux/Makefile | 2 +-
tb/axis_demux/test_axis_demux.py | 2 +-
tb/axis_fifo/Makefile | 2 +-
tb/axis_fifo/test_axis_fifo.py | 2 +-
tb/axis_fifo_adapter/Makefile | 4 ++--
tb/axis_fifo_adapter/test_axis_fifo_adapter.py | 4 ++--
tb/axis_frame_length_adjust/Makefile | 2 +-
tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py | 2 +-
tb/axis_frame_length_adjust_fifo/Makefile | 2 +-
.../test_axis_frame_length_adjust_fifo.py | 2 +-
tb/axis_mux/Makefile | 2 +-
tb/axis_mux/test_axis_mux.py | 2 +-
tb/axis_pipeline_fifo/Makefile | 2 +-
tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py | 2 +-
tb/axis_pipeline_register/Makefile | 2 +-
tb/axis_pipeline_register/test_axis_pipeline_register.py | 2 +-
tb/axis_ram_switch/Makefile | 4 ++--
tb/axis_ram_switch/test_axis_ram_switch.py | 4 ++--
tb/axis_rate_limit/Makefile | 2 +-
tb/axis_rate_limit/test_axis_rate_limit.py | 2 +-
tb/axis_register/Makefile | 2 +-
tb/axis_register/test_axis_register.py | 2 +-
tb/axis_srl_fifo/Makefile | 2 +-
tb/axis_srl_fifo/test_axis_srl_fifo.py | 2 +-
tb/axis_srl_register/Makefile | 2 +-
tb/axis_srl_register/test_axis_srl_register.py | 2 +-
tb/axis_switch/Makefile | 2 +-
tb/axis_switch/test_axis_switch.py | 2 +-
69 files changed, 82 insertions(+), 82 deletions(-)
diff --git a/README.md b/README.md
index 8ea4b149..397ca505 100644
--- a/README.md
+++ b/README.md
@@ -205,7 +205,7 @@ Parametrizable priority encoder.
DATA_WIDTH : width of tdata signal
KEEP_ENABLE : enable tkeep signal (default DATA_WIDTH>8)
- KEEP_WIDTH : width of tkeep signal (default DATA_WIDTH/8)
+ KEEP_WIDTH : width of tkeep signal (default (DATA_WIDTH+7)/8)
LAST_ENABLE : enable tlast signal
ID_ENABLE : enable tid signal
ID_WIDTH : width of tid signal
diff --git a/rtl/axis_adapter.v b/rtl/axis_adapter.v
index cb332510..51aa226a 100644
--- a/rtl/axis_adapter.v
+++ b/rtl/axis_adapter.v
@@ -39,14 +39,14 @@ module axis_adapter #
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/rtl/axis_arb_mux.v b/rtl/axis_arb_mux.v
index 83bdd4f6..43a588f4 100644
--- a/rtl/axis_arb_mux.v
+++ b/rtl/axis_arb_mux.v
@@ -40,7 +40,7 @@ module axis_arb_mux #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/rtl/axis_arb_mux_wrap.py b/rtl/axis_arb_mux_wrap.py
index 091d3661..076d8a1a 100755
--- a/rtl/axis_arb_mux_wrap.py
+++ b/rtl/axis_arb_mux_wrap.py
@@ -75,7 +75,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/rtl/axis_async_fifo.v b/rtl/axis_async_fifo.v
index 2d89f2da..4f1e3601 100644
--- a/rtl/axis_async_fifo.v
+++ b/rtl/axis_async_fifo.v
@@ -43,7 +43,7 @@ module axis_async_fifo #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_async_fifo_adapter.v b/rtl/axis_async_fifo_adapter.v
index 76a293a6..848fcf50 100644
--- a/rtl/axis_async_fifo_adapter.v
+++ b/rtl/axis_async_fifo_adapter.v
@@ -43,14 +43,14 @@ module axis_async_fifo_adapter #
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/rtl/axis_broadcast.v b/rtl/axis_broadcast.v
index 16137ea7..34fafd26 100644
--- a/rtl/axis_broadcast.v
+++ b/rtl/axis_broadcast.v
@@ -40,7 +40,7 @@ module axis_broadcast #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_broadcast_wrap.py b/rtl/axis_broadcast_wrap.py
index e755a20e..acd31571 100755
--- a/rtl/axis_broadcast_wrap.py
+++ b/rtl/axis_broadcast_wrap.py
@@ -75,7 +75,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_crosspoint.v b/rtl/axis_crosspoint.v
index c6574d26..7fde4ab4 100644
--- a/rtl/axis_crosspoint.v
+++ b/rtl/axis_crosspoint.v
@@ -42,7 +42,7 @@ module axis_crosspoint #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_crosspoint_wrap.py b/rtl/axis_crosspoint_wrap.py
index f7396532..0646ec8a 100755
--- a/rtl/axis_crosspoint_wrap.py
+++ b/rtl/axis_crosspoint_wrap.py
@@ -81,7 +81,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_demux.v b/rtl/axis_demux.v
index 796799e5..7edd757f 100644
--- a/rtl/axis_demux.v
+++ b/rtl/axis_demux.v
@@ -40,7 +40,7 @@ module axis_demux #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/rtl/axis_demux_wrap.py b/rtl/axis_demux_wrap.py
index 344c8bcb..bc731176 100755
--- a/rtl/axis_demux_wrap.py
+++ b/rtl/axis_demux_wrap.py
@@ -75,7 +75,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/rtl/axis_fifo.v b/rtl/axis_fifo.v
index bf3be6e1..c9314746 100644
--- a/rtl/axis_fifo.v
+++ b/rtl/axis_fifo.v
@@ -43,7 +43,7 @@ module axis_fifo #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_fifo_adapter.v b/rtl/axis_fifo_adapter.v
index 7b43b007..095d6ce7 100644
--- a/rtl/axis_fifo_adapter.v
+++ b/rtl/axis_fifo_adapter.v
@@ -43,14 +43,14 @@ module axis_fifo_adapter #
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/rtl/axis_frame_len.v b/rtl/axis_frame_len.v
index a1f75e5d..49ce097a 100644
--- a/rtl/axis_frame_len.v
+++ b/rtl/axis_frame_len.v
@@ -39,7 +39,7 @@ module axis_frame_len #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Width of length counter
parameter LEN_WIDTH = 16
)
diff --git a/rtl/axis_frame_length_adjust.v b/rtl/axis_frame_length_adjust.v
index 42550ad0..92fb2ec1 100644
--- a/rtl/axis_frame_length_adjust.v
+++ b/rtl/axis_frame_length_adjust.v
@@ -39,7 +39,7 @@ module axis_frame_length_adjust #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/rtl/axis_frame_length_adjust_fifo.v b/rtl/axis_frame_length_adjust_fifo.v
index a580cee9..f2bc4a06 100644
--- a/rtl/axis_frame_length_adjust_fifo.v
+++ b/rtl/axis_frame_length_adjust_fifo.v
@@ -39,7 +39,7 @@ module axis_frame_length_adjust_fifo #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/rtl/axis_mux.v b/rtl/axis_mux.v
index ba97d939..ab021d3e 100644
--- a/rtl/axis_mux.v
+++ b/rtl/axis_mux.v
@@ -40,7 +40,7 @@ module axis_mux #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/rtl/axis_mux_wrap.py b/rtl/axis_mux_wrap.py
index bc1b8325..00698cd0 100755
--- a/rtl/axis_mux_wrap.py
+++ b/rtl/axis_mux_wrap.py
@@ -75,7 +75,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/rtl/axis_pipeline_fifo.v b/rtl/axis_pipeline_fifo.v
index 0da81457..4c194bf7 100644
--- a/rtl/axis_pipeline_fifo.v
+++ b/rtl/axis_pipeline_fifo.v
@@ -38,7 +38,7 @@ module axis_pipeline_fifo #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_pipeline_register.v b/rtl/axis_pipeline_register.v
index 1e22ffcc..9715dca4 100644
--- a/rtl/axis_pipeline_register.v
+++ b/rtl/axis_pipeline_register.v
@@ -38,7 +38,7 @@ module axis_pipeline_register #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_ram_switch.v b/rtl/axis_ram_switch.v
index ed831fe2..ac31dcca 100644
--- a/rtl/axis_ram_switch.v
+++ b/rtl/axis_ram_switch.v
@@ -52,13 +52,13 @@ module axis_ram_switch #
// Propagate tkeep signal
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interfaces in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/rtl/axis_ram_switch_wrap.py b/rtl/axis_ram_switch_wrap.py
index 45adfed5..1dbd223a 100755
--- a/rtl/axis_ram_switch_wrap.py
+++ b/rtl/axis_ram_switch_wrap.py
@@ -91,13 +91,13 @@ module {{name}} #
// Propagate tkeep signal
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+ parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interfaces in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+ parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/rtl/axis_rate_limit.v b/rtl/axis_rate_limit.v
index 3f91b4cb..24ec9546 100644
--- a/rtl/axis_rate_limit.v
+++ b/rtl/axis_rate_limit.v
@@ -39,7 +39,7 @@ module axis_rate_limit #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_register.v b/rtl/axis_register.v
index fbd245c1..7e8f1093 100644
--- a/rtl/axis_register.v
+++ b/rtl/axis_register.v
@@ -38,7 +38,7 @@ module axis_register #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_srl_fifo.v b/rtl/axis_srl_fifo.v
index e0cc4164..7eabf8f4 100644
--- a/rtl/axis_srl_fifo.v
+++ b/rtl/axis_srl_fifo.v
@@ -38,7 +38,7 @@ module axis_srl_fifo #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_srl_register.v b/rtl/axis_srl_register.v
index 4bfaeaaf..f0e9efee 100644
--- a/rtl/axis_srl_register.v
+++ b/rtl/axis_srl_register.v
@@ -38,7 +38,7 @@ module axis_srl_register #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
diff --git a/rtl/axis_stat_counter.v b/rtl/axis_stat_counter.v
index c59c441b..cc047608 100644
--- a/rtl/axis_stat_counter.v
+++ b/rtl/axis_stat_counter.v
@@ -39,7 +39,7 @@ module axis_stat_counter #
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Prepend data with tag
parameter TAG_ENABLE = 1,
// Tag field width
diff --git a/rtl/axis_switch.v b/rtl/axis_switch.v
index c949b700..d791294b 100644
--- a/rtl/axis_switch.v
+++ b/rtl/axis_switch.v
@@ -42,7 +42,7 @@ module axis_switch #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/rtl/axis_switch_wrap.py b/rtl/axis_switch_wrap.py
index 0af37e02..e3e13dc3 100755
--- a/rtl/axis_switch_wrap.py
+++ b/rtl/axis_switch_wrap.py
@@ -81,7 +81,7 @@ module {{name}} #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
diff --git a/rtl/axis_tap.v b/rtl/axis_tap.v
index a9c7e19e..13966adc 100644
--- a/rtl/axis_tap.v
+++ b/rtl/axis_tap.v
@@ -38,7 +38,7 @@ module axis_tap #
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
- parameter KEEP_WIDTH = (DATA_WIDTH/8),
+ parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
diff --git a/tb/axis_adapter/Makefile b/tb/axis_adapter/Makefile
index af559301..621657d7 100644
--- a/tb/axis_adapter/Makefile
+++ b/tb/axis_adapter/Makefile
@@ -34,10 +34,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_adapter/test_axis_adapter.py b/tb/axis_adapter/test_axis_adapter.py
index addc7274..5997d61e 100644
--- a/tb/axis_adapter/test_axis_adapter.py
+++ b/tb/axis_adapter/test_axis_adapter.py
@@ -227,10 +227,10 @@ def test_axis_register(request, s_data_width, m_data_width):
parameters['S_DATA_WIDTH'] = s_data_width
parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
- parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+ parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
parameters['M_DATA_WIDTH'] = m_data_width
parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
- parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+ parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/tb/axis_arb_mux/Makefile b/tb/axis_arb_mux/Makefile
index 962af950..936f22b1 100644
--- a/tb/axis_arb_mux/Makefile
+++ b/tb/axis_arb_mux/Makefile
@@ -40,7 +40,7 @@ VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 8
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())")
diff --git a/tb/axis_arb_mux/test_axis_arb_mux.py b/tb/axis_arb_mux/test_axis_arb_mux.py
index ec23a41c..187964b3 100644
--- a/tb/axis_arb_mux/test_axis_arb_mux.py
+++ b/tb/axis_arb_mux/test_axis_arb_mux.py
@@ -344,7 +344,7 @@ def test_axis_arb_mux(request, ports, data_width, round_robin):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['S_ID_WIDTH'] = 8
parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (ports-1).bit_length()
diff --git a/tb/axis_async_fifo/Makefile b/tb/axis_async_fifo/Makefile
index 75efe994..f301f8b4 100644
--- a/tb/axis_async_fifo/Makefile
+++ b/tb/axis_async_fifo/Makefile
@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_async_fifo/test_axis_async_fifo.py b/tb/axis_async_fifo/test_axis_async_fifo.py
index 223a7e36..fb3026d8 100644
--- a/tb/axis_async_fifo/test_axis_async_fifo.py
+++ b/tb/axis_async_fifo/test_axis_async_fifo.py
@@ -539,7 +539,7 @@ def test_axis_async_fifo(request, data_width, frame_fifo, drop_oversize_frame, d
parameters['DEPTH'] = 1024
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/tb/axis_async_fifo_adapter/Makefile b/tb/axis_async_fifo_adapter/Makefile
index 1471541e..c193ebb0 100644
--- a/tb/axis_async_fifo_adapter/Makefile
+++ b/tb/axis_async_fifo_adapter/Makefile
@@ -37,10 +37,10 @@ VERILOG_SOURCES += ../../rtl/axis_adapter.v
export PARAM_DEPTH ?= 1024
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py b/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py
index 6ff2ac88..bae15ef0 100644
--- a/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py
+++ b/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py
@@ -536,10 +536,10 @@ def test_axis_async_fifo_adapter(request, s_data_width, m_data_width, frame_fifo
parameters['DEPTH'] = 1024
parameters['S_DATA_WIDTH'] = s_data_width
parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
- parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+ parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
parameters['M_DATA_WIDTH'] = m_data_width
parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
- parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+ parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/tb/axis_broadcast/Makefile b/tb/axis_broadcast/Makefile
index 8bd2282a..7b66215c 100644
--- a/tb/axis_broadcast/Makefile
+++ b/tb/axis_broadcast/Makefile
@@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_broadcast/test_axis_broadcast.py b/tb/axis_broadcast/test_axis_broadcast.py
index 8bc7ac9a..caca5188 100644
--- a/tb/axis_broadcast/test_axis_broadcast.py
+++ b/tb/axis_broadcast/test_axis_broadcast.py
@@ -170,7 +170,7 @@ def test_axis_broadcast(request, ports, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/tb/axis_demux/Makefile b/tb/axis_demux/Makefile
index 6fd45472..8822019d 100644
--- a/tb/axis_demux/Makefile
+++ b/tb/axis_demux/Makefile
@@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/tb/axis_demux/test_axis_demux.py b/tb/axis_demux/test_axis_demux.py
index 832b0211..bce6b471 100644
--- a/tb/axis_demux/test_axis_demux.py
+++ b/tb/axis_demux/test_axis_demux.py
@@ -186,7 +186,7 @@ def test_axis_demux(request, ports, data_width, tdest_route):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/tb/axis_fifo/Makefile b/tb/axis_fifo/Makefile
index 9073da6c..fabad14d 100644
--- a/tb/axis_fifo/Makefile
+++ b/tb/axis_fifo/Makefile
@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_fifo/test_axis_fifo.py b/tb/axis_fifo/test_axis_fifo.py
index 61b5351d..db13ca87 100644
--- a/tb/axis_fifo/test_axis_fifo.py
+++ b/tb/axis_fifo/test_axis_fifo.py
@@ -329,7 +329,7 @@ def test_axis_fifo(request, data_width, frame_fifo, drop_oversize_frame, drop_ba
parameters['DEPTH'] = 1024
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/tb/axis_fifo_adapter/Makefile b/tb/axis_fifo_adapter/Makefile
index 786c51c5..86e3f2f3 100644
--- a/tb/axis_fifo_adapter/Makefile
+++ b/tb/axis_fifo_adapter/Makefile
@@ -37,10 +37,10 @@ VERILOG_SOURCES += ../../rtl/axis_adapter.v
export PARAM_DEPTH ?= 1024
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_fifo_adapter/test_axis_fifo_adapter.py b/tb/axis_fifo_adapter/test_axis_fifo_adapter.py
index 6ff21ca9..bc3fc76e 100644
--- a/tb/axis_fifo_adapter/test_axis_fifo_adapter.py
+++ b/tb/axis_fifo_adapter/test_axis_fifo_adapter.py
@@ -332,10 +332,10 @@ def test_axis_fifo_adapter(request, s_data_width, m_data_width, frame_fifo, drop
parameters['DEPTH'] = 1024
parameters['S_DATA_WIDTH'] = s_data_width
parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
- parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+ parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
parameters['M_DATA_WIDTH'] = m_data_width
parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
- parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+ parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/tb/axis_frame_length_adjust/Makefile b/tb/axis_frame_length_adjust/Makefile
index 0cec922d..abe6052c 100644
--- a/tb/axis_frame_length_adjust/Makefile
+++ b/tb/axis_frame_length_adjust/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py b/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py
index 5817f5c0..260c9fe5 100644
--- a/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py
+++ b/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py
@@ -214,7 +214,7 @@ def test_axis_frame_length_adjust(request, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/tb/axis_frame_length_adjust_fifo/Makefile b/tb/axis_frame_length_adjust_fifo/Makefile
index ed886c2a..59b5d822 100644
--- a/tb/axis_frame_length_adjust_fifo/Makefile
+++ b/tb/axis_frame_length_adjust_fifo/Makefile
@@ -36,7 +36,7 @@ VERILOG_SOURCES += ../../rtl/axis_fifo.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py b/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py
index b3403cd0..0ad01cf8 100644
--- a/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py
+++ b/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py
@@ -306,7 +306,7 @@ def test_axis_frame_length_adjust_fifo(request, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/tb/axis_mux/Makefile b/tb/axis_mux/Makefile
index 5323a4d3..247a0784 100644
--- a/tb/axis_mux/Makefile
+++ b/tb/axis_mux/Makefile
@@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/tb/axis_mux/test_axis_mux.py b/tb/axis_mux/test_axis_mux.py
index 217b03ce..d722acf1 100644
--- a/tb/axis_mux/test_axis_mux.py
+++ b/tb/axis_mux/test_axis_mux.py
@@ -206,7 +206,7 @@ def test_axis_mux(request, ports, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
parameters['DEST_ENABLE'] = 1
diff --git a/tb/axis_pipeline_fifo/Makefile b/tb/axis_pipeline_fifo/Makefile
index cfb36c0b..a356a55e 100644
--- a/tb/axis_pipeline_fifo/Makefile
+++ b/tb/axis_pipeline_fifo/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py b/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py
index 830b0337..57559857 100644
--- a/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py
+++ b/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py
@@ -317,7 +317,7 @@ def test_axis_pipeline_fifo(request, length, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/tb/axis_pipeline_register/Makefile b/tb/axis_pipeline_register/Makefile
index b635f728..13e6e6cf 100644
--- a/tb/axis_pipeline_register/Makefile
+++ b/tb/axis_pipeline_register/Makefile
@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/axis_register.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_pipeline_register/test_axis_pipeline_register.py b/tb/axis_pipeline_register/test_axis_pipeline_register.py
index a971e8e1..2ea13bf5 100644
--- a/tb/axis_pipeline_register/test_axis_pipeline_register.py
+++ b/tb/axis_pipeline_register/test_axis_pipeline_register.py
@@ -229,7 +229,7 @@ def test_axis_pipeline_register(request, length, data_width, reg_type):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/tb/axis_ram_switch/Makefile b/tb/axis_ram_switch/Makefile
index adfea859..6b07dabe 100644
--- a/tb/axis_ram_switch/Makefile
+++ b/tb/axis_ram_switch/Makefile
@@ -45,10 +45,10 @@ export PARAM_CMD_FIFO_DEPTH ?= 32
export PARAM_SPEEDUP ?= 0
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 16
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
diff --git a/tb/axis_ram_switch/test_axis_ram_switch.py b/tb/axis_ram_switch/test_axis_ram_switch.py
index 422fcd84..6bc3fd1e 100644
--- a/tb/axis_ram_switch/test_axis_ram_switch.py
+++ b/tb/axis_ram_switch/test_axis_ram_switch.py
@@ -356,10 +356,10 @@ def test_axis_ram_switch(request, s_count, m_count, s_data_width, m_data_width):
parameters['SPEEDUP'] = 0
parameters['S_DATA_WIDTH'] = s_data_width
parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
- parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+ parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
parameters['M_DATA_WIDTH'] = m_data_width
parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
- parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+ parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['S_ID_WIDTH'] = 16
parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length()
diff --git a/tb/axis_rate_limit/Makefile b/tb/axis_rate_limit/Makefile
index 4da3e0bb..002d611c 100644
--- a/tb/axis_rate_limit/Makefile
+++ b/tb/axis_rate_limit/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_rate_limit/test_axis_rate_limit.py b/tb/axis_rate_limit/test_axis_rate_limit.py
index 170419df..f54828e7 100644
--- a/tb/axis_rate_limit/test_axis_rate_limit.py
+++ b/tb/axis_rate_limit/test_axis_rate_limit.py
@@ -187,7 +187,7 @@ def test_axis_rate_limit(request, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/tb/axis_register/Makefile b/tb/axis_register/Makefile
index 20747961..0a2e2e9d 100644
--- a/tb/axis_register/Makefile
+++ b/tb/axis_register/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_register/test_axis_register.py b/tb/axis_register/test_axis_register.py
index bd9e3e79..55e4c786 100644
--- a/tb/axis_register/test_axis_register.py
+++ b/tb/axis_register/test_axis_register.py
@@ -227,7 +227,7 @@ def test_axis_register(request, data_width, reg_type):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/tb/axis_srl_fifo/Makefile b/tb/axis_srl_fifo/Makefile
index 35b77686..43b43716 100644
--- a/tb/axis_srl_fifo/Makefile
+++ b/tb/axis_srl_fifo/Makefile
@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
diff --git a/tb/axis_srl_fifo/test_axis_srl_fifo.py b/tb/axis_srl_fifo/test_axis_srl_fifo.py
index e18fd8a8..0e7281a8 100644
--- a/tb/axis_srl_fifo/test_axis_srl_fifo.py
+++ b/tb/axis_srl_fifo/test_axis_srl_fifo.py
@@ -317,7 +317,7 @@ def test_axis_srl_fifo(request, data_width):
parameters['DEPTH'] = 1024
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/tb/axis_srl_register/Makefile b/tb/axis_srl_register/Makefile
index d1842025..d7c66b76 100644
--- a/tb/axis_srl_register/Makefile
+++ b/tb/axis_srl_register/Makefile
@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
diff --git a/tb/axis_srl_register/test_axis_srl_register.py b/tb/axis_srl_register/test_axis_srl_register.py
index 4dd1c0c3..7be3ad87 100644
--- a/tb/axis_srl_register/test_axis_srl_register.py
+++ b/tb/axis_srl_register/test_axis_srl_register.py
@@ -226,7 +226,7 @@ def test_axis_srl_register(request, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['LAST_ENABLE'] = 1
parameters['ID_ENABLE'] = 1
parameters['ID_WIDTH'] = 8
diff --git a/tb/axis_switch/Makefile b/tb/axis_switch/Makefile
index 9cf55599..a59fb3db 100644
--- a/tb/axis_switch/Makefile
+++ b/tb/axis_switch/Makefile
@@ -42,7 +42,7 @@ VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 16
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
diff --git a/tb/axis_switch/test_axis_switch.py b/tb/axis_switch/test_axis_switch.py
index 9e250e33..c2da5a08 100644
--- a/tb/axis_switch/test_axis_switch.py
+++ b/tb/axis_switch/test_axis_switch.py
@@ -351,7 +351,7 @@ def test_axis_switch(request, s_count, m_count, data_width):
parameters['DATA_WIDTH'] = data_width
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
- parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+ parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
parameters['ID_ENABLE'] = 1
parameters['S_ID_WIDTH'] = 16
parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length()
--
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