module audio_test_top (
	input logic CLOCK_50,
	input logic [1:0] KEY,
	output logic [7:0] LEDG,
	output logic [17:0] LEDR,
	//output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
	output logic [12:0] DRAM_ADDR,
	output logic [1:0] DRAM_BA,
	output logic DRAM_CAS_N, DRAM_CKE, DRAM_CS_N,
	inout wire [31:0] DRAM_DQ,
	output logic [3:0] DRAM_DQM,
	output logic DRAM_RAS_N, DRAM_WE_N, DRAM_CLK,
	output logic AUD_XCK,                   			
				 AUD_DACDAT,           
				        
				 I2C_SCLK,

	input logic  AUD_ADCDAT,
				 

	inout wire AUD_BCLK,
				AUD_ADCLRCK,
				AUD_DACLRCK,
				I2C_SDAT,
	//output wire[2:0] LEDG
	
	//output wire [15:0] LEDR
	
	//sd card
	inout wire [3:0]SD_DAT,
	inout wire	SD_CMD,
					
	output wire SD_CLK,
	input wire SD_WP_N
);
	otogame main_soc (
		.clk_clk(CLOCK_50),
		.reset_reset_n(KEY[0]),
		.sdram_wire_addr(DRAM_ADDR),
		.sdram_wire_ba(DRAM_BA),
		.sdram_wire_cas_n(DRAM_CAS_N),
		.sdram_wire_cke(DRAM_CKE),
		.sdram_wire_cs_n(DRAM_CS_N),
		.sdram_wire_dq(DRAM_DQ),
		.sdram_wire_dqm(DRAM_DQM),
		.sdram_wire_ras_n(DRAM_RAS_N),
		.sdram_wire_we_n(DRAM_WE_N),
		.sdram_clk_clk(DRAM_CLK),
		.audio_clk_clk(AUD_XCK),       //      audio.mclk
		.audio_bclk(AUD_BCLK),       //           .bclk
		.audio_adc_data( AUD_ADCDAT),   //           .adc_data
		.audio_dac_data(AUD_DACDAT),   //           .dac_data
		.audio_dac_clk(AUD_DACLRCK),    //           .dac_clk
		.audio_adc_clk(AUD_ADCLRCK),    //           .adc_clk
		.audio_i2c_sdat(I2C_SDAT),   //           .i2c_sdat
		.audio_i2c_sclk(I2C_SCLK),
		//.audio_ledr(LEDR[15:0]),
		//.SW(SW)
//		.sd_export_b_SD_cmd(SD_CMD),   //  sd_export.b_SD_cmd
//		.sd_export_b_SD_dat(SD_DAT0),   //           .b_SD_dat
//		.sd_export_b_SD_dat3(SD_DAT3),  //           .b_SD_dat3
//		.sd_export_o_SD_clock(SD_CLK)
		.sd_interface_sd_clk(SD_CLK),    //     sd_clk.export
		.sd_interface_sd_cmd(SD_CMD),    //     sd_cmd.export
		.sd_interface_sd_dat(SD_DAT),    //     sd_dat.export
		//.sd_wp_n_export(),
		.sd_interface_led_green(LEDG),
		.sd_interface_led_red(LEDR[15:0])
	);
	
endmodule