/**
 *	gl_avalon_intf
 *
 *	Avalon-MM interface for GL modules
 *
 */

module gl_avalon_intf (
	// Avalon Clock Input
	input logic CLK, RESET,

	// GL Controller Slave
	input  logic AVL_S_READ,
	input  logic AVL_S_WRITE,
	input  logic AVL_S_CS,
	input  logic [3:0] AVL_S_BYTE_EN,
	input  logic [1:0] AVL_S_ADDR,
	input  logic [31:0] AVL_S_WRITEDATA,
	output logic [31:0] AVL_S_READDATA,

	// SRAM Conduit
	output logic [19:0] SRAM_ADDR,
	inout wire [15:0] SRAM_DQ,
	output logic SRAM_UB_N, SRAM_LB_N, SRAM_CE_N, SRAM_OE_N, SRAM_WE_N,

	// VGA Conduit
	output logic VGA_CLK,
	output logic [7:0] VGA_R, VGA_G, VGA_B,
	output logic VGA_SYNC_N, VGA_BLANK_N, VGA_VS, VGA_HS
);



endmodule