From fcaf4db88b22c1387fa1e12c49e3824c96e06203 Mon Sep 17 00:00:00 2001
From: Jumbo <nomandjiang@gmail.com>
Date: Mon, 4 Dec 2017 04:28:11 -0600
Subject: [PATCH] buffered audio complete

---
 audio.sv                                      | 146 ++++++++++++++----
 audio_hw.tcl                                  |   4 +-
 final_sd_interface.sv                         |   6 +
 final_sd_interface_hw.tcl                     |   4 +-
 osu_fpga_toplevel.qsf                         | 112 +++++++++++++-
 otogame.qsys                                  |  75 +++++++--
 software/audio_sd_other/main.c                |  46 +++---
 .../terasic_fat/FatFileSystem.c               |   2 +-
 .../audio_sd_other/terasic_sdcard/sd_hal.c    |  84 ++++++----
 9 files changed, 381 insertions(+), 98 deletions(-)

diff --git a/audio.sv b/audio.sv
index e12b439..4fae75d 100644
--- a/audio.sv
+++ b/audio.sv
@@ -6,6 +6,8 @@ module audio(
 	input logic AVL_RD,AVL_WR,
 	input logic [31:0] AVL_WDATA,
 	output logic [31:0] AVL_RDATA,
+	
+	output logic [6:0] LEDG,
 
 	output logic //AUD_MCLK,                   			
 				 AUD_DACDAT,           
@@ -23,9 +25,11 @@ module audio(
 	//output logic [15:0] LEDR
 );
 
+assign LEDG= {3'b0,available,state};
+
 logic should_give,should_give_next;
 
-logic [7:0]counter,counter_next;
+logic [7:0]counter,counter_next/*synthesis keep*/;
 
 logic audio_out_allowed,write_audio_out,write_audio_out_next;
 
@@ -33,37 +37,53 @@ logic [4:0] data,data_next;
 
 logic vol_set,vol_set_next;
 
-logic state,state_next;
+logic [1:0] state,state_next;
+
+//logic c_reset/*synthesis keep*/;
+
+logic buff_select,buff_select_next;
+
+logic available,available_next;
 
-logic c_reset;
+//logic write_complete,write_complete_next;
 
-logic MEM_WE;
+logic MEM_WE[2];
 
-logic[31:0] MEM_DATAIN,MEM_DATAOUT /*synthesis keep*/;
+logic[31:0] MEM_DATAIN;
+logic [31:0] MEM_DATAOUT[0:1];
 logic[7:0] MEM_ADDR;
+
+logic [31:0] audio_data_in /*synthesis keep*/;
+
 //logic audio_ready,audio_ready_next;
 
 //logic audio_out_allowed;
 //assign LEDR = data[0][31:16];
 
-always_ff @(negedge CLK) begin
+always_ff @(posedge CLK) begin
 	if(RESET) begin
 		data <= 32'h0;
 		//data[1] <= 32'h0;
 		//write_audio_out <= 1'b0;
 		vol_set <= 1'b0;
-		state <=1'b1;
+		state <=2'b11;
+		buff_select <= 1'b0;
+		available <= 1'b0;
+		//write_complete <= 1'b0;
 	end else begin
 		data <= data_next;
 		//data[1] <= data_next[1];
 		//write_audio_out <= write_audio_out_next;
 		vol_set <= vol_set_next;
 		state <= state_next;
+		buff_select <= buff_select_next;
+		available <= available_next;
+		//write_complete <= write_complete_next;
 	end
 end
 
 always_ff @(posedge CLK) begin
-	if(c_reset) begin
+	if(RESET) begin
 		counter <= 0;
 	end else begin
 		counter <= counter_next;
@@ -71,27 +91,33 @@ always_ff @(posedge CLK) begin
 end
 
 always_comb begin
+
 	//audio_ready_next = audio_ready;
 	data_next = data;
 	//data_next[1] = data[1];
 	//INIT = 1'b0;
-	c_reset = 0;
+	//c_reset = 0;
 	counter_next = counter;
 	AVL_RDATA = 32'hCCCC;
 	write_audio_out=0;
 	vol_set_next = 0;
 	
+	available_next = available;
+	buff_select_next = buff_select;
 	state_next = state;
 
-	MEM_WE = 1'b0;
+	MEM_WE[0] = 1'b0;
+	MEM_WE[1] = 1'b0;
 	MEM_ADDR = 8'hCC;
-	MEM_DATAIN = 20'b00000000000000000000;
-	
+	MEM_DATAIN = 32'hCCCC;
+
+	audio_data_in = MEM_DATAOUT[!buff_select];
+
 	if (AVL_WR && AVL_CS) begin
 		if (!AVL_ADDR[8]) begin
-			MEM_ADDR = AVL_ADDR;
+			MEM_ADDR = AVL_ADDR[6:0];
 			MEM_DATAIN = AVL_WDATA;
-			MEM_WE = 1'b1;
+			MEM_WE[buff_select] = 1'b1;
 		end else begin
 			if (AVL_ADDR[1:0] == 2'b10) begin
 				data_next = AVL_WDATA;
@@ -104,7 +130,7 @@ always_comb begin
 
 	if (AVL_RD && AVL_CS) begin
 		if (AVL_ADDR[8] && (AVL_ADDR[1:0] == 2'b00))begin
-				AVL_RDATA = {31'b0,state};
+				AVL_RDATA = {31'b0,available};
 		end
 	end
 
@@ -113,36 +139,100 @@ always_comb begin
 //	end else
 //		audio_ready_next = 1'b0;
 	case (state)
-		0:begin
+		2'b00:begin
+			buff_select_next = 0;
+			//buffer 0 for read
+			//buffer 1 for audio data
+				
 			if (audio_out_allowed) begin
 				counter_next = counter + 1;
+				write_audio_out = 1;
+
 				if (counter == 8'b01111111) begin
-					write_audio_out = 1;
-					state_next = 1;
-					c_reset = 1;
+					if (!available) begin
+						state_next = 2'b01;
+						counter_next = 8'b0;
+						available_next = 1;
+						buff_select_next = 1;
+						//write_complete_next = 0;
+					end else begin
+						audio_data_in = 32'h0;
+						counter_next = counter;
+					end
 				end
 			end
+			if (AVL_ADDR == 9'b001111111 && (AVL_WR)) begin
+				available_next = 0;
+				//write_complete_next = 1;
+			end
+
 		end
-		1:begin
-			if (AVL_ADDR == 9'b001111111) begin
+		2'b01:begin
+			//reading in buffer 1 
+			//output audio in buffer 0
+			buff_select_next = 1;
+			if (audio_out_allowed) begin
+				counter_next = counter + 1;
+				write_audio_out = 1;
+				if (counter == 8'b01111111) begin
+					if (!available) begin
+						state_next = 2'b00;
+						counter_next = 8'b0;
+						available_next = 1;
+						buff_select_next = 0;
+						//write_complete_next = 0;
+					end else begin
+						audio_data_in = 32'h0;
+						counter_next = counter;
+					end
+				end
+			end
+			if ((AVL_ADDR == 9'b001111111) && (AVL_CS)) begin
+				available_next = 0;
+				//write_complete_next = 1;
+			end
+		end
+		2'b11:begin
+			//reading buffer 0
+			//output nothing
+			buff_select_next = 0;
+			available_next = 1'b1;
+			if ((AVL_ADDR == 9'b001111111)  && (AVL_CS)) begin
 				//c_reset = 1;
-				state_next = 0;
+				state_next = 2'b01;
+				//write_complete_next = 0;
+				buff_select_next = 1;
+				counter_next = 8'b0;
 			end
 		end
+
 	endcase
 end
 
 byte_enabled_simple_dual_port_ram #(
 		.ADDR_WIDTH(7),
 		.WIDTH(32)
-)MEM 
+)MEM0
+( 
+	.waddr(MEM_ADDR),
+	.raddr(counter[6:0]),
+	.wdata(MEM_DATAIN), 
+	.we(MEM_WE[0]),
+	.clk(CLK),
+	.q(MEM_DATAOUT[0])
+);
+
+byte_enabled_simple_dual_port_ram #(
+		.ADDR_WIDTH(7),
+		.WIDTH(32)
+)MEM1
 ( 
 	.waddr(MEM_ADDR),
-	.raddr(counter),
+	.raddr(counter[6:0]),
 	.wdata(MEM_DATAIN), 
-	.we(MEM_WE),
+	.we(MEM_WE[1]),
 	.clk(CLK),
-	.q(MEM_DATAOUT)
+	.q(MEM_DATAOUT[1])
 );
 
 Audio_Controller Audio_Controller (
@@ -154,8 +244,8 @@ Audio_Controller Audio_Controller (
 	.read_audio_in				(1'b0),
 	
 	.clear_audio_out_memory		(),
-	.left_channel_audio_out		({4'h0,MEM_DATAOUT[31:16],8'h0}),
-	.right_channel_audio_out	({4'h0,MEM_DATAOUT[15:0],8'h0}),
+	.left_channel_audio_out		({{8{audio_data_in[31]}},audio_data_in[31:16],8'h0}),
+	.right_channel_audio_out	({{8{audio_data_in[15]}},audio_data_in[15:0],8'h0}),
 	
 	//16'(signed'(IR[5:0]))
 	.write_audio_out			(write_audio_out),
diff --git a/audio_hw.tcl b/audio_hw.tcl
index daebb5d..7556aa0 100644
--- a/audio_hw.tcl
+++ b/audio_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 17.1
-# Wed Nov 29 09:57:36 CST 2017
+# Thu Nov 30 01:24:47 CST 2017
 # DO NOT MODIFY
 
 
 # 
 # audio "audio" v1.0
-#  2017.11.29.09:57:36
+#  2017.11.30.01:24:47
 # 
 # 
 
diff --git a/final_sd_interface.sv b/final_sd_interface.sv
index 8d270ed..c59cd86 100644
--- a/final_sd_interface.sv
+++ b/final_sd_interface.sv
@@ -205,6 +205,7 @@ always_comb begin
 					reg_48_next = {sd_cmd_message[0],sd_cmd_message[1],sd_cmd_message[2],
 								   sd_cmd_message[3],sd_cmd_message[4],sd_cmd_message[5]};
 					state_next = Send_cmd;
+					interface_status_next = 2'b00;
 				end
 				3'b010: begin
 					//receive cmd state
@@ -213,29 +214,34 @@ always_comb begin
 					//sd_cmd_rec_shift = 1;		
 
 					state_next = Receive_cmd;
+					interface_status_next = 2'b00;
 				end
 				3'b011: begin
 					//read data state
 					c_reset = 1;
 					sd_clk_tog = 1;
 					state_next = Read_data_0;
+					interface_status_next = 2'b00;
 				end
 				3'b100: begin
 					//toggle 8 SD_CLK 
 					c_reset = 1;
 					sd_clk_tog = 1;
 					state_next = Dummy_clk;
+					interface_status_next = 2'b00;
 				end
 				3'b101: begin
 					c_reset = 1;
 					sd_clk_tog = 1;
 					state_next = Dummy_clk2;
+					interface_status_next = 2'b00;
 				end
 				3'b110: begin
 					//probe read
 					c_reset = 1;
 					sd_clk_tog = 1;
 					state_next = Receive_cmd_probe_0;
+					interface_status_next = 2'b00;
 				end
 				default : state_next = Idle;
 			endcase
diff --git a/final_sd_interface_hw.tcl b/final_sd_interface_hw.tcl
index 295c657..08e36a6 100644
--- a/final_sd_interface_hw.tcl
+++ b/final_sd_interface_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 17.1
-# Fri Nov 24 20:46:05 CST 2017
+# Mon Dec 04 00:24:12 CST 2017
 # DO NOT MODIFY
 
 
 # 
 # final_sd_interface "final_sd_interface" v1.0
-#  2017.11.24.20:46:05
+#  2017.12.04.00:24:12
 # 
 # 
 
diff --git a/osu_fpga_toplevel.qsf b/osu_fpga_toplevel.qsf
index b4c6f6c..ce0b95e 100644
--- a/osu_fpga_toplevel.qsf
+++ b/osu_fpga_toplevel.qsf
@@ -677,6 +677,40 @@ set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
 set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to *
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to CLOCK_50 -section_id auto_signaltap_0
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/sd_interface_signal_tap.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/sd_interface_signal_tap.stp
 set_global_assignment -name SOURCE_FILE DE2_115.qsf
 set_global_assignment -name VERILOG_FILE avconf/I2C_Controller.v
 set_global_assignment -name VERILOG_FILE avconf/avconf.v
@@ -690,6 +724,78 @@ set_global_assignment -name VERILOG_FILE Audio_Controller/Altera_UP_Audio_Bit_Co
 set_global_assignment -name QIP_FILE otogame/synthesis/otogame.qip
 set_global_assignment -name SYSTEMVERILOG_FILE audio_test_top.sv
 set_global_assignment -name SYSTEMVERILOG_FILE audio.sv
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=8192" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=8192" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_CLK" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_CMD" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_CMD~direct" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_CLK" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_CMD" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_CMD~direct" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_DAT[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_DAT[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_DAT[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "otogame:main_soc|final_sd_interface:sd_interface|SD_DAT[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "otogame:main_soc|final_sd_interface:sd_interface|dataBuffer[0][9]" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=39" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=3" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=39" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=36" -section_id auto_signaltap_0
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SLD_FILE db/sd_interface_signal_tap_auto_stripped.stp
\ No newline at end of file
diff --git a/otogame.qsys b/otogame.qsys
index adcd17e..5cb6772 100644
--- a/otogame.qsys
+++ b/otogame.qsys
@@ -21,7 +21,7 @@
    {
       datum baseAddress
       {
-         value = "268439632";
+         value = "268439552";
          type = "String";
       }
    }
@@ -77,7 +77,7 @@
    {
       datum baseAddress
       {
-         value = "268439696";
+         value = "268442736";
          type = "String";
       }
    }
@@ -117,7 +117,7 @@
    {
       datum baseAddress
       {
-         value = "268439648";
+         value = "268442688";
          type = "String";
       }
    }
@@ -133,7 +133,7 @@
    {
       datum baseAddress
       {
-         value = "268439688";
+         value = "268442728";
          type = "String";
       }
    }
@@ -177,6 +177,22 @@
          type = "String";
       }
    }
+   element sd_interface
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element sd_interface.sd_slave
+   {
+      datum baseAddress
+      {
+         value = "268441600";
+         type = "String";
+      }
+   }
    element sdram
    {
       datum _sortIndex
@@ -205,7 +221,7 @@
    {
       datum baseAddress
       {
-         value = "268439664";
+         value = "268442704";
          type = "String";
       }
    }
@@ -226,7 +242,7 @@
    {
       datum baseAddress
       {
-         value = "268439552";
+         value = "268442624";
          type = "String";
       }
    }
@@ -264,6 +280,11 @@
  <interface name="ps2_data" internal="keyboard.ps2_data" />
  <interface name="ps2_data_conn" internal="keyboard.ps2_data_conn" />
  <interface name="reset" internal="clk_50.clk_in_reset" type="reset" dir="end" />
+ <interface
+   name="sd_interface"
+   internal="sd_interface.EXPORT"
+   type="conduit"
+   dir="end" />
  <interface name="sdram_clk" internal="sdram_pll.c1" type="clock" dir="start" />
  <interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
  <module name="audio_0" kind="audio" version="1.0" enabled="1" />
@@ -362,7 +383,7 @@
   <parameter name="cpuReset" value="false" />
   <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
   <parameter name="dataAddrWidth" value="29" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x8000000' end='0x10000000' /><slave name='proc_main.jtag_debug_module' start='0x10000800' end='0x10001000' /><slave name='timer.s1' start='0x10001000' end='0x10001020' /><slave name='audio_0.Audio_Slave' start='0x10001050' end='0x10001060' /><slave name='ocm_null.s1' start='0x10001060' end='0x10001070' /><slave name='sdram_pll.pll_slave' start='0x10001070' end='0x10001080' /><slave name='osu_sysid.control_slave' start='0x10001088' end='0x10001090' /><slave name='jtag_uart.avalon_jtag_slave' start='0x10001090' end='0x10001098' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x8000000' end='0x10000000' /><slave name='proc_main.jtag_debug_module' start='0x10000800' end='0x10001000' /><slave name='audio_0.Audio_Slave' start='0x10001000' end='0x10001800' /><slave name='sd_interface.sd_slave' start='0x10001800' end='0x10001C00' /><slave name='timer.s1' start='0x10001C00' end='0x10001C20' /><slave name='ocm_null.s1' start='0x10001C40' end='0x10001C50' /><slave name='sdram_pll.pll_slave' start='0x10001C50' end='0x10001C60' /><slave name='osu_sysid.control_slave' start='0x10001C68' end='0x10001C70' /><slave name='jtag_uart.avalon_jtag_slave' start='0x10001C70' end='0x10001C78' /></address-map>]]></parameter>
   <parameter name="dcache_bursts" value="false" />
   <parameter name="dcache_lineSize" value="32" />
   <parameter name="dcache_numTCDM" value="0" />
@@ -389,7 +410,7 @@
   <parameter name="icache_tagramBlockType" value="Automatic" />
   <parameter name="impl" value="Tiny" />
   <parameter name="instAddrWidth" value="29" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x8000000' end='0x10000000' /><slave name='proc_main.jtag_debug_module' start='0x10000800' end='0x10001000' /><slave name='ocm_null.s1' start='0x10001060' end='0x10001070' /><slave name='sdram_pll.pll_slave' start='0x10001070' end='0x10001080' /><slave name='osu_sysid.control_slave' start='0x10001088' end='0x10001090' /></address-map>]]></parameter>
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x8000000' end='0x10000000' /><slave name='proc_main.jtag_debug_module' start='0x10000800' end='0x10001000' /><slave name='ocm_null.s1' start='0x10001C40' end='0x10001C50' /><slave name='sdram_pll.pll_slave' start='0x10001C50' end='0x10001C60' /><slave name='osu_sysid.control_slave' start='0x10001C68' end='0x10001C70' /></address-map>]]></parameter>
   <parameter name="internalIrqMaskSystemInfo" value="3" />
   <parameter name="manuallyAssignCpuID" value="true" />
   <parameter name="mmu_TLBMissExcOffset" value="0" />
@@ -479,6 +500,11 @@
   <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
   <parameter name="userDefinedSettings" value="" />
  </module>
+ <module
+   name="sd_interface"
+   kind="final_sd_interface"
+   version="1.0"
+   enabled="1" />
  <module
    name="sdram"
    kind="altera_avalon_new_sdram_controller"
@@ -693,7 +719,7 @@
    start="proc_main.data_master"
    end="audio_0.Audio_Slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10001050" />
+  <parameter name="baseAddress" value="0x10001000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -702,7 +728,7 @@
    start="proc_main.data_master"
    end="jtag_uart.avalon_jtag_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10001090" />
+  <parameter name="baseAddress" value="0x10001c70" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -711,7 +737,7 @@
    start="proc_main.data_master"
    end="osu_sysid.control_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10001088" />
+  <parameter name="baseAddress" value="0x10001c68" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -756,7 +782,7 @@
    start="proc_main.data_master"
    end="sdram_pll.pll_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10001070" />
+  <parameter name="baseAddress" value="0x10001c50" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -765,7 +791,7 @@
    start="proc_main.data_master"
    end="ocm_null.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10001060" />
+  <parameter name="baseAddress" value="0x10001c40" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -783,7 +809,16 @@
    start="proc_main.data_master"
    end="timer.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10001000" />
+  <parameter name="baseAddress" value="0x10001c00" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="17.1"
+   start="proc_main.data_master"
+   end="sd_interface.sd_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10001800" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -792,7 +827,7 @@
    start="proc_main.instruction_master"
    end="osu_sysid.control_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10001088" />
+  <parameter name="baseAddress" value="0x10001c68" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -819,7 +854,7 @@
    start="proc_main.instruction_master"
    end="sdram_pll.pll_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10001070" />
+  <parameter name="baseAddress" value="0x10001c50" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -828,7 +863,7 @@
    start="proc_main.instruction_master"
    end="ocm_null.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10001060" />
+  <parameter name="baseAddress" value="0x10001c40" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -842,6 +877,7 @@
  </connection>
  <connection kind="clock" version="17.1" start="sdram_pll.c0" end="sdram.clk" />
  <connection kind="clock" version="17.1" start="clk_50.clk" end="audio_0.CLK" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="sd_interface.CLK" />
  <connection kind="clock" version="17.1" start="clk_50.clk" end="osu_sysid.clk" />
  <connection kind="clock" version="17.1" start="clk_50.clk" end="proc_main.clk" />
  <connection kind="clock" version="17.1" start="clk_50.clk" end="jtag_uart.clk" />
@@ -878,6 +914,11 @@
    version="17.1"
    start="clk_50.clk_reset"
    end="audio_0.RESET" />
+ <connection
+   kind="reset"
+   version="17.1"
+   start="clk_50.clk_reset"
+   end="sd_interface.RESET" />
  <connection
    kind="reset"
    version="17.1"
diff --git a/software/audio_sd_other/main.c b/software/audio_sd_other/main.c
index b9a2261..6490627 100644
--- a/software/audio_sd_other/main.c
+++ b/software/audio_sd_other/main.c
@@ -9,7 +9,7 @@
 #include <inttypes.h>
 #include <unistd.h>
 #include "system.h"
-
+#include <string.h>
 #include <ctype.h>
 #include <time.h>
 
@@ -72,32 +72,42 @@ int main() {
 	
 	//pin point the beginning of file
 	fileSize = Fat_FileSize(fileP);
-	uint32_t* audioDataInDram = malloc(512);
-	//memset(audioDataInDram,0xCC,fileSize);
-	//start mp3 decoding
-	//printf("start decoding mp3\n");
-	//decode(audioBuffer,2048,fileP,audioDataInDram);
-	//size_t start = clock();
+	fileSize = fileSize >> 4;
+	uint32_t* audioDataInDram = malloc(fileSize);
+	memset(audioDataInDram,0xCC,fileSize);
+
 
 	//size_t end = clock();
 	//printf("mp3 decoding finished!\n %d ms used!\n",end-start);
 	
 	//unsigned int ptr=0;
-	bool flag = 0;
+	//bool flag = 0;
+	
+	//for (i=0;i<(fileSize);++i){
+	i=0;
+	Fat_FileRead(fileP,audioDataInDram,fileSize);
 	fileSize = fileSize>>9;
-	for (i=0;i<(fileSize);++i){
-		if (*audioReady && flag){
-			for(j=0;j<256;j+=2){
-				audioData[j] = (audioDataInDram[j>>1]&(0xFF00)>>16);
-				audioData[j+1] = (audioDataInDram[j>>1]&(0x00FF));
-			}
-		}else{
-			Fat_FileRead(fileP,audioDataInDram,512);
-			if (!flag) flag=1;
+	//printf("%s\n", audioDataInDram);
+	while(i<fileSize){
+		if ((*audioReady)){
+				//Fat_FileRead(fileP,audioData,512);
+				for(j=0;j<128;++j){
+					audioData[j] = audioDataInDram[j];
+				//audioData[j+1] = (audioDataInDram[j>>1]&(0x00FF));
+					//printf("%c%c%c%c",  ((char*)(audioDataInDram+i))[0],((char*)(SDData+i))[1],((char*)(SDData+i))[2],((char*)(SDData+i))[3]);
+
+				}
+				//printf("%s",audioDataInDram);
+//			memcpy(audioData,audioDataInDram,512);
+		//}else{
+
+			//if (!flag) flag=1;
+				++i;
+				audioDataInDram += 128;
 		}
 	}
 	printf("Playback completed\n");
-	return 0;
+	goto AUDIO;
 }
 
 
diff --git a/software/audio_sd_other/terasic_fat/FatFileSystem.c b/software/audio_sd_other/terasic_fat/FatFileSystem.c
index 64a67dc..10e5749 100644
--- a/software/audio_sd_other/terasic_fat/FatFileSystem.c
+++ b/software/audio_sd_other/terasic_fat/FatFileSystem.c
@@ -393,7 +393,7 @@ bool Fat_FileRead(FAT_FILE_HANDLE hFileHandle, void *pBuffer, const int nBufferS
             }else{
                 // read secter data
                 bSuccess = fatReadSecter(pVol, PhysicalSecter);
-                
+
                 if (bSuccess){
                     // copy data to user buffer
                 
diff --git a/software/audio_sd_other/terasic_sdcard/sd_hal.c b/software/audio_sd_other/terasic_sdcard/sd_hal.c
index 92071fb..cabca96 100644
--- a/software/audio_sd_other/terasic_sdcard/sd_hal.c
+++ b/software/audio_sd_other/terasic_sdcard/sd_hal.c
@@ -35,15 +35,23 @@
 #include "sd_hw.h"
 #include "crc16.h"
 #include <inttypes.h>
-//#include "system.h"
+#include <unistd.h>
+#include "system.h"
 
-#define SD_BASE ((uint32_t*)(FINAL_SD_INTERFACE_0_BASE))
+#define SD_BASE ((uint32_t*)(SD_INTERFACE_BASE))
 //#define SD_BASE ((uint32_t*)0x10001000)
-volatile uint32_t* InterfaceCmd = SD_BASE + 0x81;
+/*volatile uint32_t* InterfaceCmd = SD_BASE + 0x81;
 volatile uint32_t* SDCmd = SD_BASE + 0x88;
 volatile uint32_t* SDResponse = SD_BASE + 0x82;
 volatile uint32_t* InterfaceStatus = SD_BASE + 0x84;
-volatile uint32_t* SDData = SD_BASE;
+volatile uint32_t* SDData = SD_BASE;*/
+
+#define InterfaceCmd (SD_BASE + 0x81)
+#define InterfaceStatus (SD_BASE + 0x84)
+#define SDCmd (SD_BASE + 0x88)
+#define SDResponse (SD_BASE + 0x82)
+#define SDData (SD_BASE)
+
 
 bool SDHAL_IsSupport4Bits(void){
     bool bYes = FALSE;
@@ -59,7 +67,8 @@ void SDHAL_Init(void){
 //    SD_CLK_HIGH;
 //    SD_CMD_HIGH;
 //    SD_DAT_LOW;
-	*InterfaceCmd = 7;
+    IOWR_32DIRECT(InterfaceCmd,0,7);
+    //*InterfaceCmd = 7;
 }
 
 void SDHAL_SendCmd(alt_u8 szCommand[6], int nCmdLen){
@@ -84,10 +93,12 @@ void SDHAL_SendCmd(alt_u8 szCommand[6], int nCmdLen){
 //        }
 //    }
     for (i=0;i<6;++i){
-    	*(SDCmd+i) = szCommand[i];
-    	//printf("%c sent, %c receive\n",szCommand[i],*(SDCmd+i));
+        IOWR_32DIRECT(SDCmd+i,0,szCommand[i]);
+        //*(SDCmd+i) = szCommand[i];
+        //printf("%c sent, %c receive\n",szCommand[i],*(SDCmd+i));
     }
-    *InterfaceCmd = 1;
+    //*InterfaceCmd = 1;
+    IOWR_32DIRECT(InterfaceCmd,0,1);
 }
 
 
@@ -99,16 +110,24 @@ bool SDHAL_GetResponse(alt_u8 szResponse[], int nLen){
     // int nCnt, nBitCnt, nIndex;
     // alt_u8 Value;
     int i;
-    *InterfaceCmd = 6;
-    while (!(*InterfaceStatus));
-    if (*InterfaceStatus == 3){ 
-    	printf("Response Timeout\n");
-    	return 0;}
-    szResponse[0] = *SDResponse;
+    //*InterfaceCmd = 6;
+    IOWR_32DIRECT(InterfaceCmd,0,6);
+    //while (!(*InterfaceStatus));
+    while (!(IORD_32DIRECT(InterfaceStatus,0)));
+    //if (*InterfaceStatus == 3){ 
+    if (IORD_32DIRECT(InterfaceStatus,0)==3) {
+        printf("Response Timeout\n");
+        return 0;
+    }
+    szResponse[0] = IORD_32DIRECT(SDResponse,0);
+    //szResponse[0] = *SDResponse;
     for (i=1;i<nLen;++i){
-    	*InterfaceCmd = 2;
-    	while (!(*InterfaceStatus));
-    	szResponse[i] = *SDResponse;
+        //*InterfaceCmd = 2;
+        IOWR_32DIRECT(InterfaceCmd,0,2);
+        //while (!(*InterfaceStatus));
+        while (!(IORD_32DIRECT(InterfaceStatus,0)));
+        //szResponse[i] = *SDResponse;
+        szResponse[i] = IORD_32DIRECT(SDResponse,0);
     }
     // SD_CMD_IN;
     
@@ -153,10 +172,10 @@ bool SDHAL_GetResponse(alt_u8 szResponse[], int nLen){
     //     }
     //     nIndex++;
     // } 
-    
+    //IOWR_32DIRECT((addr),offset,data);
     // A command with response. 8 clocks after the card response end bit.
-    *InterfaceCmd = 4;
-    
+    //*InterfaceCmd = 4;
+    IOWR_32DIRECT(InterfaceCmd,0,4);
     return 1;
 }
 
@@ -194,11 +213,20 @@ bool SDHAL_ReadData(alt_u8 szBuf[], int nBufLen){
 //       if (nTry++ > nMaxTry)
 //         return FALSE;        
 //     }     
-	int i;
-    *InterfaceCmd = 3;
-    while (!(*InterfaceStatus));
+    int i;
+    
+    //*InterfaceCmd = 3;
+    IOWR_32DIRECT(InterfaceCmd,0,3);
+    //printf("fucked\n");
+    //scanf("%d",&i);
+    //usleep(100);
+    //while (!(*InterfaceStatus));
+    while (!(IORD_32DIRECT(InterfaceStatus,0)));
     for (i=0;i<128;++i){
-    	((uint32_t*)szBuf)[i] = *(SDData+i);
+        //printf("%c%c%c%c",  ((char*)(SDData+i))[0],((char*)(SDData+i))[1],((char*)(SDData+i))[2],((char*)(SDData+i))[3]);
+        //usleep(20);
+        //((uint32_t*)szBuf)[i] = *(SDData+i);
+        ((uint32_t*)szBuf)[i] = IORD_32DIRECT(SDData+i,0);
     }
     //===== CRC16 and end-bit check (each channel is seperated)
 
@@ -207,8 +235,9 @@ bool SDHAL_ReadData(alt_u8 szBuf[], int nBufLen){
      
     // to provide8 (eight) clock cycles for the card to complete the operation before shutting down the clock 
     //SDHAL_DummyClock(8);     
-    *InterfaceCmd = 5;
-    *InterfaceCmd = 4;
+    //*InterfaceCmd = 5;
+    IOWR_32DIRECT(InterfaceCmd,0,5);
+    //*InterfaceCmd = 4;
     //Jump 16 + 1 + 8 = 25 cycles
     return 1;
 }
@@ -231,7 +260,8 @@ bool SDHAL_WriteData(alt_u8 szDataWrite[], int nDataLen){
 
 
 void SDHAL_DummyClock(int nClockCnt){
-	*InterfaceCmd = 4;
+    //*InterfaceCmd = 4;
+    IOWR_32DIRECT(InterfaceCmd,0,4);
 }
 
 
-- 
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