From d6bad8c35b589f7ae65cc6c82803fcfcff68573e Mon Sep 17 00:00:00 2001
From: Fang Lu <cc2lufang@gmail.com>
Date: Thu, 7 Dec 2017 17:22:55 -0600
Subject: [PATCH] polygon - shorten combinational logic

Registered output
---
 gl/painters/gl_painter_polygon.sv | 10 ++++++----
 gl/utils/gl_line_scanner.sv       |  7 +++++--
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/gl/painters/gl_painter_polygon.sv b/gl/painters/gl_painter_polygon.sv
index a68dfd5..9647b64 100644
--- a/gl/painters/gl_painter_polygon.sv
+++ b/gl/painters/gl_painter_polygon.sv
@@ -41,10 +41,12 @@ module gl_painter_polygon (
 	// Inclined line scanner instances
 	logic [9:0] l_x1, l_y1, l_x2, l_y2, r_x1, r_y1, r_x2, r_y2;
 	logic l_side, r_side;
-	gl_line_scanner scanner_left(.X({6'h0, x}), .Y({6'h0, y}), .SIDE(l_side),
-		.X1({6'h0,l_x1}), .Y1({6'h0,l_y1}), .X2({6'h0,l_x2}), .Y2({6'h0,l_y2}));
-	gl_line_scanner scanner_right(.X({6'h0, x}), .Y({6'h0, y}), .SIDE(r_side),
-		.X1({6'h0,r_x1}), .Y1({6'h0,r_y1}), .X2({6'h0,r_x2}), .Y2({6'h0,r_y2}));
+	gl_line_scanner scanner_left(.X({6'h0, x}), .Y({6'h0, y}),
+		.SIDE(l_side), .X1({6'h0,l_x1}), .Y1({6'h0,l_y1}),
+		.X2({6'h0,l_x2}), .Y2({6'h0,l_y2}), .CLOCK(CLOCK));
+	gl_line_scanner scanner_right(.X({6'h0, x}), .Y({6'h0, y}),
+		.SIDE(r_side), .X1({6'h0,r_x1}), .Y1({6'h0,r_y1}),
+		.X2({6'h0,r_x2}), .Y2({6'h0,r_y2}), .CLOCK(CLOCK));
 
 	// Midpoint tracking
 	logic [9:0] l_lim, l_lim_in, r_lim, r_lim_in, xbeg, xbeg_in;
diff --git a/gl/utils/gl_line_scanner.sv b/gl/utils/gl_line_scanner.sv
index 8f3c795..765e326 100644
--- a/gl/utils/gl_line_scanner.sv
+++ b/gl/utils/gl_line_scanner.sv
@@ -1,12 +1,15 @@
 module gl_line_scanner (
+	input logic CLOCK,
 	input logic signed [15:0] X1, Y1, X2, Y2,
 	input logic signed [15:0] X, Y,
 	output logic SIDE
 );
 
-logic signed [31:0] prod1, prod2 /*synthesis keep*/;
+logic signed [31:0] prod1, prod2;
 assign prod1 = (X-X1) * (Y2-Y1);
 assign prod2 = (Y-Y1) * (X2-X1);
-assign SIDE = (prod1 - prod2)>0;
+always_ff @(posedge CLOCK) begin
+	SIDE <= (prod1 - prod2)>0;
+end
 
 endmodule
-- 
GitLab