diff --git a/.gitignore b/.gitignore
index d35ba51e12ebc314b5f6d61e095c368f7f2feec5..d5b5002f5f5c6b42e587679f056e8bada40a6660 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,5 +1,6 @@
*.pdf
db/
+RemoteSystemsTempFiles/
incremental_db/
output_files/
simulation/
diff --git a/RemoteSystemsTempFiles/.project b/RemoteSystemsTempFiles/.project
deleted file mode 100644
index 5447a64fa9d029de5bd06a0ad372bebc0db9a9c1..0000000000000000000000000000000000000000
--- a/RemoteSystemsTempFiles/.project
+++ /dev/null
@@ -1,12 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>RemoteSystemsTempFiles</name>
- <comment></comment>
- <projects>
- </projects>
- <buildSpec>
- </buildSpec>
- <natures>
- <nature>org.eclipse.rse.ui.remoteSystemsTempNature</nature>
- </natures>
-</projectDescription>
diff --git a/hexdriver.sv b/hexdriver.sv
index 61a01ddbb306b4cd882bedfd882675096b863f28..40dd7b937204032417ee6a3f1da64deed3523aa6 100644
--- a/hexdriver.sv
+++ b/hexdriver.sv
@@ -22,7 +22,6 @@ always_comb begin
4'b1101 : Out = 7'b0100001; // 'd'
4'b1110 : Out = 7'b0000110; // 'E'
4'b1111 : Out = 7'b0001110; // 'F'
- default : Out = 7'bX;
endcase
end
diff --git a/input/hpi_io_intf.sv b/input/hpi_io_intf.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3b1eb51c45eb909aecc0bcea572257310508e803
--- /dev/null
+++ b/input/hpi_io_intf.sv
@@ -0,0 +1,43 @@
+// Interface between NIOS II and EZ-OTG chip
+module hpi_io_intf( input Clk, Reset,
+ input [1:0] from_sw_address,
+ output[15:0] from_sw_data_in,
+ input [15:0] from_sw_data_out,
+ input from_sw_r,from_sw_w,from_sw_cs,
+ inout [15:0] OTG_DATA,
+ output[1:0] OTG_ADDR,
+ output OTG_RD_N, OTG_WR_N, OTG_CS_N, OTG_RST_N
+ );
+
+// Buffer (register) for from_sw_data_out because inout bus should be driven
+// by a register, not combinational logic.
+logic [15:0] from_sw_data_out_buffer;
+
+// TODO: Fill in the blanks below.
+// OTG_DATA should be high Z (tristated) when NIOS is not writing to OTG_DATA inout bus.
+// Look at tristate.sv in lab 6 for an example.
+assign OTG_DATA = from_sw_w ? 16'hZZZZ: from_sw_data_out_buffer;
+assign OTG_RST_N = !Reset; // ?
+
+always_ff @ (posedge Clk)
+begin
+ if(Reset)
+ begin
+ from_sw_data_out_buffer <= 16'hcccc;
+ OTG_ADDR <= 2'b10; // ?
+ OTG_RD_N <= 1'b1;
+ OTG_WR_N <= 1'b1;
+ OTG_CS_N <= 1'b1;
+ from_sw_data_in <= 16'hcccc;
+ end
+ else
+ begin
+ from_sw_data_out_buffer <= from_sw_data_out;
+ OTG_ADDR <= from_sw_address;
+ OTG_RD_N <= from_sw_r;
+ OTG_WR_N <= from_sw_w;
+ OTG_CS_N <= from_sw_cs;
+ from_sw_data_in <= OTG_DATA;
+ end
+end
+endmodule
diff --git a/ps2kb_hw.tcl b/input/ps2kb_hw.tcl
similarity index 96%
rename from ps2kb_hw.tcl
rename to input/ps2kb_hw.tcl
index 1cfbad3a63506bf30efc3450caba610fde95755d..a5585a6d42bc6cacb9afa0f10f374a01a5c870f6 100644
--- a/ps2kb_hw.tcl
+++ b/input/ps2kb_hw.tcl
@@ -3,21 +3,21 @@
# DO NOT MODIFY
-#
+#
# ps2kb "PS/2 Keyboard Interface" v1.0
# 2017.11.18.22:12:04
# This module produces key events for PS/2 keyboard
-#
+#
-#
+#
# request TCL package from ACDS 16.1
-#
+#
package require -exact qsys 16.1
-#
+#
# module ps2kb
-#
+#
set_module_property DESCRIPTION "This module produces key events for PS/2 keyboard"
set_module_property NAME ps2kb
set_module_property VERSION 1.0
@@ -33,35 +33,35 @@ set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
-#
+#
# file sets
-#
+#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL ps2kb
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ps2kb.sv SYSTEM_VERILOG PATH input/ps2kb.sv TOP_LEVEL_FILE
+add_fileset_file ps2kb.sv SYSTEM_VERILOG PATH ps2kb.sv TOP_LEVEL_FILE
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL ps2kb
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ps2kb.sv SYSTEM_VERILOG PATH input/ps2kb.sv
+add_fileset_file ps2kb.sv SYSTEM_VERILOG PATH ps2kb.sv
-#
+#
# parameters
-#
+#
-#
+#
# display items
-#
+#
-#
+#
# connection point clock
-#
+#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
@@ -73,9 +73,9 @@ set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock CLK clk Input 1
-#
+#
# connection point reset
-#
+#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
@@ -88,9 +88,9 @@ set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset RESET reset Input 1
-#
+#
# connection point ps2_clk
-#
+#
add_interface ps2_clk conduit end
set_interface_property ps2_clk associatedClock clock
set_interface_property ps2_clk associatedReset ""
@@ -103,9 +103,9 @@ set_interface_property ps2_clk SVD_ADDRESS_GROUP ""
add_interface_port ps2_clk PS2_CLK export Bidir 1
-#
+#
# connection point ps2_data
-#
+#
add_interface ps2_data conduit end
set_interface_property ps2_data associatedClock clock
set_interface_property ps2_data associatedReset ""
@@ -118,9 +118,9 @@ set_interface_property ps2_data SVD_ADDRESS_GROUP ""
add_interface_port ps2_data PS2_DATA export Bidir 1
-#
+#
# connection point key_events
-#
+#
add_interface key_events avalon end
set_interface_property key_events addressUnits WORDS
set_interface_property key_events associatedClock clock
diff --git a/osu_fpga_toplevel.qsf b/osu_fpga_toplevel.qsf
index 480fe63973260d581458f996e83a1a66f7531834..f2e3275897d2c68ec7a27b22b2a4f96a86bd577a 100644
--- a/osu_fpga_toplevel.qsf
+++ b/osu_fpga_toplevel.qsf
@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY osu_fpga_toplevel
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:41:32 NOVEMBER 11, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -1118,9 +1118,12 @@ set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to *
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE input/hpi_io_intf.sv
set_global_assignment -name QIP_FILE otogame/synthesis/otogame.qip
set_global_assignment -name SDC_FILE timing.sdc
set_global_assignment -name SYSTEMVERILOG_FILE hexdriver.sv
set_global_assignment -name SYSTEMVERILOG_FILE input/ps2kb.sv
set_global_assignment -name SYSTEMVERILOG_FILE osu_fpga_toplevel.sv
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/osu_fpga_toplevel.sv b/osu_fpga_toplevel.sv
index 8705405fa3436a351918ce2cff99a11939d6dc0d..0563fc7d3035c64d11784aed28c853b4c4d7e1ce 100644
--- a/osu_fpga_toplevel.sv
+++ b/osu_fpga_toplevel.sv
@@ -9,22 +9,98 @@
*
*/
module osu_fpga_toplevel (
+ // Clock
input logic CLOCK_50,
+
+ // Buttons & LEDs
input logic [1:0] KEY,
output logic [7:0] LEDG,
output logic [17:0] LEDR,
output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
+
+ // DRAM
output logic [12:0] DRAM_ADDR,
output logic [1:0] DRAM_BA,
output logic DRAM_CAS_N, DRAM_CKE, DRAM_CS_N,
inout wire [31:0] DRAM_DQ,
output logic [3:0] DRAM_DQM,
output logic DRAM_RAS_N, DRAM_WE_N, DRAM_CLK,
- inout wire PS2_KBCLK, PS2_KBDAT
+
+ // SRAM
+
+ // Flash
+ output logic [22:0] FL_ADDR,
+ inout wire [7:0] FL_DQ,
+ output logic FL_CE_N, FL_OE_N, FL_WE_N, FL_RESET_N, FL_WP_N,
+ input logic FL_RY,
+
+ // sdcard
+
+ // PS/2
+ inout wire PS2_KBCLK, PS2_KBDAT,
+
+ // HPI (USB)
+ inout wire [15:0] OTG_DATA,
+ output logic [1:0] OTG_ADDR,
+ output logic OTG_CS_N, OTG_OE_N, OTG_WE_N, OTG_RST_N,
+ input logic[1:0] OTG_INT,
+
+ // VGA
+ output logic VGA_CLK,
+ output logic [7:0] VGA_R, VGA_G, VGA_B,
+ output logic VGA_SYNC_N, VGA_BLANK_N, VGA_VS, VGA_HS
+
+ // Audio
);
+ // Synchronizers
+ logic Reset_h, Clk;
+ always_ff @ (posedge Clk) begin
+ Reset_h <= ~(KEY[0]); // The push buttons are active low
+ end
+
+ // Additional wires for Flash
+ assign FL_WP_N = 1'b1;
+
+ // HPI wrapper
+ logic [1:0] hpi_addr;
+ logic [15:0] hpi_data_in, hpi_data_out;
+ logic hpi_r, hpi_w, hpi_cs;
+ hpi_io_intf hpi_io_inst(
+ .Clk(CLOCK_50),
+ .Reset(Reset_h),
+ // signals connected to NIOS II
+ .from_sw_address(hpi_addr),
+ .from_sw_data_in(hpi_data_in),
+ .from_sw_data_out(hpi_data_out),
+ .from_sw_r(hpi_r),
+ .from_sw_w(hpi_w),
+ .from_sw_cs(hpi_cs),
+ // signals connected to EZ-OTG chip
+ .OTG_DATA(OTG_DATA),
+ .OTG_ADDR(OTG_ADDR),
+ .OTG_RD_N(OTG_OE_N),
+ .OTG_WR_N(OTG_WE_N),
+ .OTG_CS_N(OTG_CS_N),
+ .OTG_RST_N(OTG_RST_N)
+ );
+
+ // Hex drivers
+ logic [31:0] hex_export;
+ hexdriver hexdrv7(.In(hex_export[31:28]), .Out(HEX7));
+ hexdriver hexdrv6(.In(hex_export[27:24]), .Out(HEX6));
+ hexdriver hexdrv5(.In(hex_export[23:20]), .Out(HEX5));
+ hexdriver hexdrv4(.In(hex_export[19:16]), .Out(HEX4));
+ hexdriver hexdrv3(.In(hex_export[15:12]), .Out(HEX3));
+ hexdriver hexdrv2(.In(hex_export[11:8]), .Out(HEX2));
+ hexdriver hexdrv1(.In(hex_export[7:4]), .Out(HEX1));
+ hexdriver hexdrv0(.In(hex_export[3:0]), .Out(HEX0));
+
+ // Main Program (SoC)
otogame main_soc (
+ // Clock
.clk_clk(CLOCK_50),
- .reset_reset_n(KEY[0]),
+ .reset_reset_n(~Reset_h),
+ // DRAM
.sdram_wire_addr(DRAM_ADDR),
.sdram_wire_ba(DRAM_BA),
.sdram_wire_cas_n(DRAM_CAS_N),
@@ -35,25 +111,27 @@ module osu_fpga_toplevel (
.sdram_wire_ras_n(DRAM_RAS_N),
.sdram_wire_we_n(DRAM_WE_N),
.sdram_clk_clk(DRAM_CLK),
+ // Flash
+ .flash_conn_ADDR(FL_ADDR),
+ .flash_conn_DQ(FL_DQ),
+ .flash_conn_CE_N(FL_CE_N),
+ .flash_conn_OE_N(FL_OE_N),
+ .flash_conn_WE_N(FL_WE_N),
+ .flash_conn_RST_N(FL_RESET_N),
+ // PS/2
.ps2_data_export(PS2_KBDAT),
- .ps2_clk_export(PS2_KBCLK)
+ .ps2_clk_export(PS2_KBCLK),
+ // USB
+ .otg_hpi_address_export(hpi_addr),
+ .otg_hpi_data_in_port(hpi_data_in),
+ .otg_hpi_data_out_port(hpi_data_out),
+ .otg_hpi_cs_export(hpi_cs),
+ .otg_hpi_r_export(hpi_r),
+ .otg_hpi_w_export(hpi_w),
+ // LEDs
+ .hex_export(hex_export),
+ .ledr_export(LEDR),
+ .ledg_export(LEDG)
);
- // logic[7:0] kdr1, kdr2, kur1, kur2, kc;
- // logic[2:0] st;
-
- // ps2kb kb(.CLK(CLOCK_50), .RESET(~KEY[0]), .AVL_READ(0), .AVL_WRITE(0), .AVL_CS(0),
- // .AVL_BYTE_EN(0), .AVL_ADDR(0), .AVL_WRITEDATA(0), .AVL_READDATA(0),
- // .PS2_CLK(PS2_KBCLK), .PS2_DATA(PS2_KBDAT), .debug_state(LEDG[2:0]), .debug_kc(LEDR[7:0]),
- // .debug_kdr1(kdr1), .debug_kdr2(kdr2), .debug_kur1(kur1), .debug_kur2(kur2));
-
- // hexdriver kd1l(.In(kdr1[3:0]), .Out(HEX0));
- // hexdriver kd1h(.In(kdr1[7:4]), .Out(HEX1));
- // hexdriver kd2l(.In(kdr2[3:0]), .Out(HEX2));
- // hexdriver kd2h(.In(kdr2[7:4]), .Out(HEX3));
- // hexdriver ku1l(.In(kur1[3:0]), .Out(HEX4));
- // hexdriver ku1h(.In(kur1[7:4]), .Out(HEX5));
- // hexdriver ku2l(.In(kur2[3:0]), .Out(HEX6));
- // hexdriver ku2h(.In(kur2[7:4]), .Out(HEX7));
- // hexdriver sthex(.In({1'b0,st}), .Out(HEX7));
endmodule
diff --git a/osu_fpga_toplevel_assignment_defaults.qdf b/osu_fpga_toplevel_assignment_defaults.qdf
new file mode 100644
index 0000000000000000000000000000000000000000..e44468ff093ba55f5104594c4b5b2853f466d92d
--- /dev/null
+++ b/osu_fpga_toplevel_assignment_defaults.qdf
@@ -0,0 +1,807 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors. Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+# Date created = 02:27:58 November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+# automatically by the Quartus Prime software and is used
+# to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL Enable
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/otogame.qsys b/otogame.qsys
index 32161491af34c542d168b3ade4540f48eb6b7143..0f38560ffde8dbe9b59c48423cdd7f003d829d51 100644
--- a/otogame.qsys
+++ b/otogame.qsys
@@ -21,15 +21,25 @@
{
datum _sortIndex
{
- value = "8";
+ value = "10";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
}
element flash.flash_data
{
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "402653184";
+ value = "536870912";
type = "String";
}
}
@@ -37,7 +47,7 @@
{
datum baseAddress
{
- value = "406847488";
+ value = "552599552";
type = "String";
}
}
@@ -45,7 +55,7 @@
{
datum _sortIndex
{
- value = "6";
+ value = "1";
type = "int";
}
}
@@ -57,13 +67,26 @@
type = "String";
}
}
+ element jtag_uart.irq
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
element keyboard
{
datum _sortIndex
{
- value = "9";
+ value = "11";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
}
element keyboard.key_events
{
@@ -81,107 +104,179 @@
type = "String";
}
}
- element ocm_null
+ element mouse_btn_in
{
datum _sortIndex
{
- value = "2";
+ value = "19";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element mouse_btn_in.s1
+ {
+ datum baseAddress
+ {
+ value = "20800";
+ type = "String";
+ }
}
- element osu_sysid
+ element mouse_btn_out
{
datum _sortIndex
{
- value = "5";
+ value = "18";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
- element osu_sysid.control_slave
+ element mouse_btn_out.s1
{
datum baseAddress
{
- value = "8328";
+ value = "20800";
type = "String";
}
}
- element otogame
+ element mouse_scroll_in
{
- datum _originalDeviceFamily
+ datum _sortIndex
{
- value = "Cyclone IV E";
+ value = "17";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element mouse_scroll_in.s1
+ {
+ datum baseAddress
+ {
+ value = "20784";
type = "String";
}
}
- element otogame
+ element mouse_scroll_out
{
- datum _originalDeviceFamily
+ datum _sortIndex
{
- value = "Cyclone IV E";
+ value = "16";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element mouse_scroll_out.s1
+ {
+ datum baseAddress
+ {
+ value = "20784";
type = "String";
}
}
- element otogame
+ element mouse_x_in
{
- datum _originalDeviceFamily
+ datum _sortIndex
{
- value = "Cyclone IV E";
+ value = "13";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element mouse_x_in.s1
+ {
+ datum baseAddress
+ {
+ value = "20752";
type = "String";
}
}
- element proc_main
+ element mouse_x_out
{
datum _sortIndex
{
- value = "1";
+ value = "12";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
- element proc_main.jtag_debug_module
+ element mouse_x_out.s1
{
datum baseAddress
{
- value = "6144";
+ value = "20752";
type = "String";
}
}
- element sdram
+ element mouse_y_in
{
datum _sortIndex
{
- value = "3";
+ value = "15";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
- element sdram.s1
+ element mouse_y_in.s1
{
datum baseAddress
{
- value = "268435456";
+ value = "20768";
type = "String";
}
}
- element sdram_pll
+ element mouse_y_out
{
datum _sortIndex
{
- value = "4";
+ value = "14";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
- element sdram_pll.pll_slave
+ element mouse_y_out.s1
{
datum baseAddress
{
- value = "48";
+ value = "20768";
type = "String";
}
}
- element timer
+ element ocm_null
{
datum _sortIndex
{
- value = "7";
+ value = "8";
type = "int";
}
datum sopceditor_expanded
@@ -190,129 +285,1100 @@
type = "boolean";
}
}
- element timer.s1
+ element otg_clock_crossing_bridge
+ {
+ datum _sortIndex
+ {
+ value = "25";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element otg_clock_crossing_bridge.s0
{
datum baseAddress
{
- value = "64";
+ value = "805306368";
type = "String";
}
}
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="EP4CE115F29C7" />
- <parameter name="deviceFamily" value="Cyclone IV E" />
- <parameter name="deviceSpeedGrade" value="7" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="osu_fpga.qpf" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="clk" internal="clk_50.clk_in" type="clock" dir="end" />
- <interface name="ps2_clk" internal="keyboard.ps2_clk" type="conduit" dir="end" />
- <interface name="ps2_clock_conn" internal="keyboard.ps2_clock_conn" />
- <interface name="ps2_conn" internal="keyboard.ps2_export" />
- <interface name="ps2_data" internal="keyboard.ps2_data" type="conduit" dir="end" />
- <interface name="ps2_data_conn" internal="keyboard.ps2_data_conn" />
- <interface name="reset" internal="clk_50.clk_in_reset" type="reset" dir="end" />
- <interface name="sdram_clk" internal="sdram_pll.c1" type="clock" dir="start" />
- <interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
- <module name="clk_50" kind="clock_source" version="17.0" enabled="1">
- <parameter name="clockFrequency" value="50000000" />
- <parameter name="clockFrequencyKnown" value="true" />
- <parameter name="inputClockFrequency" value="0" />
- <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <module
- name="flash"
- kind="Altera_UP_Flash_Memory_IP_Core_Avalon_Interface"
- version="17.0"
- enabled="0">
- <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
- <parameter name="FLASH_MEMORY_ADDRESS_WIDTH" value="22" />
- </module>
- <module
- name="jtag_uart"
- kind="altera_avalon_jtag_uart"
- version="17.0"
- enabled="1">
- <parameter name="allowMultipleConnections" value="false" />
- <parameter name="avalonSpec" value="2.0" />
- <parameter name="clkFreq" value="50000000" />
- <parameter name="hubInstanceID" value="0" />
- <parameter name="readBufferDepth" value="64" />
- <parameter name="readIRQThreshold" value="8" />
- <parameter name="simInputCharacterStream" value="" />
- <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
- <parameter name="useRegistersForReadBuffer" value="false" />
- <parameter name="useRegistersForWriteBuffer" value="false" />
- <parameter name="useRelativePathForSimFile" value="false" />
- <parameter name="writeBufferDepth" value="64" />
- <parameter name="writeIRQThreshold" value="8" />
- </module>
- <module name="keyboard" kind="ps2kb" version="1.0" enabled="1" />
- <module
- name="ocm_null"
- kind="altera_avalon_onchip_memory2"
- version="17.0"
- enabled="1">
- <parameter name="allowInSystemMemoryContentEditor" value="false" />
- <parameter name="autoInitializationFileName">$${FILENAME}_ocm_null</parameter>
- <parameter name="blockType" value="AUTO" />
- <parameter name="copyInitFile" value="false" />
- <parameter name="dataWidth" value="32" />
- <parameter name="dataWidth2" value="32" />
- <parameter name="deviceFamily" value="Cyclone IV E" />
- <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
- <parameter name="dualPort" value="false" />
- <parameter name="ecc_enabled" value="false" />
- <parameter name="enPRInitMode" value="false" />
- <parameter name="enableDiffWidth" value="false" />
- <parameter name="initMemContent" value="true" />
- <parameter name="initializationFileName" value="onchip_mem.hex" />
- <parameter name="instanceID" value="NONE" />
- <parameter name="memorySize" value="16" />
- <parameter name="readDuringWriteMode" value="DONT_CARE" />
- <parameter name="resetrequest_enabled" value="true" />
- <parameter name="simAllowMRAMContentsFile" value="false" />
- <parameter name="simMemInitOnlyFilename" value="0" />
- <parameter name="singleClockOperation" value="false" />
- <parameter name="slave1Latency" value="1" />
- <parameter name="slave2Latency" value="1" />
- <parameter name="useNonDefaultInitFile" value="false" />
- <parameter name="useShallowMemBlocks" value="false" />
- <parameter name="writable" value="true" />
- </module>
- <module
- name="osu_sysid"
- kind="altera_avalon_sysid_qsys"
- version="17.0"
- enabled="1">
- <parameter name="id" value="1869837601" />
+ element otg_hpi_address
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element otg_hpi_address.s1
+ {
+ datum baseAddress
+ {
+ value = "8720";
+ type = "String";
+ }
+ }
+ element otg_hpi_cs
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element otg_hpi_cs.s1
+ {
+ datum baseAddress
+ {
+ value = "8704";
+ type = "String";
+ }
+ }
+ element otg_hpi_data
+ {
+ datum _sortIndex
+ {
+ value = "22";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element otg_hpi_data.s1
+ {
+ datum baseAddress
+ {
+ value = "8736";
+ type = "String";
+ }
+ }
+ element otg_hpi_r
+ {
+ datum _sortIndex
+ {
+ value = "23";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element otg_hpi_r.s1
+ {
+ datum baseAddress
+ {
+ value = "8752";
+ type = "String";
+ }
+ }
+ element otg_hpi_w
+ {
+ datum _sortIndex
+ {
+ value = "24";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element otg_hpi_w.s1
+ {
+ datum baseAddress
+ {
+ value = "8768";
+ type = "String";
+ }
+ }
+ element otogame
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Cyclone IV E";
+ type = "String";
+ }
+ }
+ element otogame
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Cyclone IV E";
+ type = "String";
+ }
+ }
+ element otogame
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Cyclone IV E";
+ type = "String";
+ }
+ }
+ element pio_hex
+ {
+ datum _sortIndex
+ {
+ value = "26";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_hex.s1
+ {
+ datum baseAddress
+ {
+ value = "8448";
+ type = "String";
+ }
+ }
+ element pio_ledg
+ {
+ datum _sortIndex
+ {
+ value = "28";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_ledg.s1
+ {
+ datum baseAddress
+ {
+ value = "8480";
+ type = "String";
+ }
+ }
+ element pio_ledr
+ {
+ datum _sortIndex
+ {
+ value = "27";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_ledr.s1
+ {
+ datum baseAddress
+ {
+ value = "8464";
+ type = "String";
+ }
+ }
+ element pll
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element pll.pll_slave
+ {
+ datum baseAddress
+ {
+ value = "48";
+ type = "String";
+ }
+ }
+ element proc_main
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element proc_main.clk
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element proc_main.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "4096";
+ type = "String";
+ }
+ }
+ element proc_usb
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ }
+ element proc_usb.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "6144";
+ type = "String";
+ }
+ }
+ element sdram
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element sdram.s1
+ {
+ datum baseAddress
+ {
+ value = "268435456";
+ type = "String";
+ }
+ }
+ element sysid_main
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element sysid_main.control_slave
+ {
+ datum baseAddress
+ {
+ value = "8320";
+ type = "String";
+ }
+ }
+ element sysid_usb
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ }
+ element sysid_usb.control_slave
+ {
+ datum baseAddress
+ {
+ value = "8320";
+ type = "String";
+ }
+ }
+ element timer
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element timer.irq
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element timer.reset
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element timer.s1
+ {
+ datum baseAddress
+ {
+ value = "64";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4CE115F29C7" />
+ <parameter name="deviceFamily" value="Cyclone IV E" />
+ <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="osu_fpga.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk" internal="clk_50.clk_in" type="clock" dir="end" />
+ <interface
+ name="flash_conn"
+ internal="flash.conduit_end"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="hex"
+ internal="pio_hex.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ledg"
+ internal="pio_ledg.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ledr"
+ internal="pio_ledr.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="otg_hpi_address"
+ internal="otg_hpi_address.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="otg_hpi_cs"
+ internal="otg_hpi_cs.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="otg_hpi_data"
+ internal="otg_hpi_data.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="otg_hpi_r"
+ internal="otg_hpi_r.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="otg_hpi_w"
+ internal="otg_hpi_w.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface name="ps2_clk" internal="keyboard.ps2_clk" type="conduit" dir="end" />
+ <interface name="ps2_clock_conn" internal="keyboard.ps2_clock_conn" />
+ <interface name="ps2_conn" internal="keyboard.ps2_export" />
+ <interface name="ps2_data" internal="keyboard.ps2_data" type="conduit" dir="end" />
+ <interface name="ps2_data_conn" internal="keyboard.ps2_data_conn" />
+ <interface name="reset" internal="clk_50.clk_in_reset" type="reset" dir="end" />
+ <interface name="sdram_clk" internal="pll.c1" type="clock" dir="start" />
+ <interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
+ <module name="clk_50" kind="clock_source" version="17.1" enabled="1">
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+ name="flash"
+ kind="Altera_UP_Flash_Memory_IP_Core_Avalon_Interface"
+ version="17.1"
+ enabled="1">
+ <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ <parameter name="FLASH_MEMORY_ADDRESS_WIDTH" value="23" />
+ </module>
+ <module
+ name="jtag_uart"
+ kind="altera_avalon_jtag_uart"
+ version="17.1"
+ enabled="1">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="avalonSpec" value="2.0" />
+ <parameter name="clkFreq" value="50000000" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream" value="" />
+ <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module name="keyboard" kind="ps2kb" version="1.0" enabled="1" />
+ <module
+ name="mouse_btn_in"
+ kind="altera_avalon_pio"
+ version="17.1"
+ enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Input" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="3" />
+ </module>
+ <module
+ name="mouse_btn_out"
+ kind="altera_avalon_pio"
+ version="17.1"
+ enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="3" />
+ </module>
+ <module
+ name="mouse_scroll_in"
+ kind="altera_avalon_pio"
+ version="17.1"
+ enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Input" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="8" />
+ </module>
+ <module
+ name="mouse_scroll_out"
+ kind="altera_avalon_pio"
+ version="17.1"
+ enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="8" />
+ </module>
+ <module name="mouse_x_in" kind="altera_avalon_pio" version="17.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Input" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="16" />
+ </module>
+ <module
+ name="mouse_x_out"
+ kind="altera_avalon_pio"
+ version="17.1"
+ enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="16" />
+ </module>
+ <module name="mouse_y_in" kind="altera_avalon_pio" version="17.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Input" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="16" />
+ </module>
+ <module
+ name="mouse_y_out"
+ kind="altera_avalon_pio"
+ version="17.1"
+ enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="16" />
+ </module>
+ <module
+ name="ocm_null"
+ kind="altera_avalon_onchip_memory2"
+ version="17.1"
+ enabled="1">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">$${FILENAME}_ocm_null</parameter>
+ <parameter name="blockType" value="AUTO" />
+ <parameter name="copyInitFile" value="false" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="dataWidth2" value="32" />
+ <parameter name="deviceFamily" value="Cyclone IV E" />
+ <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="dualPort" value="false" />
+ <parameter name="ecc_enabled" value="false" />
+ <parameter name="enPRInitMode" value="false" />
+ <parameter name="enableDiffWidth" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_mem.hex" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="16" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="false" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ name="otg_clock_crossing_bridge"
+ kind="altera_avalon_mm_clock_crossing_bridge"
+ version="17.1"
+ enabled="1">
+ <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+ <parameter name="ADDRESS_WIDTH" value="10" />
+ <parameter name="COMMAND_FIFO_DEPTH" value="32" />
+ <parameter name="DATA_WIDTH" value="32" />
+ <parameter name="MASTER_SYNC_DEPTH" value="3" />
+ <parameter name="MAX_BURST_SIZE" value="1" />
+ <parameter name="RESPONSE_FIFO_DEPTH" value="32" />
+ <parameter name="SLAVE_SYNC_DEPTH" value="3" />
+ <parameter name="SYMBOL_WIDTH" value="8" />
+ <parameter name="SYSINFO_ADDR_WIDTH" value="14" />
+ <parameter name="USE_AUTO_ADDRESS_WIDTH" value="1" />
+ </module>
+ <module
+ name="otg_hpi_address"
+ kind="altera_avalon_pio"
+ version="17.1"
+ enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="10000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="2" />
+ </module>
+ <module name="otg_hpi_cs" kind="altera_avalon_pio" version="17.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="10000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module
+ name="otg_hpi_data"
+ kind="altera_avalon_pio"
+ version="17.1"
+ enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="10000000" />
+ <parameter name="direction" value="InOut" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="16" />
+ </module>
+ <module name="otg_hpi_r" kind="altera_avalon_pio" version="17.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="10000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module name="otg_hpi_w" kind="altera_avalon_pio" version="17.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="10000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module name="pio_hex" kind="altera_avalon_pio" version="17.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module name="pio_ledg" kind="altera_avalon_pio" version="17.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="9" />
+ </module>
+ <module name="pio_ledr" kind="altera_avalon_pio" version="17.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="18" />
+ </module>
+ <module name="pll" kind="altpll" version="17.1" enabled="1">
+ <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+ <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+ <parameter name="BANDWIDTH" value="" />
+ <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+ <parameter name="CLK0_DIVIDE_BY" value="1" />
+ <parameter name="CLK0_DUTY_CYCLE" value="50" />
+ <parameter name="CLK0_MULTIPLY_BY" value="1" />
+ <parameter name="CLK0_PHASE_SHIFT" value="0" />
+ <parameter name="CLK1_DIVIDE_BY" value="1" />
+ <parameter name="CLK1_DUTY_CYCLE" value="50" />
+ <parameter name="CLK1_MULTIPLY_BY" value="1" />
+ <parameter name="CLK1_PHASE_SHIFT" value="-3000" />
+ <parameter name="CLK2_DIVIDE_BY" value="5" />
+ <parameter name="CLK2_DUTY_CYCLE" value="50" />
+ <parameter name="CLK2_MULTIPLY_BY" value="1" />
+ <parameter name="CLK2_PHASE_SHIFT" value="0" />
+ <parameter name="CLK3_DIVIDE_BY" value="1" />
+ <parameter name="CLK3_DUTY_CYCLE" value="50" />
+ <parameter name="CLK3_MULTIPLY_BY" value="2" />
+ <parameter name="CLK3_PHASE_SHIFT" value="0" />
+ <parameter name="CLK4_DIVIDE_BY" value="" />
+ <parameter name="CLK4_DUTY_CYCLE" value="" />
+ <parameter name="CLK4_MULTIPLY_BY" value="" />
+ <parameter name="CLK4_PHASE_SHIFT" value="" />
+ <parameter name="CLK5_DIVIDE_BY" value="" />
+ <parameter name="CLK5_DUTY_CYCLE" value="" />
+ <parameter name="CLK5_MULTIPLY_BY" value="" />
+ <parameter name="CLK5_PHASE_SHIFT" value="" />
+ <parameter name="CLK6_DIVIDE_BY" value="" />
+ <parameter name="CLK6_DUTY_CYCLE" value="" />
+ <parameter name="CLK6_MULTIPLY_BY" value="" />
+ <parameter name="CLK6_PHASE_SHIFT" value="" />
+ <parameter name="CLK7_DIVIDE_BY" value="" />
+ <parameter name="CLK7_DUTY_CYCLE" value="" />
+ <parameter name="CLK7_MULTIPLY_BY" value="" />
+ <parameter name="CLK7_PHASE_SHIFT" value="" />
+ <parameter name="CLK8_DIVIDE_BY" value="" />
+ <parameter name="CLK8_DUTY_CYCLE" value="" />
+ <parameter name="CLK8_MULTIPLY_BY" value="" />
+ <parameter name="CLK8_PHASE_SHIFT" value="" />
+ <parameter name="CLK9_DIVIDE_BY" value="" />
+ <parameter name="CLK9_DUTY_CYCLE" value="" />
+ <parameter name="CLK9_MULTIPLY_BY" value="" />
+ <parameter name="CLK9_PHASE_SHIFT" value="" />
+ <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+ <parameter name="DOWN_SPREAD" value="" />
+ <parameter name="DPA_DIVIDER" value="" />
+ <parameter name="DPA_DIVIDE_BY" value="" />
+ <parameter name="DPA_MULTIPLY_BY" value="" />
+ <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+ <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+ <parameter name="FEEDBACK_SOURCE" value="" />
+ <parameter name="GATE_LOCK_COUNTER" value="" />
+ <parameter name="GATE_LOCK_SIGNAL" value="" />
+ <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 5 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 1 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -3000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#CLK3_MULTIPLY_BY 2 CT#PORT_LOCKED PORT_UNUSED</parameter>
+ <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+ <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+ <parameter name="HIDDEN_IF_PORTS">IF#phasecounterselect {input 4} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}</parameter>
+ <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+ <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+ <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+ <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 10.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 -3.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE3 100.000000 PT#EFF_OUTPUT_FREQ_VALUE2 10.000000 PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 ns PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1508019453416741.mif PT#ACTIVECLK_CHECK 0</parameter>
+ <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+ <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+ <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Cyclone IV E" />
+ <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="LOCK_HIGH" value="" />
+ <parameter name="LOCK_LOW" value="" />
+ <parameter name="OPERATION_MODE" value="NORMAL" />
+ <parameter name="PLL_TYPE" value="AUTO" />
+ <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+ <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+ <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+ <parameter name="PORT_ENABLE0" value="" />
+ <parameter name="PORT_ENABLE1" value="" />
+ <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+ <parameter name="PORT_FBOUT" value="" />
+ <parameter name="PORT_INCLK0" value="PORT_USED" />
+ <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+ <parameter name="PORT_LOCKED" value="PORT_UNUSED" />
+ <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+ <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCLKOUT0" value="" />
+ <parameter name="PORT_SCLKOUT1" value="" />
+ <parameter name="PORT_VCOOVERRANGE" value="" />
+ <parameter name="PORT_VCOUNDERRANGE" value="" />
+ <parameter name="PORT_clk0" value="PORT_USED" />
+ <parameter name="PORT_clk1" value="PORT_USED" />
+ <parameter name="PORT_clk2" value="PORT_USED" />
+ <parameter name="PORT_clk3" value="PORT_USED" />
+ <parameter name="PORT_clk4" value="PORT_UNUSED" />
+ <parameter name="PORT_clk5" value="PORT_UNUSED" />
+ <parameter name="PORT_clk6" value="" />
+ <parameter name="PORT_clk7" value="" />
+ <parameter name="PORT_clk8" value="" />
+ <parameter name="PORT_clk9" value="" />
+ <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+ <parameter name="PORT_extclkena0" value="" />
+ <parameter name="PORT_extclkena1" value="" />
+ <parameter name="PORT_extclkena2" value="" />
+ <parameter name="PORT_extclkena3" value="" />
+ <parameter name="PRIMARY_CLOCK" value="" />
+ <parameter name="QUALIFY_CONF_DONE" value="" />
+ <parameter name="SCAN_CHAIN" value="" />
+ <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+ <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+ <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+ <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+ <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+ <parameter name="SKIP_VCO" value="" />
+ <parameter name="SPREAD_FREQUENCY" value="" />
+ <parameter name="SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+ <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+ <parameter name="SWITCH_OVER_TYPE" value="" />
+ <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+ <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="VCO_DIVIDE_BY" value="" />
+ <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+ <parameter name="VCO_MULTIPLY_BY" value="" />
+ <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+ <parameter name="WIDTH_CLOCK" value="5" />
+ <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module name="proc_main" kind="altera_nios2_qsys" version="16.1" enabled="1">
+ <parameter name="bht_ramBlockType" value="Automatic" />
+ <parameter name="breakOffset" value="32" />
+ <parameter name="breakSlave">proc_main.jtag_debug_module</parameter>
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="cpuID_stored" value="0" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="dataAddrWidth" value="30" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='pll.pll_slave' start='0x30' end='0x40' /><slave name='timer.s1' start='0x40' end='0x60' /><slave name='proc_main.jtag_debug_module' start='0x1000' end='0x1800' /><slave name='sysid_main.control_slave' start='0x2080' end='0x2088' /><slave name='jtag_uart.avalon_jtag_slave' start='0x2090' end='0x2098' /><slave name='pio_hex.s1' start='0x2100' end='0x2110' /><slave name='pio_ledr.s1' start='0x2110' end='0x2120' /><slave name='pio_ledg.s1' start='0x2120' end='0x2130' /><slave name='keyboard.key_events' start='0x5000' end='0x5010' /><slave name='mouse_x_in.s1' start='0x5110' end='0x5120' /><slave name='mouse_y_in.s1' start='0x5120' end='0x5130' /><slave name='mouse_scroll_in.s1' start='0x5130' end='0x5140' /><slave name='mouse_btn_in.s1' start='0x5140' end='0x5150' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /><slave name='flash.flash_data' start='0x20000000' end='0x20800000' /><slave name='flash.flash_erase_control' start='0x20F00000' end='0x20F00004' /></address-map>]]></parameter>
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dcache_lineSize" value="32" />
+ <parameter name="dcache_numTCDM" value="0" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_size" value="2048" />
+ <parameter name="dcache_tagramBlockType" value="Automatic" />
+ <parameter name="dcache_victim_buf_impl" value="ram" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="deviceFamilyName" value="Cyclone IV E" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="exceptionSlave" value="sdram.s1" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="icache_numTCIM" value="0" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_size" value="4096" />
+ <parameter name="icache_tagramBlockType" value="Automatic" />
+ <parameter name="impl" value="Tiny" />
+ <parameter name="instAddrWidth" value="29" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='proc_main.jtag_debug_module' start='0x1000' end='0x1800' /><slave name='sysid_main.control_slave' start='0x2080' end='0x2088' /><slave name='jtag_uart.avalon_jtag_slave' start='0x2090' end='0x2098' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
+ <parameter name="internalIrqMaskSystemInfo" value="3" />
+ <parameter name="manuallyAssignCpuID" value="true" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="mmu_TLBMissExcSlave" value="None" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_processIDNumBits" value="8" />
+ <parameter name="mmu_ramBlockType" value="Automatic" />
+ <parameter name="mmu_tlbNumWays" value="16" />
+ <parameter name="mmu_tlbPtrSz" value="7" />
+ <parameter name="mmu_udtlbNumEntries" value="6" />
+ <parameter name="mmu_uitlbNumEntries" value="4" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mpu_minDataRegionSize" value="12" />
+ <parameter name="mpu_minInstRegionSize" value="12" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
+ <parameter name="ocimem_ramBlockType" value="Automatic" />
+ <parameter name="regfile_ramBlockType" value="Automatic" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="resetSlave" value="sdram.s1" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTrace_user" value="false" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_asic_enabled" value="false" />
+ <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_bhtPtrSz" value="8" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_breakslaveoveride" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_dc_ecc_present" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_dtcm_ecc_present" value="false" />
+ <parameter name="setting_ecc_present" value="false" />
+ <parameter name="setting_ecc_sim_test_ports" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_export_large_RAMs" value="false" />
+ <parameter name="setting_exportvectors" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_ic_ecc_present" value="true" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_itcm_ecc_present" value="false" />
+ <parameter name="setting_mmu_ecc_present" value="true" />
+ <parameter name="setting_oci_export_jtag_signals" value="false" />
+ <parameter name="setting_perfCounterWidth" value="32" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_removeRAMinit" value="false" />
+ <parameter name="setting_rf_ecc_present" value="true" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="userDefinedSettings" value="" />
</module>
- <module name="proc_main" kind="altera_nios2_qsys" version="16.1" enabled="1">
+ <module name="proc_usb" kind="altera_nios2_qsys" version="16.1" enabled="1">
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
- <parameter name="breakSlave">proc_main.jtag_debug_module</parameter>
+ <parameter name="breakSlave">proc_usb.jtag_debug_module</parameter>
<parameter name="clockFrequency" value="50000000" />
<parameter name="cpuID" value="0" />
<parameter name="cpuID_stored" value="0" />
<parameter name="cpuReset" value="false" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
- <parameter name="dataAddrWidth" value="29" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='sdram_pll.pll_slave' start='0x30' end='0x40' /><slave name='timer.s1' start='0x40' end='0x60' /><slave name='proc_main.jtag_debug_module' start='0x1800' end='0x2000' /><slave name='osu_sysid.control_slave' start='0x2088' end='0x2090' /><slave name='jtag_uart.avalon_jtag_slave' start='0x2090' end='0x2098' /><slave name='keyboard.key_events' start='0x5000' end='0x5010' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
+ <parameter name="dataAddrWidth" value="30" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='timer.s1' start='0x40' end='0x60' /><slave name='proc_usb.jtag_debug_module' start='0x1800' end='0x2000' /><slave name='sysid_usb.control_slave' start='0x2080' end='0x2088' /><slave name='jtag_uart.avalon_jtag_slave' start='0x2090' end='0x2098' /><slave name='otg_hpi_cs.s1' start='0x2200' end='0x2210' /><slave name='otg_hpi_address.s1' start='0x2210' end='0x2220' /><slave name='otg_hpi_data.s1' start='0x2220' end='0x2230' /><slave name='otg_hpi_r.s1' start='0x2230' end='0x2240' /><slave name='otg_hpi_w.s1' start='0x2240' end='0x2250' /><slave name='mouse_x_out.s1' start='0x5110' end='0x5120' /><slave name='mouse_y_out.s1' start='0x5120' end='0x5130' /><slave name='mouse_scroll_out.s1' start='0x5130' end='0x5140' /><slave name='mouse_btn_out.s1' start='0x5140' end='0x5150' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /><slave name='otg_hpi_cs.s1' start='0x30002200' end='0x30002210' /><slave name='otg_hpi_address.s1' start='0x30002210' end='0x30002220' /><slave name='otg_hpi_data.s1' start='0x30002220' end='0x30002230' /><slave name='otg_hpi_r.s1' start='0x30002230' end='0x30002240' /><slave name='otg_hpi_w.s1' start='0x30002240' end='0x30002250' /></address-map>]]></parameter>
<parameter name="dcache_bursts" value="false" />
<parameter name="dcache_lineSize" value="32" />
<parameter name="dcache_numTCDM" value="0" />
@@ -339,7 +1405,7 @@
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Tiny" />
<parameter name="instAddrWidth" value="29" />
- <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='sdram_pll.pll_slave' start='0x30' end='0x40' /><slave name='proc_main.jtag_debug_module' start='0x1800' end='0x2000' /><slave name='osu_sysid.control_slave' start='0x2088' end='0x2090' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='proc_usb.jtag_debug_module' start='0x1800' end='0x2000' /><slave name='sysid_usb.control_slave' start='0x2080' end='0x2088' /><slave name='jtag_uart.avalon_jtag_slave' start='0x2090' end='0x2098' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
<parameter name="internalIrqMaskSystemInfo" value="3" />
<parameter name="manuallyAssignCpuID" value="true" />
<parameter name="mmu_TLBMissExcOffset" value="0" />
@@ -432,7 +1498,7 @@
<module
name="sdram"
kind="altera_avalon_new_sdram_controller"
- version="17.0"
+ version="17.1"
enabled="1">
<parameter name="TAC" value="5.5" />
<parameter name="TMRD" value="3" />
@@ -458,174 +1524,21 @@
<parameter name="registerDataIn" value="true" />
<parameter name="rowWidth" value="13" />
</module>
- <module name="sdram_pll" kind="altpll" version="17.0" enabled="1">
- <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
- <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
- <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
- <parameter name="BANDWIDTH" value="" />
- <parameter name="BANDWIDTH_TYPE" value="AUTO" />
- <parameter name="CLK0_DIVIDE_BY" value="1" />
- <parameter name="CLK0_DUTY_CYCLE" value="50" />
- <parameter name="CLK0_MULTIPLY_BY" value="1" />
- <parameter name="CLK0_PHASE_SHIFT" value="0" />
- <parameter name="CLK1_DIVIDE_BY" value="1" />
- <parameter name="CLK1_DUTY_CYCLE" value="50" />
- <parameter name="CLK1_MULTIPLY_BY" value="1" />
- <parameter name="CLK1_PHASE_SHIFT" value="-3000" />
- <parameter name="CLK2_DIVIDE_BY" value="" />
- <parameter name="CLK2_DUTY_CYCLE" value="" />
- <parameter name="CLK2_MULTIPLY_BY" value="" />
- <parameter name="CLK2_PHASE_SHIFT" value="" />
- <parameter name="CLK3_DIVIDE_BY" value="" />
- <parameter name="CLK3_DUTY_CYCLE" value="" />
- <parameter name="CLK3_MULTIPLY_BY" value="" />
- <parameter name="CLK3_PHASE_SHIFT" value="" />
- <parameter name="CLK4_DIVIDE_BY" value="" />
- <parameter name="CLK4_DUTY_CYCLE" value="" />
- <parameter name="CLK4_MULTIPLY_BY" value="" />
- <parameter name="CLK4_PHASE_SHIFT" value="" />
- <parameter name="CLK5_DIVIDE_BY" value="" />
- <parameter name="CLK5_DUTY_CYCLE" value="" />
- <parameter name="CLK5_MULTIPLY_BY" value="" />
- <parameter name="CLK5_PHASE_SHIFT" value="" />
- <parameter name="CLK6_DIVIDE_BY" value="" />
- <parameter name="CLK6_DUTY_CYCLE" value="" />
- <parameter name="CLK6_MULTIPLY_BY" value="" />
- <parameter name="CLK6_PHASE_SHIFT" value="" />
- <parameter name="CLK7_DIVIDE_BY" value="" />
- <parameter name="CLK7_DUTY_CYCLE" value="" />
- <parameter name="CLK7_MULTIPLY_BY" value="" />
- <parameter name="CLK7_PHASE_SHIFT" value="" />
- <parameter name="CLK8_DIVIDE_BY" value="" />
- <parameter name="CLK8_DUTY_CYCLE" value="" />
- <parameter name="CLK8_MULTIPLY_BY" value="" />
- <parameter name="CLK8_PHASE_SHIFT" value="" />
- <parameter name="CLK9_DIVIDE_BY" value="" />
- <parameter name="CLK9_DUTY_CYCLE" value="" />
- <parameter name="CLK9_MULTIPLY_BY" value="" />
- <parameter name="CLK9_PHASE_SHIFT" value="" />
- <parameter name="COMPENSATE_CLOCK" value="CLK0" />
- <parameter name="DOWN_SPREAD" value="" />
- <parameter name="DPA_DIVIDER" value="" />
- <parameter name="DPA_DIVIDE_BY" value="" />
- <parameter name="DPA_MULTIPLY_BY" value="" />
- <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
- <parameter name="EXTCLK0_DIVIDE_BY" value="" />
- <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK1_DIVIDE_BY" value="" />
- <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK2_DIVIDE_BY" value="" />
- <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK3_DIVIDE_BY" value="" />
- <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
- <parameter name="FEEDBACK_SOURCE" value="" />
- <parameter name="GATE_LOCK_COUNTER" value="" />
- <parameter name="GATE_LOCK_SIGNAL" value="" />
- <parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -3000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED</parameter>
- <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
- <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
- <parameter name="HIDDEN_IF_PORTS">IF#phasecounterselect {input 4} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}</parameter>
- <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
- <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
- <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
- <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -3.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 ns PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1508019453416741.mif PT#ACTIVECLK_CHECK 0</parameter>
- <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
- <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
- <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
- <parameter name="INTENDED_DEVICE_FAMILY" value="Cyclone IV E" />
- <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
- <parameter name="LOCK_HIGH" value="" />
- <parameter name="LOCK_LOW" value="" />
- <parameter name="OPERATION_MODE" value="NORMAL" />
- <parameter name="PLL_TYPE" value="AUTO" />
- <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
- <parameter name="PORT_ARESET" value="PORT_UNUSED" />
- <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
- <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
- <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
- <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
- <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
- <parameter name="PORT_ENABLE0" value="" />
- <parameter name="PORT_ENABLE1" value="" />
- <parameter name="PORT_FBIN" value="PORT_UNUSED" />
- <parameter name="PORT_FBOUT" value="" />
- <parameter name="PORT_INCLK0" value="PORT_USED" />
- <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
- <parameter name="PORT_LOCKED" value="PORT_UNUSED" />
- <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
- <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
- <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
- <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
- <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
- <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
- <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
- <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
- <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
- <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
- <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
- <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
- <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
- <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
- <parameter name="PORT_SCLKOUT0" value="" />
- <parameter name="PORT_SCLKOUT1" value="" />
- <parameter name="PORT_VCOOVERRANGE" value="" />
- <parameter name="PORT_VCOUNDERRANGE" value="" />
- <parameter name="PORT_clk0" value="PORT_USED" />
- <parameter name="PORT_clk1" value="PORT_USED" />
- <parameter name="PORT_clk2" value="PORT_UNUSED" />
- <parameter name="PORT_clk3" value="PORT_UNUSED" />
- <parameter name="PORT_clk4" value="PORT_UNUSED" />
- <parameter name="PORT_clk5" value="PORT_UNUSED" />
- <parameter name="PORT_clk6" value="" />
- <parameter name="PORT_clk7" value="" />
- <parameter name="PORT_clk8" value="" />
- <parameter name="PORT_clk9" value="" />
- <parameter name="PORT_clkena0" value="PORT_UNUSED" />
- <parameter name="PORT_clkena1" value="PORT_UNUSED" />
- <parameter name="PORT_clkena2" value="PORT_UNUSED" />
- <parameter name="PORT_clkena3" value="PORT_UNUSED" />
- <parameter name="PORT_clkena4" value="PORT_UNUSED" />
- <parameter name="PORT_clkena5" value="PORT_UNUSED" />
- <parameter name="PORT_extclk0" value="PORT_UNUSED" />
- <parameter name="PORT_extclk1" value="PORT_UNUSED" />
- <parameter name="PORT_extclk2" value="PORT_UNUSED" />
- <parameter name="PORT_extclk3" value="PORT_UNUSED" />
- <parameter name="PORT_extclkena0" value="" />
- <parameter name="PORT_extclkena1" value="" />
- <parameter name="PORT_extclkena2" value="" />
- <parameter name="PORT_extclkena3" value="" />
- <parameter name="PRIMARY_CLOCK" value="" />
- <parameter name="QUALIFY_CONF_DONE" value="" />
- <parameter name="SCAN_CHAIN" value="" />
- <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
- <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
- <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
- <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
- <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
- <parameter name="SKIP_VCO" value="" />
- <parameter name="SPREAD_FREQUENCY" value="" />
- <parameter name="SWITCH_OVER_COUNTER" value="" />
- <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
- <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
- <parameter name="SWITCH_OVER_TYPE" value="" />
- <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
- <parameter name="VALID_LOCK_MULTIPLIER" value="" />
- <parameter name="VCO_DIVIDE_BY" value="" />
- <parameter name="VCO_FREQUENCY_CONTROL" value="" />
- <parameter name="VCO_MULTIPLY_BY" value="" />
- <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
- <parameter name="WIDTH_CLOCK" value="5" />
- <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ <module
+ name="sysid_main"
+ kind="altera_avalon_sysid_qsys"
+ version="17.1"
+ enabled="1">
+ <parameter name="id" value="1869837601" />
+ </module>
+ <module
+ name="sysid_usb"
+ kind="altera_avalon_sysid_qsys"
+ version="17.1"
+ enabled="1">
+ <parameter name="id" value="1970496033" />
</module>
- <module name="timer" kind="altera_avalon_timer" version="17.0" enabled="1">
+ <module name="timer" kind="altera_avalon_timer" version="17.1" enabled="1">
<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="fixedPeriod" value="false" />
@@ -639,79 +1552,268 @@
</module>
<connection
kind="avalon"
- version="17.0"
- start="proc_main.data_master"
- end="jtag_uart.avalon_jtag_slave">
+ version="17.1"
+ start="proc_main.data_master"
+ end="jtag_uart.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2090" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="jtag_uart.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2090" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_main.data_master"
+ end="sysid_main.control_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2080" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="sysid_usb.control_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2080" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_main.data_master"
+ end="flash.flash_data">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x20000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_main.data_master"
+ end="flash.flash_erase_control">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x20f00000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_main.data_master"
+ end="proc_main.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="proc_usb.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1800" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_main.data_master"
+ end="keyboard.key_events">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x5000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_main.data_master"
+ end="pll.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0030" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="otg_clock_crossing_bridge.s0">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x30000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_main.data_master"
+ end="timer.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0040" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="timer.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2090" />
+ <parameter name="baseAddress" value="0x0040" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
- end="osu_sysid.control_slave">
+ end="mouse_x_in.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x5110" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="mouse_x_out.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x5110" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="mouse_y_out.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2088" />
+ <parameter name="baseAddress" value="0x5120" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
- end="flash.flash_data">
+ end="mouse_y_in.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x5120" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="mouse_scroll_out.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x18000000" />
+ <parameter name="baseAddress" value="0x5130" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
- end="flash.flash_erase_control">
+ end="mouse_scroll_in.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x5130" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="mouse_btn_out.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x18400000" />
+ <parameter name="baseAddress" value="0x5140" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
- end="proc_main.jtag_debug_module">
+ end="mouse_btn_in.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x1800" />
+ <parameter name="baseAddress" value="0x5140" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
- end="keyboard.key_events">
+ end="pio_hex.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x5000" />
+ <parameter name="baseAddress" value="0x2100" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
- end="sdram_pll.pll_slave">
+ end="pio_ledr.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0030" />
+ <parameter name="baseAddress" value="0x2110" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
- end="ocm_null.s1">
+ end="pio_ledg.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
+ <parameter name="baseAddress" value="0x2120" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="otg_hpi_cs.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2200" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="otg_hpi_address.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2210" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="otg_hpi_data.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2220" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="otg_hpi_r.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2230" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="otg_hpi_w.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2240" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="sdram.s1">
<parameter name="arbitrationPriority" value="1" />
@@ -720,52 +1822,106 @@
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="sdram.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x10000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
start="proc_main.data_master"
- end="timer.s1">
+ end="ocm_null.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0040" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.data_master"
+ end="ocm_null.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
- end="osu_sysid.control_slave">
+ end="jtag_uart.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2090" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.instruction_master"
+ end="jtag_uart.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2088" />
+ <parameter name="baseAddress" value="0x2090" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
- end="flash.flash_data">
+ end="sysid_main.control_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2080" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.instruction_master"
+ end="sysid_usb.control_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x18000000" />
+ <parameter name="baseAddress" value="0x2080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
end="proc_main.jtag_debug_module">
<parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="proc_usb.instruction_master"
+ end="proc_usb.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x1800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
+ start="proc_usb.instruction_master"
+ end="sdram.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x10000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
start="proc_main.instruction_master"
- end="sdram_pll.pll_slave">
+ end="sdram.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0030" />
+ <parameter name="baseAddress" value="0x10000000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
end="ocm_null.s1">
<parameter name="arbitrationPriority" value="1" />
@@ -774,85 +1930,363 @@
</connection>
<connection
kind="avalon"
- version="17.0"
- start="proc_main.instruction_master"
- end="sdram.s1">
+ version="17.1"
+ start="proc_usb.instruction_master"
+ end="ocm_null.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x10000000" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="otg_clock_crossing_bridge.m0"
+ end="otg_hpi_w.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2240" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="otg_clock_crossing_bridge.m0"
+ end="otg_hpi_r.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2230" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="otg_clock_crossing_bridge.m0"
+ end="otg_hpi_data.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2220" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="otg_clock_crossing_bridge.m0"
+ end="otg_hpi_address.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2210" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="otg_clock_crossing_bridge.m0"
+ end="otg_hpi_cs.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2200" />
<parameter name="defaultConnection" value="false" />
</connection>
- <connection kind="clock" version="17.0" start="sdram_pll.c0" end="sdram.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="osu_sysid.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="proc_main.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="jtag_uart.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="timer.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="flash.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="ocm_null.clk1" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="keyboard.clock" />
+ <connection kind="clock" version="17.1" start="pll.c2" end="otg_hpi_cs.clk" />
+ <connection kind="clock" version="17.1" start="pll.c2" end="otg_hpi_address.clk" />
+ <connection kind="clock" version="17.1" start="pll.c2" end="otg_hpi_data.clk" />
+ <connection kind="clock" version="17.1" start="pll.c2" end="otg_hpi_r.clk" />
+ <connection kind="clock" version="17.1" start="pll.c2" end="otg_hpi_w.clk" />
+ <connection
+ kind="clock"
+ version="17.1"
+ start="pll.c2"
+ end="otg_clock_crossing_bridge.m0_clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="timer.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="flash.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="pio_hex.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="pio_ledr.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="pio_ledg.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="mouse_x_in.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="mouse_x_out.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="mouse_y_out.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="mouse_y_in.clk" />
+ <connection
+ kind="clock"
+ version="17.1"
+ start="clk_50.clk"
+ end="mouse_scroll_out.clk" />
+ <connection
+ kind="clock"
+ version="17.1"
+ start="clk_50.clk"
+ end="mouse_scroll_in.clk" />
+ <connection
+ kind="clock"
+ version="17.1"
+ start="clk_50.clk"
+ end="mouse_btn_out.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="mouse_btn_in.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="sdram.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="proc_usb.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="sysid_usb.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="jtag_uart.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="proc_main.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="sysid_main.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="ocm_null.clk1" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="keyboard.clock" />
+ <connection
+ kind="clock"
+ version="17.1"
+ start="clk_50.clk"
+ end="pll.inclk_interface" />
<connection
kind="clock"
- version="17.0"
+ version="17.1"
start="clk_50.clk"
- end="sdram_pll.inclk_interface" />
+ end="otg_clock_crossing_bridge.s0_clk" />
+ <connection
+ kind="conduit"
+ version="17.1"
+ start="mouse_x_out.external_connection"
+ end="mouse_x_in.external_connection">
+ <parameter name="endPort" value="" />
+ <parameter name="endPortLSB" value="0" />
+ <parameter name="startPort" value="" />
+ <parameter name="startPortLSB" value="0" />
+ <parameter name="width" value="0" />
+ </connection>
+ <connection
+ kind="conduit"
+ version="17.1"
+ start="mouse_y_out.external_connection"
+ end="mouse_y_in.external_connection">
+ <parameter name="endPort" value="" />
+ <parameter name="endPortLSB" value="0" />
+ <parameter name="startPort" value="" />
+ <parameter name="startPortLSB" value="0" />
+ <parameter name="width" value="0" />
+ </connection>
+ <connection
+ kind="conduit"
+ version="17.1"
+ start="mouse_scroll_in.external_connection"
+ end="mouse_scroll_out.external_connection">
+ <parameter name="endPort" value="" />
+ <parameter name="endPortLSB" value="0" />
+ <parameter name="startPort" value="" />
+ <parameter name="startPortLSB" value="0" />
+ <parameter name="width" value="0" />
+ </connection>
+ <connection
+ kind="conduit"
+ version="17.1"
+ start="mouse_btn_out.external_connection"
+ end="mouse_btn_in.external_connection">
+ <parameter name="endPort" value="" />
+ <parameter name="endPortLSB" value="0" />
+ <parameter name="startPort" value="" />
+ <parameter name="startPortLSB" value="0" />
+ <parameter name="width" value="0" />
+ </connection>
<connection
kind="interrupt"
- version="17.0"
- start="proc_main.d_irq"
+ version="17.1"
+ start="proc_usb.d_irq"
+ end="timer.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="17.1"
+ start="proc_usb.d_irq"
end="jtag_uart.irq">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
- version="17.0"
+ version="17.1"
start="proc_main.d_irq"
end="timer.irq">
<parameter name="irqNumber" value="1" />
</connection>
+ <connection
+ kind="interrupt"
+ version="17.1"
+ start="proc_main.d_irq"
+ end="jtag_uart.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
- end="sdram_pll.inclk_interface_reset" />
+ end="pll.inclk_interface_reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
- end="sdram.reset" />
+ end="otg_clock_crossing_bridge.m0_reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
- end="osu_sysid.reset" />
+ end="sdram.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
- end="jtag_uart.reset" />
+ end="timer.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
- end="timer.reset" />
+ end="keyboard.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="flash.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
- end="keyboard.reset" />
+ end="pio_hex.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="pio_ledr.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="pio_ledg.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="mouse_x_in.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="mouse_y_out.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="mouse_y_in.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="mouse_scroll_out.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="mouse_scroll_in.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="mouse_btn_out.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="mouse_btn_in.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="otg_hpi_cs.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="otg_hpi_address.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="otg_hpi_data.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="otg_hpi_r.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="otg_hpi_w.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="mouse_x_out.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="sysid_usb.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="jtag_uart.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="sysid_main.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="ocm_null.reset1" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="proc_usb.reset_n" />
+ <connection
+ kind="reset"
+ version="17.1"
start="clk_50.clk_reset"
end="proc_main.reset_n" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="otg_clock_crossing_bridge.s0_reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="proc_usb.jtag_debug_module_reset"
+ end="otg_clock_crossing_bridge.m0_reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="proc_usb.jtag_debug_module_reset"
+ end="otg_hpi_w.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="proc_usb.jtag_debug_module_reset"
+ end="otg_hpi_r.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="proc_usb.jtag_debug_module_reset"
+ end="otg_hpi_data.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="proc_usb.jtag_debug_module_reset"
+ end="otg_hpi_address.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="proc_usb.jtag_debug_module_reset"
+ end="otg_hpi_cs.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="proc_usb.jtag_debug_module_reset"
+ end="otg_clock_crossing_bridge.s0_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/software/osu_main/.cproject b/software/osu_main/.cproject
index 745f9bc7f730c10066ff75b73856d6195f86b021..60ab71ea6f74e27b4ed2639307398ffaba4faa15 100644
--- a/software/osu_main/.cproject
+++ b/software/osu_main/.cproject
@@ -1,32 +1,32 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
- <buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065">
- <storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065" moduleId="org.eclipse.cdt.core.settings"/>
+ <buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195">
+ <storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195" moduleId="org.eclipse.cdt.core.settings"/>
</buildSystem>
- <cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065">
+ <cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195">
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
- <folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065." name="/" resourcePath="">
- <toolChain id="altera.nios2.mingw.gcc4.1695715586" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
- <targetPlatform id="altera.nios2.mingw.gcc4.2130013499" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
- <builder buildPath="${workspace_loc://osu_main}" id="altera.tool.gnu.builder.mingw.1243813729" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
- <tool id="altera.tool.gnu.c.compiler.mingw.1512907719" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
- <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1040711810" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ <configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195." name="/" resourcePath="">
+ <toolChain id="altera.nios2.mingw.gcc4.351469300" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
+ <targetPlatform id="altera.nios2.mingw.gcc4.26023271" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
+ <builder buildPath="${workspace_loc://osu_main}" id="altera.tool.gnu.builder.mingw.45764510" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
+ <tool id="altera.tool.gnu.c.compiler.mingw.1227833858" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.240421295" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
- <tool id="altera.tool.gnu.cpp.compiler.mingw.1573963372" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
- <inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.232317194" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+ <tool id="altera.tool.gnu.cpp.compiler.mingw.1606977472" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.372136993" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool>
- <tool id="altera.tool.gnu.archiver.mingw.1684988338" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
- <tool id="altera.tool.gnu.c.linker.mingw.1482049235" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
- <tool id="altera.tool.gnu.assembler.mingw.1402728829" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
- <inputType id="cdt.managedbuild.tool.gnu.assembler.input.422854114" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ <tool id="altera.tool.gnu.archiver.mingw.1316883666" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
+ <tool id="altera.tool.gnu.c.linker.mingw.1006047636" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
+ <tool id="altera.tool.gnu.assembler.mingw.1720644171" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.736097008" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
</tool>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -45,10 +45,10 @@
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065.;altera.tool.gnu.cpp.compiler.mingw.1573963372;cdt.managedbuild.tool.gnu.cpp.compiler.input.232317194">
+ <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195.;altera.tool.gnu.cpp.compiler.mingw.1606977472;cdt.managedbuild.tool.gnu.cpp.compiler.input.372136993">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065.;altera.tool.gnu.c.compiler.mingw.1512907719;cdt.managedbuild.tool.gnu.c.compiler.input.1040711810">
+ <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1776890195.;altera.tool.gnu.c.compiler.mingw.1227833858;cdt.managedbuild.tool.gnu.c.compiler.input.240421295">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
diff --git a/software/osu_main/Makefile b/software/osu_main/Makefile
index 472b0189bd2c8ba3037f630b44a747250162c7de..24d9434ac9d06bc97af7fe54e97a72c2e28563e2 100644
--- a/software/osu_main/Makefile
+++ b/software/osu_main/Makefile
@@ -129,12 +129,12 @@ BUILD_CONFIGS := default
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
-# ACDS_VERSION: 17.0
-ACDS_VERSION := 17.0
+# ACDS_VERSION: 17.1
+ACDS_VERSION := 17.1
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
-# BUILD_NUMBER: 595
+# BUILD_NUMBER: 590
# Define path to the application ELF.
# It may be used by the makefile fragments so is defined before including them.
@@ -152,7 +152,7 @@ OBJ_ROOT_DIR := obj
# Options to control objdump.
CREATE_OBJDUMP := 1
-OBJDUMP_INCLUDE_SOURCE := 1
+OBJDUMP_INCLUDE_SOURCE := 0
OBJDUMP_FULL_CONTENTS := 0
# Options to enable/disable optional files.
@@ -177,7 +177,7 @@ CRT0 :=
SYS_LIB :=
# Define path to the root of the BSP.
-BSP_ROOT_DIR := ../otofpga_main_bsp/
+BSP_ROOT_DIR := ../proc_main_bsp/
# List of application specific include directories, library directories and library names
APP_INCLUDE_DIRS :=
@@ -188,7 +188,6 @@ APP_LIBRARY_NAMES :=
BUILD_PRE_PROCESS :=
BUILD_POST_PROCESS :=
-QUARTUS_PROJECT_DIR := ../../
#END GENERATED
diff --git a/software/osu_main/create-this-app b/software/osu_main/create-this-app
deleted file mode 100644
index 4e1d5e0c1b6a31a836ecfdcb2603d9cdb64b0810..0000000000000000000000000000000000000000
--- a/software/osu_main/create-this-app
+++ /dev/null
@@ -1,114 +0,0 @@
-#!/bin/bash
-#
-# This script creates the blank_project application in this directory.
-
-
-BSP_DIR=../otofpga_main_bsp
-QUARTUS_PROJECT_DIR=../../
-NIOS2_APP_GEN_ARGS="--elf-name osu_main.elf --no-src --set OBJDUMP_INCLUDE_SOURCE 1"
-
-
-# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set.
-# This variable is required for the command line tools to execute correctly.
-if [ -z "${SOPC_KIT_NIOS2}" ]
-then
- echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set!
- exit 1
-fi
-
-
-# Also make sure that the APP has not been created already. Check for
-# existence of Makefile in the app directory
-if [ -f ./Makefile ]
-then
- echo Application has already been created! Delete Makefile if you want to create a new application makefile
- exit 1
-fi
-
-
-# We are selecting hal_default bsp because it supports this application.
-# Check to see if the hal_default has already been generated by checking for
-# existence of the public.mk file. If not, we need to run
-# create-this-bsp file to generate the bsp.
-if [ ! -f ${BSP_DIR}/public.mk ]; then
- # Since BSP doesn't exist, create the BSP
- # Pass any command line arguments passed to this script to the BSP.
- pushd ${BSP_DIR} >> /dev/null
- ./create-this-bsp "$@" || {
- echo "create-this-bsp failed"
- exit 1
- }
- popd >> /dev/null
-fi
-
-
-# Don't run make if create-this-app script is called with --no-make arg
-SKIP_MAKE=
-while [ $# -gt 0 ]
-do
- case "$1" in
- --no-make)
- SKIP_MAKE=1
- ;;
- esac
- shift
-done
-
-
-# Now we also need to go copy the sources for this application to the
-# local directory.
-find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || {
- echo "failed during copying example source files"
- exit 1
-}
-
-find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || {
- echo "failed copying readme file"
-}
-
-if [ -d "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" ]
-then
- cp -RL "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" . || {
- echo "failed during copying project support files"
- exit 1
- }
-fi
-
-chmod -R +w . || {
- echo "failed during changing file permissions"
- exit 1
-}
-
-cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}"
-
-echo "create-this-app: Running \"${cmd}\""
-$cmd || {
- echo "nios2-app-generate-makefile failed"
- exit 1
-}
-
-if [ -z "$SKIP_MAKE" ]; then
- cmd="make"
-
- echo "create-this-app: Running \"$cmd\""
- $cmd || {
- echo "make failed"
- exit 1
- }
-
- echo
- echo "To download and run the application:"
- echo " 1. Make sure the board is connected to the system."
- echo " 2. Run 'nios2-configure-sof <SOF_FILE_PATH>' to configure the FPGA with the hardware design."
- echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell."
- echo " 4. Run 'make download-elf' from the application directory."
- echo
- echo "To debug the application:"
- echo " Import the project into Nios II Software Build Tools for Eclipse."
- echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information."
- echo
- echo -e ""
-fi
-
-
-exit 0
diff --git a/software/osu_main/readme.txt b/software/osu_main/readme.txt
deleted file mode 100644
index 57f6738b0b6536b3a08e6855442fe02dbf19d94a..0000000000000000000000000000000000000000
--- a/software/osu_main/readme.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-This template is starting point for creating a project based on your custom C code.
-It will provide you a default project to which you can add your software files. To
-add files to a project, manually copy the file into the application directory (e.g.
-using Windows Explorer), then right click on your application project and select
-refresh.
-
-You can also add files to the project using the Nios II Software Build Tools for Eclipse import function.
-Select File -> Import.
-Expand General and select File System in the Import Window and click Next.
-Identify the appropriate source and destination directories.
-Check the files you want to add and click Finish.
diff --git a/software/usb/.cproject b/software/usb/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..03862f211d1a54f7f2338524a461c51cc5f22cab
--- /dev/null
+++ b/software/usb/.cproject
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521">
+ <storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521" moduleId="org.eclipse.cdt.core.settings"/>
+ </buildSystem>
+ <cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521">
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521." name="/" resourcePath="">
+ <toolChain id="altera.nios2.mingw.gcc4.1031452200" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
+ <targetPlatform id="altera.nios2.mingw.gcc4.1988300270" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
+ <builder buildPath="${workspace_loc://usb}" id="altera.tool.gnu.builder.mingw.1474740644" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
+ <tool id="altera.tool.gnu.c.compiler.mingw.315425200" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.478849116" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ </tool>
+ <tool id="altera.tool.gnu.cpp.compiler.mingw.698791399" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1958547914" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+ </tool>
+ <tool id="altera.tool.gnu.archiver.mingw.791354557" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
+ <tool id="altera.tool.gnu.c.linker.mingw.334312366" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
+ <tool id="altera.tool.gnu.assembler.mingw.312261571" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.2113592241" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="usb.null.1123325621" name="usb"/>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521.;altera.tool.gnu.cpp.compiler.mingw.698791399;cdt.managedbuild.tool.gnu.cpp.compiler.input.1958547914">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.380090521.;altera.tool.gnu.c.compiler.mingw.315425200;cdt.managedbuild.tool.gnu.c.compiler.input.478849116">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
+ <buildTargets>
+ <target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>mem_init_install</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>false</useDefaultCommand>
+ <runAllBuilders>false</runAllBuilders>
+ </target>
+ <target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>mem_init_generate</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>false</useDefaultCommand>
+ <runAllBuilders>false</runAllBuilders>
+ </target>
+ <target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>help</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>false</useDefaultCommand>
+ <runAllBuilders>false</runAllBuilders>
+ </target>
+ </buildTargets>
+ </storageModule>
+</cproject>
diff --git a/software/usb/.project b/software/usb/.project
new file mode 100644
index 0000000000000000000000000000000000000000..bb655aac79c21916ed1b7153a99167c6e699594e
--- /dev/null
+++ b/software/usb/.project
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>usb</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>com.altera.sbtgui.project.makefileBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>com.altera.sbtgui.project.makefileBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>com.altera.sbtgui.project.SBTGUINature</nature>
+ <nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
+ <nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
+ </natures>
+</projectDescription>
diff --git a/software/usb/Makefile b/software/usb/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..fcf5ba3c31035825314c2d3c7ed5d575d4971c73
--- /dev/null
+++ b/software/usb/Makefile
@@ -0,0 +1,1083 @@
+#------------------------------------------------------------------------------
+# VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS
+#------------------------------------------------------------------------------
+
+# List of include directories for -I compiler option (-I added when used).
+# Includes the BSP.
+ALT_INCLUDE_DIRS :=
+
+# List of library directories for -L linker option (-L added when used).
+# Includes the BSP.
+ALT_LIBRARY_DIRS :=
+
+# List of library names for -l linker option (-l added when used).
+# Includes the BSP.
+ALT_LIBRARY_NAMES :=
+
+# List of library names for -msys-lib linker option (-msys-lib added when used).
+# These are libraries that might be located in the BSP and depend on the BSP
+# library, or vice versa
+ALT_BSP_DEP_LIBRARY_NAMES :=
+
+# List of dependencies for the linker. This is usually the full pathname
+# of each library (*.a) file.
+# Includes the BSP.
+ALT_LDDEPS :=
+
+# List of root library directories that support running make to build them.
+# Includes the BSP and any ALT libraries.
+MAKEABLE_LIBRARY_ROOT_DIRS :=
+
+# Generic flags passed to the compiler for different types of input files.
+ALT_CFLAGS :=
+ALT_CXXFLAGS :=
+ALT_CPPFLAGS :=
+ALT_ASFLAGS :=
+ALT_LDFLAGS :=
+
+
+#------------------------------------------------------------------------------
+# The adjust-path macro
+#
+# If COMSPEC/ComSpec is defined, Make is launched from Windows through
+# Cygwin. The adjust-path macro converts absolute windows paths into
+# unix style paths (Example: c:/dir -> /c/dir). This will ensture
+# paths are readable by GNU Make.
+#
+# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no
+# adjustment is necessary
+#
+#------------------------------------------------------------------------------
+
+ifndef COMSPEC
+ifdef ComSpec
+COMSPEC = $(ComSpec)
+endif # ComSpec
+endif # COMSPEC
+
+ifdef COMSPEC # if Windows OS
+
+ifeq ($(MAKE_VERSION),3.81)
+#
+# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows
+#
+# Example Usage:
+# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb
+# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb
+# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb
+#
+
+#
+# adjust-path
+# - converts back slash characters into forward slashes
+# - if input arg ($1) is an empty string then return the empty string
+# - if input arg ($1) does not contain the string ":/", then return input arg
+# - using sed, convert mixed path [c:/...] into mingw path [/c/...]
+define adjust-path
+$(strip \
+$(if $1,\
+$(if $(findstring :/,$(subst \,/,$1)),\
+$(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\
+$(subst \,/,$1))))
+endef
+
+#
+# adjust-path-mixed
+# - converts back slash characters into forward slashes
+# - if input arg ($1) is an empty string then return the empty string
+# - if input arg ($1) does not begin with a forward slash '/' char, then
+# return input arg
+# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...]
+# into a mixed path [c:/...]
+define adjust-path-mixed
+$(strip \
+$(if $1,\
+$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\
+$(subst \,/,$1),\
+$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,'))))
+endef
+
+else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79)
+#
+# adjust-path for Cygwin Gnu Make
+# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb
+# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb
+#
+adjust-path = $(if $1,$(shell cygpath -u "$1"),)
+adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),)
+endif
+
+else # !COMSPEC
+
+adjust-path = $1
+adjust-path-mixed = $1
+
+endif # COMSPEC
+
+
+#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
+# GENERATED SETTINGS START v
+#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
+
+#START GENERATED
+ACTIVE_BUILD_CONFIG := default
+BUILD_CONFIGS := default
+
+# The following TYPE comment allows tools to identify the 'type' of target this
+# makefile is associated with.
+# TYPE: APP_MAKEFILE
+
+# This following VERSION comment indicates the version of the tool used to
+# generate this makefile. A makefile variable is provided for VERSION as well.
+# ACDS_VERSION: 17.1
+ACDS_VERSION := 17.1
+
+# This following BUILD_NUMBER comment indicates the build number of the tool
+# used to generate this makefile.
+# BUILD_NUMBER: 590
+
+# Define path to the application ELF.
+# It may be used by the makefile fragments so is defined before including them.
+#
+ELF := usb.elf
+
+# Paths to C, C++, and assembly source files.
+C_SRCS += src/io_handler.c
+C_SRCS += src/main.c
+C_SRCS += src/usb.c
+CXX_SRCS :=
+ASM_SRCS :=
+
+
+# Path to root of object file tree.
+OBJ_ROOT_DIR := obj
+
+# Options to control objdump.
+CREATE_OBJDUMP := 1
+OBJDUMP_INCLUDE_SOURCE := 0
+OBJDUMP_FULL_CONTENTS := 0
+
+# Options to enable/disable optional files.
+CREATE_ELF_DERIVED_FILES := 0
+CREATE_LINKER_MAP := 1
+
+# Common arguments for ALT_CFLAGSs
+APP_CFLAGS_DEFINED_SYMBOLS :=
+APP_CFLAGS_UNDEFINED_SYMBOLS :=
+APP_CFLAGS_OPTIMIZATION := -O0
+APP_CFLAGS_DEBUG_LEVEL := -g
+APP_CFLAGS_WARNINGS := -Wall
+APP_CFLAGS_USER_FLAGS :=
+
+APP_ASFLAGS_USER :=
+APP_LDFLAGS_USER :=
+
+# Linker options that have default values assigned later if not
+# assigned here.
+LINKER_SCRIPT :=
+CRT0 :=
+SYS_LIB :=
+
+# Define path to the root of the BSP.
+BSP_ROOT_DIR := ../proc_usb_bsp/
+
+# List of application specific include directories, library directories and library names
+APP_INCLUDE_DIRS :=
+APP_LIBRARY_DIRS :=
+APP_LIBRARY_NAMES :=
+
+# Pre- and post- processor settings.
+BUILD_PRE_PROCESS :=
+BUILD_POST_PROCESS :=
+
+
+
+#END GENERATED
+
+#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+# GENERATED SETTINGS END ^
+#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+
+#------------------------------------------------------------------------------
+# DEFAULT TARGET
+#------------------------------------------------------------------------------
+
+# Define the variable used to echo output if not already defined.
+ifeq ($(ECHO),)
+ECHO := echo
+endif
+
+# Put "all" rule before included makefile fragments because they may
+# define rules and we don't want one of those to become the default rule.
+.PHONY : all
+
+all:
+ @$(ECHO) [$(APP_NAME) build complete]
+
+all : build_pre_process libs app build_post_process
+
+
+#------------------------------------------------------------------------------
+# VARIABLES DEPENDENT ON GENERATED CONTENT
+#------------------------------------------------------------------------------
+
+# Define object file directory per build configuration
+CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG)
+
+ifeq ($(BSP_ROOT_DIR),)
+$(error Edit Makefile and provide a value for BSP_ROOT_DIR)
+endif
+
+ifeq ($(wildcard $(BSP_ROOT_DIR)),)
+$(error BSP directory does not exist: $(BSP_ROOT_DIR))
+endif
+
+# Define absolute path to the root of the BSP.
+ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd))
+
+# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before
+# including each makefile fragment so that it knows the path to itself.
+BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk
+ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR)
+include $(BSP_INCLUDE_FILE)
+# C2H will need this to touch the BSP public.mk and avoid the sopc file
+# out-of-date error during a BSP make
+ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk
+
+
+ifneq ($(WARNING.SMALL_STACK_SIZE),)
+# This WARNING is here to protect you from unknowingly using a very small stack
+# If the warning is set, increase your stack size or enable the BSP small stack
+# setting to eliminate the warning
+$(warning WARNING: $(WARNING.SMALL_STACK_SIZE))
+endif
+
+# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF
+# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_.
+ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),)
+ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF)
+endif
+
+# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to
+# download_elf target
+ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),)
+GMON_OUT_FILENAME := gmon.out
+WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME)
+endif
+
+# Name of ELF application.
+APP_NAME := $(basename $(ELF))
+
+# Set to defaults if variables not already defined in settings.
+ifeq ($(LINKER_SCRIPT),)
+LINKER_SCRIPT := $(BSP_LINKER_SCRIPT)
+endif
+ifeq ($(CRT0),)
+CRT0 := $(BSP_CRT0)
+endif
+ifeq ($(SYS_LIB),)
+SYS_LIB := $(BSP_SYS_LIB)
+endif
+
+OBJDUMP_NAME := $(APP_NAME).objdump
+OBJDUMP_FLAGS := --disassemble --syms --all-header
+ifeq ($(OBJDUMP_INCLUDE_SOURCE),1)
+OBJDUMP_FLAGS += --source
+endif
+ifeq ($(OBJDUMP_FULL_CONTENTS),1)
+OBJDUMP_FLAGS += --full-contents
+endif
+
+# Create list of linker dependencies (*.a files).
+APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS)
+
+# Take lists and add required prefixes.
+APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
+ASM_INC_PREFIX := -Wa,-I
+APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
+APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS))
+APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS))
+
+ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
+
+#
+# Avoid Nios II GCC 3.X options.
+#
+
+# Detect if small newlib C library is requested.
+# If yes, remove the -msmallc option because it is
+# now handled by other means.
+ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),)
+ ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS))
+ ALT_C_LIBRARY := smallc
+else
+ ALT_C_LIBRARY := c
+endif
+
+# Put each BSP dependent library in a group to avoid circular dependencies.
+APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -lm -l$(l) -Wl,--end-group)
+
+else # !AVOID_NIOS2_GCC3_OPTIONS
+
+#
+# Use Nios II GCC 3.X options.
+#
+ALT_BSP_DEP_LIBRARY_NAMES += $(ALT_BSP_DEP_LIBRARY_NAMES) m
+APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES))
+
+endif # !AVOID_NIOS2_GCC3_OPTIONS
+
+# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker.
+APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \
+ $(APP_CFLAGS_UNDEFINED_SYMBOLS) \
+ $(APP_CFLAGS_OPTIMIZATION) \
+ $(APP_CFLAGS_DEBUG_LEVEL) \
+ $(APP_CFLAGS_WARNINGS) \
+ $(APP_CFLAGS_USER_FLAGS) \
+ $(ALT_CFLAGS) \
+ $(CFLAGS)
+
+# Arguments only for the C++ compiler.
+APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS)
+
+# Arguments only for the C preprocessor.
+# Prefix each include directory with -I.
+APP_CPPFLAGS := $(APP_INC_DIRS) \
+ $(ALT_CPPFLAGS) \
+ $(CPPFLAGS)
+
+# Arguments only for the assembler.
+APP_ASFLAGS := $(APP_ASM_INC_DIRS) \
+ $(ALT_ASFLAGS) \
+ $(APP_ASFLAGS_USER) \
+ $(ASFLAGS)
+
+# Arguments only for the linker.
+APP_LDFLAGS := $(APP_LDFLAGS_USER)
+
+ifneq ($(LINKER_SCRIPT),)
+APP_LDFLAGS += -T'$(LINKER_SCRIPT)'
+endif
+
+ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
+
+# Avoid Nios II GCC 3.x options.
+ifneq ($(CRT0),)
+APP_LDFLAGS += $(CRT0)
+endif
+
+# The equivalent of the -msys-lib option is provided
+# by the GROUP() command in the linker script.
+# Note this means the SYS_LIB variable is now ignored.
+
+else # !AVOID_NIOS2_GCC3_OPTIONS
+
+# Use Nios II GCC 3.x options.
+ifneq ($(CRT0),)
+APP_LDFLAGS += -msys-crt0='$(CRT0)'
+endif
+ifneq ($(SYS_LIB),)
+APP_LDFLAGS += -msys-lib=$(SYS_LIB)
+endif
+
+endif # !AVOID_NIOS2_GCC3_OPTIONS
+
+APP_LDFLAGS += \
+ $(APP_LIB_DIRS) \
+ $(ALT_LDFLAGS) \
+ $(LDFLAGS)
+
+LINKER_MAP_NAME := $(APP_NAME).map
+ifeq ($(CREATE_LINKER_MAP), 1)
+APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME)
+endif
+
+# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the
+# mem_init_install target of the mem_init.mk (located in the associated BSP)
+# to know how to copy memory initialization files (e.g. .dat, .hex) into
+# directories required for Quartus compilation or RTL simulation.
+
+# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory
+# initialization files into your Quartus project directory. This is required
+# to provide the initial memory contents of FPGA memories that can be
+# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used
+# for VHDL simulation of on-chip memories.
+
+# Defining SOPC_NAME causes the mem_init_install target to copy memory
+# initialization files into your RTL simulation directory. This is required
+# to provide the initial memory contents of all memories that can be
+# initialized by RTL simulation. This variable should be set to the same name
+# as your SOPC Builder system name. For example, if you have a system called
+# "foo.sopc", this variable should be set to "foo".
+
+# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME.
+ifeq ($(SOPC_NAME),)
+ifneq ($(QUARTUS_PROJECT_DIR),)
+SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo)))
+endif
+endif
+
+# Defining JDI_FILE is required to specify the JTAG Debug Information File
+# path. This file is generated by Quartus, and is needed along with the
+# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU
+# systems. For multi-CPU systems, the processor instance ID is used to select
+# from multiple CPU's during ELF download.
+
+# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during
+# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then
+# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be
+# multiple .sopcinfo files in a Quartus project.
+ifeq ($(JDI_FILE),)
+ifneq ($(QUARTUS_PROJECT_DIR),)
+JDI_FILE := $(firstword $(wildcard $(QUARTUS_PROJECT_DIR)/output_files/*.jdi) $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi))
+endif
+endif
+
+# Path to root runtime directory used for hdl simulation
+RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime
+
+
+
+#------------------------------------------------------------------------------
+# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT
+#------------------------------------------------------------------------------
+# mem_init.mk is a generated makefile fragment. This file defines all targets
+# used to generate HDL initialization simulation files and pre-initialized
+# onchip memory files.
+MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk
+include $(MEM_INIT_FILE)
+
+# Create list of object files to be built using the list of source files.
+# The source file hierarchy is preserved in the object tree.
+# The supported file extensions are:
+#
+# .c - for C files
+# .cxx .cc .cpp - for C++ files
+# .S .s - for assembler files
+#
+# Handle source files specified by --src-dir & --src-rdir differently, to
+# save some processing time in calling the adjust-path macro.
+
+OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS)))
+OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS)))
+OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS)))
+OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS)))
+OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS)))
+OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS)))
+
+OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \
+ $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS))
+
+SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS)))
+SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS)))
+SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS)))
+
+SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \
+ $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \
+ $(SDIR_OBJ_LIST_SS))
+
+# Relative-pathed objects that being with "../" are handled differently.
+#
+# Regular objects are created as
+# $(CONFIG_OBJ_DIR)/<path>/<filename>.o
+# where the path structure is maintained under the obj directory. This
+# applies for both absolute and relative paths; in the absolute path
+# case this means the entire source path will be recreated under the obj
+# directory. This is done to allow two source files with the same name
+# to be included as part of the project.
+#
+# Note: On Cygwin, the path recreated under the obj directory will be
+# the cygpath -u output path.
+#
+# Relative-path objects that begin with "../" cause problems under this
+# scheme, as $(CONFIG_OBJ_DIR)/../<rest of path>/ can potentially put the object
+# files anywhere in the system, creating clutter and polluting the source tree.
+# As such, their paths are flattened - the object file created will be
+# $(CONFIG_OBJ_DIR)/<filename>.o. Due to this, two files specified with
+# "../" in the beginning cannot have the same name in the project. VPATH
+# will be set for these sources to allow make to relocate the source file
+# via %.o rules.
+#
+# The following lines separate the object list into the flatten and regular
+# lists, and then handles them as appropriate.
+
+FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST))
+FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST)))
+
+REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST))
+REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST))
+
+FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST))
+FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST)))
+
+REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST))
+
+VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST)))
+
+APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_C) \
+ $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s)))
+
+APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_CPP) \
+ $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s)))
+
+APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_CXX) \
+ $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s)))
+
+APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_CC) \
+ $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s)))
+
+APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_S) \
+ $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s)))
+
+APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_SS) \
+ $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s)))
+
+APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \
+ $(APP_OBJS_S) $(APP_OBJS_SS) \
+ $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS)
+
+# Add any extra user-provided object files.
+APP_OBJS += $(OBJS)
+
+# Create list of dependancy files for each object file.
+APP_DEPS := $(APP_OBJS:.o=.d)
+
+# Patch the Elf file with system specific information
+
+# Patch the Elf with the name of the sopc system
+ifneq ($(SOPC_NAME),)
+ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME)
+endif
+
+# Patch the Elf with the absolute path to the Quartus Project Directory
+ifneq ($(QUARTUS_PROJECT_DIR),)
+ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd))
+ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)"
+endif
+
+# Patch the Elf and download args with the JDI_FILE if specified
+ifneq ($(wildcard $(JDI_FILE)),)
+ELF_PATCH_FLAG += --jdi $(JDI_FILE)
+DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE)
+endif
+
+# Patch the Elf with the SOPCINFO_FILE if specified
+ifneq ($(wildcard $(SOPCINFO_FILE)),)
+ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE)
+endif
+
+# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use.
+# This is not needed if you only have one cable.
+ifneq ($(DOWNLOAD_CABLE),)
+DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)'
+endif
+
+
+#------------------------------------------------------------------------------
+# BUILD PRE/POST PROCESS
+#------------------------------------------------------------------------------
+build_pre_process :
+ $(BUILD_PRE_PROCESS)
+
+build_post_process :
+ $(BUILD_POST_PROCESS)
+
+.PHONY: build_pre_process build_post_process
+
+
+#------------------------------------------------------------------------------
+# TOOLS
+#------------------------------------------------------------------------------
+
+#
+# Set tool default variables if not already defined.
+# If these are defined, they would typically be defined in an
+# included makefile fragment.
+#
+ifeq ($(DEFAULT_CROSS_COMPILE),)
+DEFAULT_CROSS_COMPILE := nios2-elf-
+endif
+
+ifeq ($(DEFAULT_STACKREPORT),)
+DEFAULT_STACKREPORT := nios2-stackreport
+endif
+
+ifeq ($(DEFAULT_DOWNLOAD),)
+DEFAULT_DOWNLOAD := nios2-download
+endif
+
+ifeq ($(DEFAULT_FLASHPROG),)
+DEFAULT_FLASHPROG := nios2-flash-programmer
+endif
+
+ifeq ($(DEFAULT_ELFPATCH),)
+DEFAULT_ELFPATCH := nios2-elf-insert
+endif
+
+ifeq ($(DEFAULT_RM),)
+DEFAULT_RM := rm -f
+endif
+
+ifeq ($(DEFAULT_CP),)
+DEFAULT_CP := cp -f
+endif
+
+ifeq ($(DEFAULT_MKDIR),)
+DEFAULT_MKDIR := mkdir -p
+endif
+
+#
+# Set tool variables to defaults if not already defined.
+# If these are defined, they would typically be defined by a
+# setting in the generated portion of this makefile.
+#
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE)
+endif
+
+ifeq ($(origin CC),default)
+CC := $(CROSS_COMPILE)gcc -xc
+endif
+
+ifeq ($(origin CXX),default)
+CXX := $(CROSS_COMPILE)gcc -xc++
+endif
+
+ifeq ($(origin AS),default)
+AS := $(CROSS_COMPILE)gcc
+endif
+
+ifeq ($(origin AR),default)
+AR := $(CROSS_COMPILE)ar
+endif
+
+ifeq ($(origin LD),default)
+LD := $(CROSS_COMPILE)g++
+endif
+
+ifeq ($(origin RM),default)
+RM := $(DEFAULT_RM)
+endif
+
+ifeq ($(NM),)
+NM := $(CROSS_COMPILE)nm
+endif
+
+ifeq ($(CP),)
+CP := $(DEFAULT_CP)
+endif
+
+ifeq ($(OBJDUMP),)
+OBJDUMP := $(CROSS_COMPILE)objdump
+endif
+
+ifeq ($(OBJCOPY),)
+OBJCOPY := $(CROSS_COMPILE)objcopy
+endif
+
+ifeq ($(STACKREPORT),)
+STACKREPORT := $(DEFAULT_STACKREPORT) --prefix $(CROSS_COMPILE)
+else
+DISABLE_STACKREPORT := 1
+endif
+
+ifeq ($(DOWNLOAD),)
+DOWNLOAD := $(DEFAULT_DOWNLOAD)
+endif
+
+ifeq ($(FLASHPROG),)
+FLASHPROG := $(DEFAULT_FLASHPROG)
+endif
+
+ifeq ($(ELFPATCH),)
+ELFPATCH := $(DEFAULT_ELFPATCH)
+endif
+
+ifeq ($(MKDIR),)
+MKDIR := $(DEFAULT_MKDIR)
+endif
+
+#------------------------------------------------------------------------------
+# PATTERN RULES TO BUILD OBJECTS
+#------------------------------------------------------------------------------
+
+define compile.c
+@$(ECHO) Info: Compiling $< to $@
+@$(MKDIR) $(@D)
+$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+$(CC_POST_PROCESS)
+endef
+
+define compile.cpp
+@$(ECHO) Info: Compiling $< to $@
+@$(MKDIR) $(@D)
+$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+$(CXX_POST_PROCESS)
+endef
+
+# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS
+ifeq ($(AS),$(patsubst %as,%,$(AS)))
+COMMA := ,
+APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS))))
+endif
+
+define compile.s
+@$(ECHO) Info: Assembling $< to $@
+@$(MKDIR) $(@D)
+$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $<
+$(AS_POST_PROCESS)
+endef
+
+ifeq ($(MAKE_VERSION),3.81)
+.SECONDEXPANSION:
+
+$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c)
+ $(compile.c)
+
+$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp)
+ $(compile.cpp)
+
+$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc)
+ $(compile.cpp)
+
+$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx)
+ $(compile.cpp)
+
+$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S)
+ $(compile.s)
+
+$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s)
+ $(compile.s)
+
+endif # MAKE_VERSION != 3.81
+
+$(CONFIG_OBJ_DIR)/%.o: %.c
+ $(compile.c)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cpp
+ $(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cc
+ $(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cxx
+ $(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.S
+ $(compile.s)
+
+$(CONFIG_OBJ_DIR)/%.o: %.s
+ $(compile.s)
+
+
+#------------------------------------------------------------------------------
+# PATTERN RULES TO INTERMEDIATE FILES
+#------------------------------------------------------------------------------
+
+$(CONFIG_OBJ_DIR)/%.s: %.c
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cpp
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cc
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cxx
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.c
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cpp
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cc
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cxx
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+
+#------------------------------------------------------------------------------
+# TARGET RULES
+#------------------------------------------------------------------------------
+
+.PHONY : help
+help :
+ @$(ECHO) "Summary of Makefile targets"
+ @$(ECHO) " Build targets:"
+ @$(ECHO) " all (default) - Application and all libraries (including BSP)"
+ @$(ECHO) " bsp - Just the BSP"
+ @$(ECHO) " libs - All libraries (including BSP)"
+ @$(ECHO) " flash - All flash files"
+ @$(ECHO) " mem_init_generate - All memory initialization files"
+ @$(ECHO)
+ @$(ECHO) " Clean targets:"
+ @$(ECHO) " clean_all - Application and all libraries (including BSP)"
+ @$(ECHO) " clean - Just the application"
+ @$(ECHO) " clean_bsp - Just the BSP"
+ @$(ECHO) " clean_libs - All libraries (including BSP)"
+ @$(ECHO)
+ @$(ECHO) " Run targets:"
+ @$(ECHO) " download-elf - Download and run your elf executable"
+ @$(ECHO) " program-flash - Program flash contents to the board"
+
+# Handy rule to skip making libraries and just make application.
+.PHONY : app
+app : $(ELF)
+
+ifeq ($(CREATE_OBJDUMP), 1)
+app : $(OBJDUMP_NAME)
+endif
+
+ifeq ($(CREATE_ELF_DERIVED_FILES),1)
+app : elf_derived_files
+endif
+
+.PHONY: elf_derived_files
+elf_derived_files: default_mem_init
+
+# Handy rule for making just the BSP.
+.PHONY : bsp
+bsp :
+ @$(ECHO) Info: Building $(BSP_ROOT_DIR)
+ @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR)
+
+
+# Make sure all makeable libraries (including the BSP) are up-to-date.
+LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
+
+.PHONY : libs
+libs : $(LIB_TARGETS)
+
+ifneq ($(strip $(LIB_TARGETS)),)
+$(LIB_TARGETS): %-recurs-make-lib:
+ @$(ECHO) Info: Building $*
+ $(MAKE) --no-print-directory -C $*
+endif
+
+ifneq ($(strip $(APP_LDDEPS)),)
+$(APP_LDDEPS): libs
+ @true
+endif
+
+# Rules to force your project to rebuild or relink
+# .force_relink file will cause any application that depends on this project to relink
+# .force_rebuild file will cause this project to rebuild object files
+# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files
+
+FORCE_RELINK_DEP := .force_relink
+FORCE_REBUILD_DEP := .force_rebuild
+FORCE_REBUILD_ALL_DEP := .force_rebuild_all
+FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP)
+
+$(FORCE_REBUILD_DEP_LIST):
+
+$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS)))
+
+$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS)))
+
+
+# Clean just the application.
+.PHONY : clean
+ifeq ($(CREATE_ELF_DERIVED_FILES),1)
+clean : clean_elf_derived_files
+endif
+
+clean :
+ @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST)
+ @$(ECHO) [$(APP_NAME) clean complete]
+
+# Clean just the BSP.
+.PHONY : clean_bsp
+clean_bsp :
+ @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR)
+ @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean
+
+# Clean all makeable libraries including the BSP.
+LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
+
+.PHONY : clean_libs
+clean_libs : $(LIB_CLEAN_TARGETS)
+
+ifneq ($(strip $(LIB_CLEAN_TARGETS)),)
+$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib:
+ @$(ECHO) Info: Cleaning $*
+ $(MAKE) --no-print-directory -C $* clean
+endif
+
+.PHONY: clean_elf_derived_files
+clean_elf_derived_files: mem_init_clean
+
+# Clean application and all makeable libraries including the BSP.
+.PHONY : clean_all
+clean_all : clean mem_init_clean clean_libs
+
+# Include the dependency files unless the make goal is performing a clean
+# of the application.
+ifneq ($(firstword $(MAKECMDGOALS)),clean)
+ifneq ($(firstword $(MAKECMDGOALS)),clean_all)
+-include $(APP_DEPS)
+endif
+endif
+
+.PHONY : download-elf
+download-elf : $(ELF)
+ @if [ "$(DOWNLOAD)" = "none" ]; \
+ then \
+ $(ECHO) Downloading $(ELF) not supported; \
+ else \
+ $(ECHO) Info: Downloading $(ELF); \
+ $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \
+ fi
+
+# Delete the target of a rule if it has changed and its commands exit
+# with a nonzero exit status.
+.DELETE_ON_ERROR:
+
+# Rules for flash programming commands
+PROGRAM_FLASH_SUFFIX := -program
+PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES))
+
+.PHONY : program-flash
+program-flash : $(PROGRAM_FLASH_TARGET)
+
+.PHONY : $(PROGRAM_FLASH_TARGET)
+$(PROGRAM_FLASH_TARGET) : flash
+ @if [ "$(FLASHPROG)" = "none" ]; \
+ then \
+ $(ECHO) Programming flash not supported; \
+ else \
+ $(ECHO) Info: Programming $(basename $@).flash; \
+ if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \
+ then \
+ $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
+ $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
+ else \
+ $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
+ $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
+ fi \
+ fi
+
+
+# Rules for simulating with an HDL Simulator [QSYS only]
+ifeq ($(QSYS),1)
+#Create a top level modelsim script load_sim.tcl to source generate msim_setup.tcl and copy mem initialization files
+CREATE_TOP_SIM_SCRIPT := alt-create-top-sim-script
+
+ifeq ($(VSIM),)
+VSIM_EXE := "$(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim"
+ifeq ($(ENABLE_VSIM_GUI),1)
+VSIM := $(VSIM_EXE) -gui
+else
+VSIM := $(VSIM_EXE) -c
+endif # ENABLE_VSIM_GUI == 1
+endif # VSIM not set
+
+ifeq ($(SPD),)
+ifneq ($(ABS_QUARTUS_PROJECT_DIR),)
+ifneq ($(SOPC_NAME),)
+SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb.spd
+LEGACY_SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd
+SPD = $(if $(wildcard $(SPD_LOCATION)),$(SPD_LOCATION),$(LEGACY_SPD_LOCATION))
+endif # SOPC_NAME set
+endif # ABS_QUARTUS_PROJECT_DIR set
+endif # SPD == empty string
+
+
+ifeq ($(LOAD_SIM_SCRIPT),)
+SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim
+LOAD_SIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/load_sim.tcl
+endif # LOAD_SIM_SCRIPT == empty string
+
+ifeq ($(MAKE_VERSION),3.81)
+ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE))
+else
+ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE)
+endif
+
+$(LOAD_SIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE)
+ifeq ($(SPD),)
+ $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set)
+endif
+ @$(MKDIR) $(SIM_SCRIPT_DIR)
+ $(CREATE_TOP_SIM_SCRIPT) --spd=$(SPD) --mem-init-spd=$(abspath $(MEM_INIT_DESCRIPTOR_FILE)) --output-directory=$(SIM_SCRIPT_DIR)
+
+VSIM_COMMAND = \
+ cd $(dir $(LOAD_SIM_SCRIPT)) && \
+ $(VSIM) -do "do $(notdir $(LOAD_SIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)"
+
+.PHONY: sim
+sim: $(LOAD_SIM_SCRIPT) mem_init_generate
+ifeq ($(LOAD_SIM_SCRIPT),)
+ $(error LOAD_SIM_SCRIPT not set)
+endif
+ $(VSIM_COMMAND)
+
+endif # QSYS == 1
+
+
+
+
+#------------------------------------------------------------------------------
+# ELF TARGET RULE
+#------------------------------------------------------------------------------
+# Rule for constructing the executable elf file.
+$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS)
+ @$(ECHO) Info: Linking $@
+ $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS)
+ifneq ($(DISABLE_ELFPATCH),1)
+ $(ELFPATCH) $@ $(ELF_PATCH_FLAG)
+endif
+ifneq ($(DISABLE_STACKREPORT),1)
+ @bash -c "$(STACKREPORT) $@"
+endif
+
+$(OBJDUMP_NAME) : $(ELF)
+ @$(ECHO) Info: Creating $@
+ $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@
+
+# Rule for printing the name of the elf file
+.PHONY: print-elf-name
+print-elf-name:
+ @$(ECHO) $(ELF)
+
+
diff --git a/software/usb/src/cy7c67200.h b/software/usb/src/cy7c67200.h
new file mode 100644
index 0000000000000000000000000000000000000000..50715778a2ba6468aaa7a51734382cb8af036a2f
--- /dev/null
+++ b/software/usb/src/cy7c67200.h
@@ -0,0 +1,3327 @@
+#ifndef CY7C67200_H_
+#define CY7C67200_H_
+
+/* ---------------------------------------------------------------------
+ * Cypress C67x00 register definitions
+ */
+
+/* Hardware Revision Register */
+#define HW_REV_REG 0xC004
+
+/* usb controller base address */
+#define CY7C67200_BASE CY7C67200_IF_0_BASE
+//#define CY7C67200_IF_0_IRQ CY7C67200_IF_0_IRQ
+
+/* General USB registers */
+/* ===================== */
+//set for port 1A(0)(Device port 1) and 2A(1)(Host port 2)
+//Note: all the register are 16-bits
+/* USB Control Register */
+//port 1 : 0
+#define USB_CTL_REG(x) ((x) ? 0xC0AA : 0xC08A)
+
+//bit 0
+#define SOF_EOP_EN (0x0001)
+//bit 2 default disable
+#define SUSPEND_EN (0x0004)
+//bit 3 4 default normal state
+#define FORCEDSTATUS (0x0000) //normal state
+//bit 7 default disable
+#define PORT_RES_EN (0x0080) //hardware not connect
+//bit 9 port mode select
+#define PORT_MODE_HOST (0x0200)
+//bit 10 default full speed
+#define LOW_SPEED_PORT (0x0400)
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+/* USB Device 0 only registers */
+/* ============================= */
+/* USB ENDPOINTn CTL register */ //only support endpoint 0 if want to support n need to fix the value to if statement
+#define USB_DEVICE_ENDPOINTn_CTL_REG 0x0200
+//bit 0
+#define DEVICE_ENDPOINTn_ARM_EN(x) ((x) ? 0x0001 : 0x0000) //enable arm endpoint
+//bit 1
+#define DEVICE_ENDPOINTn_Enable(x) ((x) ? 0x0002 : 0x0000) //enable transmit to endpoint 0 from port 0
+//bit 2 1 (OUT transfer Host-->Slave the bit set as 1) (IN transfer Slave-->Host,the bit set as 0)
+#define DEVICE_ENDPOINTn_Direction_Selection(x) ((x) ? 0x0004 : 0x0000) //enable transmit to endpoint 0 from port 0
+//bit 3
+#define DEVICE_ENDPOINTn_NAK_INT_EN(x) ((x) ? 0x0008 : 0x0000) //enable endpoint NAK (response to host) interrupt to port 0
+//bit 4 iso transmit enable (Valid for Endpoint1-7)
+#define DEVICE_ENDPOINTn_ISO_EN(x) ((x) ? 0x0010 : 0x0000) //enable endpoint iso transmit to port 0
+//bit 5
+#define DEVICE_ENDPOINTn_Stall_EN(x) ((x) ? 0x0020 : 0x0000) //enable send stall in response to the next request
+//bit 6 (1:Data1 0:Data0) impact on tx only
+#define DEVICE_ENDPOINTn_Seq_Sel() ((x) ? 0x0040 : 0x0000) //the sequence data net data toggle
+//bit 7
+#define DEVICE_ENDPOINT0_Inout_Ignore(x) ((x) ? 0x0080 : 0x0000) //enable Endpoint 0 inout
+
+/* USB ENDPOINTn Address register */
+//assign the address in the memory space for endpoint n transaction can allocate in the user space 0x04A4- 0x3FFF
+#define USB_DEVICE_ENDPOINTn_Address_REG (x0202)
+
+/* USB ENDPOINTn Count register */
+//assign the OUT max packet size from PC and In max packet size to the Host 10-bit
+# define USB_DEVICE_ENDPOINTn_Count_REG (x0204)
+
+/* USB ENDPOINTn Status register */ //MUST initial to 0x0000 at first,then forbidden to write to
+//assign the OUT max packet size from PC and In max packet size to the Host 10-bit
+# define USB_DEVICE_ENDPOINTn_Status_REG (0x0206)
+//Note: all bits should be write to 0s for initial
+//bit 0 indicate the last transaction occur or not
+# define DEVICE_ENDPOINTn_ACK_FLAG (0x0001)
+//bit 1 CRC5,CRC12 or incorrect packet type received
+# define DEVICE_ENDPOINTn_Error_FLAG (0x0002)
+//bit 2 last transaction Timeout or not
+# define DEVICE_ENDPOINTn_Timeout_FLAG (0x0004)
+//bit 3 indicate the last data toggle received was a data1 or data0
+#define DEVICE_ENDPOINTn_Sequence_FLAG (0x0008)
+//bit 4 indicate the setup packet was received or not, for device 1 the setup packet are stored at mem location 0x0300
+#define DEVICE_ENDPOINTn_Setup_FLAG (0x0010)
+//bit 5 indicate the length in last transaction same or not to the endpoint count reg
+#define DEVICE_ENDPOINTn_Length_Exception_FLAG (0x0020)
+//bit 6 indicate the NAK flag packet was sent to the host or not
+#define DEVICE_ENDPOINTn_NAK_FLAG (0x0040)
+//bit 7 indicate the stall packet was sent to host or not
+#define DEVICE_ENDPOINTn_Stall_FLAG (0x0080)
+//bit 8 IN Exception Flag
+#define DEVICE_ENDPOINTn_IN_Exception_FLAG (0x0100)
+// 1 : Received IN when armed for OUT
+// 0 : Received OUT when armed for OUT
+//bit 9 OUT Exception Flag
+#define DEVICE_ENDPOINTn_OUT_Exception_FLAG (0x0200)
+// 1 : Received OUT when armed for IN
+// 0 : Received IN when armed for IN
+//bit 10
+#define DEVICE_ENDPOINTn_Underflow_FLAG (0x0400)
+//bit 11
+#define DEVICE_ENDPOINTn_Overflow_FLAG (0x0800)
+
+/* USB ENDPOINTn Count result register */ //MUST initial to 0x0000 at first,then forbidden to write to
+//assign the difference of packet size between the length assigned in the count register and the actual length received (overflow/underflow)
+# define USB_DEVICE_ENDPOINTn_CountResult_REG (x0208)
+//all bits should be write to 0s
+
+/* USB DEVICE 0 interrupt enable register */
+//The Device n Interrupt Enable register provides control over
+//device-related interrupts including eight different endpoint interrupts.
+#define USB_DEVICE_INT_EN_REG (0xC08C)
+
+//bit 0
+#define DEVICE_EPO_INT_EN(x) ((x) ? 0x0001 : 0x0000) //enable Endpoint 0 interrupt
+//bit 1
+#define DEVICE_EP1_INT_EN(x) ((x) ? 0x0002 : 0x0000) //enable Endpoint 1 interrupt
+//bit 2
+#define DEVICE_EP2_INT_EN(x) ((x) ? 0x0004 : 0x0000) //enable Endpoint 2 interrupt
+//bit 3
+#define DEVICE_EP3_INT_EN(x) ((x) ? 0x0008 : 0x0000) //enable Endpoint 3 interrupt
+//bit 4
+#define DEVICE_EP4_INT_EN(x) ((x) ? 0x0010 : 0x0000) //enable Endpoint 4 interrupt
+//bit 5
+#define DEVICE_EP5_INT_EN(x) ((x) ? 0x0020 : 0x0000) //enable Endpoint 5 interrupt
+//bit 6
+#define DEVICE_EP6_INT_EN(x) ((x) ? 0x0040 : 0x0000) //enable Endpoint 6 interrupt
+//bit 7
+#define DEVICE_EP7_INT_EN(x) ((x) ? 0x0080 : 0x0000) //enable Endpoint 7 interrupt
+//bit 8 usb reset interrupt enable
+#define DEVICE_USB_ResetDetect_INT_EN(x) ((x) ? 0x0100 : 0x0000) //enable USB device reset interrupt
+//bit 9
+#define DEVICE_SOF_EOP_INT_EN(x) ((x) ? 0x0200 : 0x0000) //enable SOP/EOP interrupt
+//bit 11
+#define DEVICE_SOF_EOP_Timeout_INT_EN(x) ((x) ? 0x0800 : 0x0000) //enable SOF/EOP Timeout interrupt
+//bit 14 (OTG ID edge detection)
+#define DEVICE_ID_INT_EN(x) ((x) ? 0x4000 : 0x0000) //enable OTG ID interrupt
+//bit 15 (OTG VBUS interrupt enable)
+#define DEVICE_VBUS_INT_EN(x) ((x) ? 0x8000 : 0x0000) //enable OTG VBUS interrupt
+
+/* USB DEVICE 0 address register */
+//The Device n address register holds the address assigned by the host
+//
+#define USB_DEVICE_Address_REG (0xC08E)
+//the register should be write the device address assigned by host
+
+/* USB DEVICE 0 status register */
+//The Device n status register provides status information for device operation
+//
+#define USB_DEVICEn_Status_REG (0xC090)
+//Pending interrupts can be cleared by writing a ¡®1¡¯ to the corresponding bit.
+//bit 0
+#define DEVICE_EP0_INT_Flag (0x0001)
+//bit 1
+#define DEVICE_EP1_INT_Flag (0x0002)
+//bit 2
+#define DEVICE_EP2_INT_Flag (0x0004)
+//bit 3
+#define DEVICE_EP3_INT_Flag (0x0008)
+//bit 4
+#define DEVICE_EP4_INT_Flag (0x0010)
+//bit 5
+#define DEVICE_EP5_INT_Flag (0x0020)
+//bit 6
+#define DEVICE_EP6_INT_Flag (0x0040)
+//bit 7
+#define DEVICE_EP7_INT_Flag (0x0080)
+//bit 8
+#define DEVICE_Reset_INT_Flag (0x0100)
+//bit 9
+#define DEVICE_SOF_EOP_INT_Flag (0x0200)
+//bit 14
+#define DEVICE_OTG_ID_INT_Flag (0x4000)
+//bit 15
+#define DEVICE_VBUS_INT_Flag (0x8000)
+
+/* USB DEVICE 0 Frame Num register */
+//The Device n Frame Number register is a read only register contains the Frame number of the last sof packet
+//read only
+#define USB_DEVICEn_FrameNum_REG (0xC092)
+//bit 10-0
+#define DEVICE_FrameNum (0x07FF)
+//bit 14-12
+#define DEVICE_SOF_EOP_Timeout_INT_Count (0x7000)
+//bit 15
+#define DEVICE_SOF_EOP_INT_Flag1 (0x8000)
+
+/* USB DEVICE 0 Frame Num register */
+//The Device n SOF/EOP count register is a write only register contains the time interval between SOF/EOP
+//write only
+#define DEVICE_SOF_EOP_COUNT_REG (0x3FFF)
+#define DEVICE_SOF_EOP_COUNT_NUM (0x2EE0+0x0010)
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/* USB Host 1 only registers */
+/* ============================= */
+
+/* USB Host 1 Control register */
+//The Host n Control register allows high-level USB transaction control.
+//read only
+#define USB_HOSTn_CTL_REG (0xC0A0)
+//bit 0
+#define HOST_ARM_EN (0x0001)
+//bit 4
+#define HOST_ISO_EN (0x0010) //for ISO transaction
+//bit 5
+#define HOST_SYN_EN (0x0020)
+// 1: The next enabled packet will be transferred after the SOF
+//or EOP packet is transmitted
+// 0: The next enabled packet will be transferred as soon as the
+//SIE is free
+//bit 6
+#define HOST_SEQ_SEL (0x0040)
+//bit 7
+#define HOST_PRE_EN (0x0080) //preamble for low speed device
+
+/* USB Host 1 Address register */
+//The Host n Address register is used as the base pointer into memory space for the current host transactions.
+//read only 16 bit
+#define USB_HOSTn_Address_REG (0xC0A2)
+
+/* USB Host 1 Count register */
+//The Host n Count register is used to hold the number of bytes (packet length) for the current transaction. The maximum
+//packet length is 1023 bytes in ISO mode.
+//read only 10 bit
+#define USB_HOSTn_Count_REG (0xC0A4)
+
+#define HOST_COUNT_MASK (0x03FF)
+
+/* USB Host 1 PID register */
+//The Host n PID register is a write-only register that provides the PID and Endpoint information to the USB SIE to be used
+//in the next transaction.
+//write only
+#define USB_HOSTn_PID_REG (0xC0A6)
+//bit0-3
+#define HOST_ENDPOINT_SEL (0x000F)
+//bit4-7
+#define HOST_PID_SEL (0x00F0)
+
+/* USB Host 1 Count Result register */
+//The Host n Count Result register is a read-only register that contains the size difference in bytes between the Host Count
+//Value specified in the Host n Count register and the last packet received.
+//in the next transaction.
+//read only
+#define USB_HOSTn_Count_Result_REG (0xC0A8)
+//bit0-15
+#define HOST_Count_Result_MASK (0xFFFF)
+
+/* USB Host 1 Device Address register */
+//The Host n Device Address register is a write-only register that contains the USB Device Address that the host wishes to communicate with.
+//read only
+#define USB_HOSTn_Device_Address_REG (0xC0A8)
+//bit0-15
+#define HOST_Device_Address_MASK (0x007F)
+
+/* USB Host 1 Interrupt Enable register */
+//The Host n Interrupt Enable register allows control over host-related interrupts.
+//R/W
+#define USB_HOSTn_INT_EN_REG (0xC0AC)
+//bit0
+#define HOST_DONE_INT_EN (0x0001)
+//bit4
+#define HOST_CON_CHANGE_EN (0x0010)
+//bit6
+#define HOST_WAKE_INT_EN (0x0040)
+//bit9
+#define HOST_SOF_EOP_INT_EN (0x0200)
+//bit14
+#define HOST_OTG_ID_INT_EN (0x4000)
+//bit15
+#define HOST_VBUS_INT_EN (0x8000)
+
+/* USB Host 1 Status register */
+//The Host n Status register provides status information for host operation.
+//R/W
+#define USB_HOSTn_STATUS_REG (0xC0B0)
+//bit0
+#define HOST_DONE_INT_FLAG (0x0001)
+//bit2
+#define HOST_SE0_FLAG (0x0002)
+//bit4
+#define HOST_CONNECT_CHANGE_INT_FLAG (0x0010)
+//bit6
+#define HOST_WAKE_INT_FLAG (0x0040)
+//bit9
+#define HOST_SOF_EOP_INT_FLAG (0x0200)
+//bit14
+#define HOST_OTG_ID_INT_FLAG (0x4000)
+//bit15
+#define HOST_VBUS_INT_FLAG (0x8000)
+
+
+/* USB Host 1 SOF EOP Count register */
+//The Host n SOF/EOP Count register contains the SOF/EOP
+//Count Value that is loaded into the SOF/EOP counter
+//R/W
+#define USB_HOSTn_SOF_EOP_COUNT_REG (0xC0B2)
+//bit 0-13
+#define HOST_SOF_EOP_COUNT_MASK (0x3FFF)
+
+/* USB Host 1 SOF EOP Count register */
+//The Host n SOF/EOP Counter register contains the current
+//value of the SOF/EOP down counter
+//R
+#define USB_HOSTn_SOF_EOP_COUNT_REG1 (0xC0B4)
+//bit 0-13
+#define HOST_SOF_EOP_COUNT_MASK (0x3FFF)
+
+/* USB Host 1 FRAME Count register */
+//The Host n Frame register maintains the next frame number
+//to be transmitted (current frame number + 1)
+//R
+#define USB_HOSTn_FRAME_COUNT_REG1 (0xC0B6)
+//bit 0-13
+#define HOST_FRAME_COUNT_MASK (0x07FF)
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/* USB HPI registers */
+/* ============================= */
+
+/* USB HPI breakpoint register */
+//The HPI Breakpoint register is a special on-chip memory location, which the external processor can access using normal HPI
+//memory read/write cycles.
+//R/W for HPI
+#define HPI_BreakPoint_REG (0x0140)
+
+/* USB HPI interrupt routing register */
+//The Interrupt Routing register allows the HPI port to take over
+//some or all of the SIE interrupts that usually go to the on-chip CPU.
+//R/W for HPI
+#define HPI_INT_ROUTING_REG (0x0142)
+
+//bit 0 & 8 not swap setting
+#define HPI_SWAP_EN (0x0000)
+//bit except 1 2
+#define HPI_ROUTE_EN (0xFECE)
+
+/* USB HPI SIEmsg register */
+//The SIEXmsg register allows an interrupt to be generated on the HPI port
+//R/W for HPI
+#define HPI_SIEmsg1_REG (0x0144)
+#define HPI_SIEmsg2_REG (0x0148)
+//bit 0-15
+#define HPI_SIEmsg_MASK (0xFFFF)
+
+/* USB HPI Mailbox register */
+//The HPI Mailbox register provides a common mailbox between the CY7C67200 and the external host processor.
+#define HPI_Mailbox_REG (0xC0C6)
+//bit 0-15
+#define HPI_Mailbox_MASK (0xFFFF)
+
+/* USB HPI Status register */
+//The HPI Status Port provides the external host processor with
+//the MailBox status bits plus several SIE status bits
+#define HPI_STATUS_REG //A1 A0 = 1 1
+//bit 0
+#define HPI_STATUS_Mailbox_Out_FLAG (0x0001)
+//bit 1
+#define HPI_STATUS_RESET1_FLAG (0x0002)
+//bit 2
+#define HPI_STATUS_DONE1_FLAG (0x0004)
+//bit 3
+#define HPI_STATUS_DONE2_FLAG (0x0008)
+//bit 4
+#define HPI_STATUS_SIE1msg_FLAG (0x0010)
+//bit 5
+#define HPI_STATUS_SIE2msg_FLAG (0x0020)
+//bit 6
+#define HPI_STATUS_Resume1_FLAG (0x0040)
+//bit 7
+#define HPI_STATUS_Resume2_FLAG (0x0080)
+//bit 8
+#define HPI_STATUS_Mailbox_In_FLAG (0x0100)
+//bit 9
+//#define HPI_STATUS_RESET1_FLAG (0x0200)
+//bit 10
+#define HPI_STATUS_SOF_EOP1_FLAG (0x0400)
+//bit 12
+#define HPI_STATUS_SOF_EOP2_FLAG (0x1000)
+//bit 14
+#define HPI_STATUS_SOF_OTG_ID_FLAG (0x4000)
+//bit 15
+#define HPI_STATUS_VBUS_FLAG (0x8000)
+
+
+
+
+
+/*********************************************************/
+/* FILE : 63700.H */
+/*********************************************************/
+/* DATE : 06/24/02 */
+/* BY : Barry Hatton */
+/* VERSION : 00.04 */
+/* */
+/* History: */
+/* SBN: Update to the latest spec July/26/02 */
+/* Change Label to start with character */
+/* */
+/* SBN: Add July/28/02 */
+/* New definition to work with current BIOS code */
+/* Update HPI HW change address 0x120-0x122 */
+/* */
+/* SBN: Copy SPI/HPI/IDE definition from sys_memmap.cds*/
+/* SBN: Add HSS definition from sys_memmap.cds */
+/* */
+/* DESCRIPTION : This file contains the register and */
+/* field definitions for the CY7C63700. */
+/* */
+/* NOTICE : This file is provided as-is for */
+/* reference purposes only. No warranty is */
+/* made as to functionality or suitability */
+/* for any particular purpose or */
+/* application. */
+/* */
+/* COPYRIGHT 2002, CYPRESS SEMICONDUCTOR CORP. */
+/*********************************************************/
+
+/*********************************************************/
+/* REGISTER/FIELD NAMING CONVENTIONS */
+/*********************************************************/
+/* */
+/* Fieldss can be considered either: */
+/* (a) BOOLEAN (1 or 0, On or Off, True or False) or */
+/* (b) BINARY (Numeric value) */
+/* */
+/* Multiple-bit fields contain numeric values only. */
+/* */
+/* Boolean fields are identified by the _EN suffix? */
+/* */
+/* Binary fields are defined by the field name. In */
+/* addition, all legal values for the binary field are */
+/* identified. */
+/* */
+/* Either ALL register names should include REG as part */
+/* of the label or NO register names should include REG */
+/* as part of the label. */
+/* */
+/* Certain nomenclature is applied universally within */
+/* this file. Commonly applied abbreviations include: */
+/* */
+/* EN Enable */
+/* DIS Disable */
+/* SEL Select */
+/* FLG Flag */
+/* STB Strobe */
+/* */
+/* ADDR Address */
+/* CTL Control */
+/* CNTRL Control */
+/* CFG Config */
+/* RST Reset */
+/* BFR Buffer */
+/* REG Register */
+/* SIE Serial Interface Engine */
+/* DEV Device */
+/* HOST Host */
+/* EP Endpoint */
+/* IRQ Interrupt */
+/* BKPT Breakpoint */
+/* STAT Status */
+/* CNT Count */
+/* CTR Counter */
+/* TMR Timer */
+/* MAX Maximum */
+/* MIN Minimum */
+/* POL Polarity */
+/* BLK Block */
+/* WDT Watchdog Timer */
+/* RX Receive */
+/* RXD Received */
+/* TX Transmit */
+/* TXD Transmitted */
+/* ACK Acknowledge */
+/* ACKD Acknowledged */
+/* MBX Mailbox */
+/* CLR Clear */
+/* bm Bit Mask (prefix) */
+/* XRAM External RAM */
+/* */
+/*********************************************************/
+
+/*********************************************************/
+/* REGISTER SUMMARY */
+/*********************************************************/
+/* */
+/* PROC_FLAGS_REG */
+/* REG_BANK_REG */
+/* HW_REV_REG */
+/* IRQ_EN_REG */
+/* CPU_SPEED_REG */
+/* POWER_CTL_REG */
+/* BKPT_REG */
+/* USB_DIAG_REG */
+/* MEM_DIAG_REG */
+/* */
+/* PGn_MAP_REG */
+/* DRAM_CTL_REG */
+/* XMEM_CTL_REG */
+/* */
+/* WDT_REG */
+/* TMRn_REG */
+/* */
+/* USBn_CTL_REG */
+/* */
+/* HOSTn_IRQ_EN_REG */
+/* HOSTn_STAT_REG */
+/* HOSTn_CTL_REG */
+/* HOSTn_ADDR_REG */
+/* HOSTn_CNT_REG */
+/* HOSTn_PID_REG */
+/* HOSTn_EP_STAT_REG */
+/* HOSTn_DEV_ADDR_REG */
+/* HOSTn_CTR_REG */
+/* HOSTn_SOF_EOP_CNT_REG */
+/* HOSTn_SOF_EOP_CTR_REG */
+/* HOSTn_FRAME_REG */
+/* */
+/* DEVn_IRQ_EN_REG */
+/* DEVn_STAT_REG */
+/* DEVn_ADDR_REG */
+/* DEVn_FRAME_REG */
+/* DEVn_EPn_CTL_REG */
+/* DEVn_EPn_ADDR_REG */
+/* DEVn_EPn_CNT_REG */
+/* DEVn_EPn_STAT_REG */
+/* DEVn_EPn_CTR_REG */
+/* */
+/* OTG_CTL_REG */
+/* */
+/* GPIO_CTL_REG */
+/* GPIOn_OUT_DATA_REG */
+/* GPIOn_IN_DATA_REG */
+/* GPIOn_DIR_REG */
+/* */
+/* EPP_CTL_REG */
+/* EPP_DATA_REG */
+/* EPP_BFR_READ_REG */
+/* EPP_ADDR_REG */
+/* */
+/* IDE_MODE_REG */
+/* IDE_START_ADDR_REG */
+/* IDE_STOP_ADDR_REG */
+/* IDE_CTL_REG */
+/* IDE_PIO_DATA_REG */
+/* IDE_PIO_ERR_REG */
+/* IDE_PIO_SECT_CNT_REG */
+/* IDE_PIO_SECT_NUM_REG */
+/* IDE_PIO_CYL_LO_REG */
+/* IDE_PIO_CYL_HI_REG */
+/* IDE_PIO_DEV_HD_REG */
+/* IDE_PIO_CMD_REG */
+/* IDE_PIO_DEV_CTL_REG */
+/* */
+/* MDMA_MODE_REG */
+/* MDMA_START_ADDR_REG */
+/* MDMA_STOP_ADDR_REG */
+/* MDMA_CTL_REG */
+/* */
+/* HSS_CTL_REG */
+/* HSS_BAUD_REG */
+/* HSS_TX_GAP_REG */
+/* HSS_DATA_REG */
+/* HSS_RX_ADDR_REG */
+/* HSS_RX_CTR_REG */
+/* HSS_TX_ADDR_REG */
+/* HSS_TX_CTR_REG */
+/* */
+/* SPI_CFG_REG */
+/* SPI_CTL_REG */
+/* SPI_IRQ_EN_REG */
+/* SPI_STAT_REG */
+/* SPI_IRQ_CLR_REG */
+/* SPI_CRC_CTL_REG */
+/* SPI_CRC_VALUE_REG */
+/* SPI_DATA_REG */
+/* SPI_TX_ADDR_REG */
+/* SPI_TX_CNT_REG */
+/* SPI_RX_ADDR_REG */
+/* SPI_RX_CNT_REG */
+/* */
+/* UART_CTL_REG */
+/* UART_STAT_REG */
+/* UART_DATA_REG */
+/* */
+/* PWM_CTL_REG */
+/* PWM_MAX_CNT_REG */
+/* PWMn_START_REG */
+/* PWMn_STOP_REG */
+/* PWM_CYCLE_CNT_REG */
+/* */
+/* HPI_MBX_REG */
+/* HPI_BKPT_REG */
+/* IRQ_ROUTING_REG */
+/* */
+/* HPI_DATA_PORT */
+/* HPI_ADDR_PORT */
+/* HPI_MBX_PORT */
+/* HPI_STAT_PORT */
+/* */
+/*********************************************************/
+
+/*********************************************************/
+/*********************************************************/
+/* CPU REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* CPU FLAGS REGISTER [R] */
+/*********************************************************/
+#define CPU_FLAGS_REG 0xC000 /* CPU Flags Register [R] */
+#define flags 0xC000
+
+/* FIELDS */
+
+#define GLOBAL_IRQ_EN 0x0010 /* Global Interrupt Enable */
+#define NEG_FLG 0x0008 /* Negative Sign Flag */
+#define OVF_FLG 0x0004 /* Overflow Flag */
+#define CARRY_FLG 0x0002 /* Carry/Borrow Flag */
+#define ZER0_FLG 0x0001 /* Zero Flag */
+
+/*********************************************************/
+/* BANK REGISTER [R/W] */
+/*********************************************************/
+
+#define BANK_REG 0xC002 /* Bank Register [R/W] */
+#define regbuf 0xC002 /* alias for BIOS code */
+
+#define BANK 0xFFE0 /* Bank */
+
+/*********************************************************/
+/* HARDWARE REVISION REGISTER [R] */
+/*********************************************************/
+/* First Silicon Revision is 0x0101. Revision number */
+/* will be incremented by one for each revision change. */
+/*********************************************************/
+
+#define HW_REV_REG 0xC004 /* Hardware Revision Register [R] */
+
+/*********************************************************/
+/* INTERRUPT ENABLE REGISTER [R/W] */
+/*********************************************************/
+
+#define IRQ_EN_REG 0xC00E /* Interrupt Enable Register [R/W] */
+#define intenb 0xC00E /* Alias for BIOS code */
+#define INT_EN_REG 0xC00E /* BIOS Interrupt Enable Register Alias */
+
+/* FIELDS */
+
+#define OTG_IRQ_EN 0x1000 /* OTG Interrupt Enable */
+#define SPI_IRQ_EN 0x0800 /* SPI Interrupt Enable */
+#define HOST2_IRQ_EN 0x0200 /* Host 2 Interrupt Enable */
+#define DEV2_IRQ_EN 0x0200 /* Device 2 Interrupt Enable */
+#define HOST1_IRQ_EN 0x0100 /* Host 1 Interrupt Enable */
+#define DEV1_IRQ_EN 0x0100 /* Device 1 Interrupt Enable */
+#define HSS_IRQ_EN 0x0080 /* HSS Interrupt Enable */
+#define IN_MBX_IRQ_EN 0x0040 /* In Mailbox Interrupt Enable */
+#define OUT_MBX_IRQ_EN 0x0020 /* Out Mailbox Interrupt Enable */
+#define DMA_IRQ_EN 0x0010 /* DMA Interrupt Enable */
+#define UART_IRQ_EN 0x0008 /* UART Interrupt Enable */
+#define GPIO_IRQ_EN 0x0004 /* GPIO Interrupt Enable */
+#define TMR1_IRQ_EN 0x0002 /* Timer 1 Interrupt Enable */
+#define TMR0_IRQ_EN 0x0001 /* Timer 0 Interrupt Enable */
+
+/* Alias bit mask definition for register IRQ_EN_REG */
+#define bmINT_EN_TM0 0x0001
+#define bmINT_EN_TM1 0x0002
+#define bmINT_EN_GPIO 0x0004
+#define bmINT_EN_UART 0x0008
+#define bmINT_EN_DMA 0x0010
+#define bmINT_EN_MBX_OUT 0x0020
+#define bmINT_EN_MBX_IN 0x0040
+#define bmINT_EN_HSP 0x0080
+#define bmINT_EN_SIE1 0x0100
+#define bmINT_EN_SIE2 0x0200
+#define bmINT_EN_SPI 0x0800
+#define bmINT_EN_OTG 0x1000
+
+/* another define from sys_memmap */
+#define GIO_IntCtl_MSK 0x0000
+#define GIO_IntCtl_IRQ0En_BIT 0x0000
+#define GIO_IntCtl_IRQ0En_BM 0x0001
+#define GIO_IntCtl_IRQ0Pol_BIT 0x0001
+#define GIO_IntCtl_IRQ0Pol_BM 0x0002
+#define GIO_IntCtl_IRQ1En_BIT 0x0002
+#define GIO_IntCtl_IRQ1En_BM 0x0004
+#define GIO_IntCtl_IRQ1Pol_BIT 0x0003
+#define GIO_IntCtl_IRQ1Pol_BM 0x0008
+#define GIO_IntCtl_SX_BIT 0x0004
+#define GIO_IntCtl_SX_BM 0x0010
+#define GIO_IntCtl_SG_BIT 0x0005
+#define GIO_IntCtl_SG_BM 0x0020
+#define GIO_IntCtl_HX_BIT 0x0006
+#define GIO_IntCtl_HX_BM 0x0040
+#define GIO_IntCtl_HG_BIT 0x0007
+#define GIO_IntCtl_HG_BM 0x0080
+
+#define GIO_IntCtl_Mode_POS 0x0008
+#define GIO_IntCtl_Mode_SIZ 0x0003
+#define GIO_IntCtl_Mode_GPIO 0x0000
+#define GIO_IntCtl_Mode_GPIObm 0x0000
+#define GIO_IntCtl_Mode_Flash 0x0001
+#define GIO_IntCtl_Mode_Flashbm 0x0100
+#define GIO_IntCtl_Mode_EPP 0x0002
+#define GIO_IntCtl_Mode_EPPbm 0x0200
+#define GIO_IntCtl_Mode_SLV 0x0003
+#define GIO_IntCtl_Mode_SLVbm 0x0300
+#define GIO_IntCtl_Mode_IDE 0x0004
+#define GIO_IntCtl_Mode_IDEbm 0x0400
+#define GIO_IntCtl_Mode_HPI 0x0005
+#define GIO_IntCtl_Mode_HPIbm 0x0500
+#define GIO_IntCtl_Mode_SCAN 0x0006
+#define GIO_IntCtl_Mode_SCANbm 0x0600
+#define GIO_IntCtl_Mode_MDiag 0x0007
+#define GIO_IntCtl_Mode_MDiagbm 0x0700
+
+#define GIO_IntCtl_Bond_POS 0x000B
+#define GIO_IntCtl_Bond_SIZ 0x0002
+#define GIO_IntCtl_Bond_Embed 0x0000
+#define GIO_IntCtl_Bond_Embedbm 0x0000
+#define GIO_IntCtl_Bond_Flash 0x0001
+#define GIO_IntCtl_Bond_Flashbm 0x0800
+#define GIO_IntCtl_Bond_Mobile 0x0002
+#define GIO_IntCtl_Bond_Mobilebm 0x1000
+
+#define GIO_IntCtl_MD_BIT 0x000F
+
+#define INT_Enable_T0_BIT 0x0000
+#define INT_Enable_T0_BM 0x0001
+#define INT_Enable_T1_BIT 0x0001
+#define INT_Enable_T1_BM 0x0002
+#define INT_Enable_GP_BIT 0x0002
+#define INT_Enable_GP_BM 0x0004
+#define INT_Enable_UART_BIT 0x0003
+#define INT_Enable_UART_BM 0x0008
+#define INT_Enable_FDMA_BIT 0x0004
+#define INT_Enable_FDMA_BM 0x0010
+#define INT_Enable_MBX_BIT 0x0006
+#define INT_Enable_MBX_BM 0x0040
+#define INT_Enable_HSS_BIT 0x0007
+#define INT_Enable_HSS_BM 0x0080
+#define INT_Enable_SIE1_BIT 0x0008
+#define INT_Enable_SIE1_BM 0x0100
+#define INT_Enable_SIE2_BIT 0x0009
+#define INT_Enable_SIE2_BM 0x0200
+#define INT_Enable_SPI_BIT 0x000B
+#define INT_Enable_SPI_BM 0x0800
+
+/*********************************************************/
+/* CPU SPEED REGISTER [R/W] */
+/*********************************************************/
+
+#define CPU_SPEED_REG 0xC008 /* CPU Speed Register [R/W] */
+#define P_SPEED 0xC008 /* Alias for BIOS code */
+
+/* CPU SPEED REGISTER FIELDS
+**
+** The Speed field in the CPU Speed Register provides a mechanism to
+** divide the external clock signal down to operate the CPU at a lower
+** clock speed (presumedly for lower-power operation). The value loaded
+** into this field is a divisor and is calculated as (n+1). For instance,
+** if 3 is loaded into the field, the resulting CPU speed will be PCLK/4.
+*/
+
+#define CPU_SPEED 0x000F /* CPU Speed */
+
+/*********************************************************/
+/* POWER CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define POWER_CTL_REG 0xC00A /* Power Control Register [R/W] */
+
+/* FIELDS */
+
+#define HOST2_WAKE_EN 0x4000 /* Host 2 Wake Enable */
+#define DEV2_WAKE_EN 0x4000 /* Device 2 Wake Enable */
+#define HOST1_WAKE_EN 0x1000 /* Host 1 Wake Enable */
+#define DEV1_WAKE_EN 0x1000 /* Device 1 Wake Enable */
+#define OTG_WAKE_EN 0x0800 /* OTG Wake Enable */
+#define HSS_WAKE_EN 0x0200 /* HSS Wake Enable */
+#define SPI_WAKE_EN 0x0100 /* SPI Wake Enable */
+#define HPI_WAKE_EN 0x0080 /* HPI Wake Enable */
+#define GPIO_WAKE_EN 0x0010 /* GPIO Wake Enable */
+#define SLEEP_EN 0x0002 /* Sleep Enable */
+#define HALT_EN 0x0001 /* Halt Enable */
+
+/*********************************************************/
+/* BREAKPOINT REGISTER [R/W] */
+/*********************************************************/
+
+#define BKPT_REG 0xC014 /* Breakpoint Register [R/W] */
+
+/*********************************************************/
+/* USB DIAGNOSTIC REGISTER [W] */
+/*********************************************************/
+
+#define USB_DIAG_REG 0xC03C /* USB Diagnostic Register [R/W] */
+
+/* FIELDS */
+
+#define c2B_DIAG_EN 0x8000 /* Port 2B Diagnostic Enable */
+#define c2A_DIAG_EN 0x4000 /* Port 2A Diagnostic Enable */
+#define c1B_DIAG_EN 0x2000 /* Port 1B Diagnostic Enable */
+#define c1A_DIAG_EN 0x1000 /* Port 1A Diagnostic Enable */
+#define PULLDOWN_EN 0x0040 /* Pull-down resistors enable */
+#define LS_PULLUP_EN 0x0020 /* Low-speed pull-up resistor enable */
+#define FS_PULLUP_EN 0x0010 /* Full-speed pull-up resistor enable */
+#define FORCE_SEL 0x0007 /* Control D+/- lines */
+
+/* FORCE FIELD VALUES */
+
+#define ASSERT_SE0 0x0004 /* Assert SE0 on selected ports */
+#define TOGGLE_JK 0x0002 /* Toggle JK state on selected ports */
+#define ASSERT_J 0x0001 /* Assert J state on selected ports */
+#define ASSERT_K 0x0000 /* Assert K state on selected ports */
+
+/*********************************************************/
+/* MEMORY DIAGNOSTIC REGISTER [W] */
+/*********************************************************/
+
+#define MEM_DIAG_REG 0xC03E /* Memory Diagnostic Register [W] */
+
+/* FIELDS */
+
+#define FAST_REFRESH_EN 0x8000 /* Fast Refresh Enable (15x acceleration) */
+#define MEM_ARB_SEL 0x0700 /* Memory Arbitration */
+#define MONITOR_EN 0x0001 /* Monitor Enable (Echoes internal address bus externally) */
+
+/* MEMORY ARBITRATION SELECT FIELD VALUES */
+#define MEM_ARB_7 0x0700 /* Number of dead cycles out of 8 possible */
+#define MEM_ARB_6 0x0600 /* Should not use any cycle >= 6 */
+#define MEM_ARB_5 0x0500 /* */
+#define MEM_ARB_4 0x0400 /* */
+#define MEM_ARB_3 0x0300 /* */
+#define MEM_ARB_2 0x0200 /* */
+#define MEM_ARB_1 0x0100 /* */
+#define MEM_ARB_0 0x0000 /* Power up default */
+
+/*********************************************************/
+/* EXTENDED PAGE n MAP REGISTER [R/W] */
+/*********************************************************/
+
+#define PG1_MAP_REG 0xC018 /* Page 1 Map Register [R/W] */
+#define PG2_MAP_REG 0xC01A /* Page 2 Map Register [R/W] */
+
+/*********************************************************/
+/* DRAM CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define DRAM_CTL_REG 0xC038 /* DRAM Control Register [R/W] */
+
+/* FIELDS */
+
+#define DRAM_DIS 0x0008 /* DRAM Disable */
+#define TURBO_EN 0x0004 /* Turbo Mode */
+#define PAGE_MODE_EN 0x0002 /* Page Mode */
+#define REFRESH_EN 0x0001 /* Refresh */
+
+/*********************************************************/
+/* EXTERNAL MEMORY CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define XMEM_CTL_REG 0xC03A /* External Memory Control Register [R/W] */
+#define X_MEM_CNTRL 0xC03A /* Alias for BIOS code */
+
+#define XRAM_BEGIN 0x4000 /* External SRAM begin */
+#define XROM_BEGIN 0xC100 /* External ROM Begin */
+#define IROM_BEGIN 0xE000 /* Internal ROM Begin */
+
+
+/* FIELDS */
+#define XRAM_MERGE_EN 0x2000 /* Overlay XRAMSEL w/ XMEMSEL */
+#define XROM_MERGE_EN 0x1000 /* Overlay XROMSEL w/ XMEMSEL */
+#define XMEM_WIDTH_SEL 0x0800 /* External MEM Width Select */
+#define XMEM_WAIT_SEL 0x0700 /* Number of Extended Memory wait states (0-7) */
+#define XROM_WIDTH_SEL 0x0080 /* External ROM Width Select */
+#define XROM_WAIT_SEL 0x0070 /* Number of External ROM wait states (0-7) */
+#define XRAM_WIDTH_SEL 0x0008 /* External RAM Width Select */
+#define XRAM_WAIT_SEL 0x0007 /* Number of External RAM wait states (0-7) */
+
+/* XMEM_WIDTH FIELD VALUES */
+
+#define XMEM_8 0x0800 /* */
+#define XMEM_16 0x0000 /* */
+
+/* XRAM_WIDTH FIELD VALUES */
+
+#define XROM_8 0x0080 /* */
+#define XROM_16 0x0000 /* */
+
+/* XRAM_WIDTH FIELD VALUES */
+
+#define XRAM_8 0x0008 /* */
+#define XRAM_16 0x0000 /* */
+
+
+/*********************************************************/
+/* WATCHDOG TIMER REGISTER [R/W] */
+/*********************************************************/
+
+#define WDT_REG 0xC00C /* Watchdog Timer Register [R/W] */
+
+/* FIELDS */
+
+#define WDT_TIMEOUT_FLG 0x0020 /* WDT timeout flag */
+#define WDT_PERIOD_SEL 0x0018 /* WDT period select (options below) */
+#define WDT_LOCK_EN 0x0004 /* WDT enable */
+#define WDT_EN 0x0002 /* WDT lock enable */
+#define WDT_RST_STB 0x0001 /* WDT reset Strobe */
+
+/* WATCHDOG PERIOD FIELD VALUES */
+
+#define WDT_64MS 0x0003 /* 64.38 ms */
+#define WDT_21MS 0x0002 /* 21.68 ms */
+#define WDT_5MS 0x0001 /* 5.67 ms */
+#define WDT_1MS 0x0000 /* 1.67 ms */
+
+/*********************************************************/
+/* TIMER n REGISTER [R/W] */
+/*********************************************************/
+
+#define TMR0_REG 0xC010 /* Timer 0 Register [R/W] */
+#define TIMER_0 0xC010 /* Alias for BIOS code */
+#define TMR1_REG 0xC012 /* Timer 1 Register [R/W] */
+#define TIMER_1 0xC012 /* Alias for BIOS code */
+
+/*********************************************************/
+/*********************************************************/
+/* USB REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* USB n CONTROL REGISTERS [R/W] */
+/*********************************************************/
+
+#define USB1_CTL_REG 0xC08A /* USB 1 Control Register [R/W] */
+#define SIE1_USB_CONTROL 0xC08A
+
+#define USB2_CTL_REG 0xC0AA /* USB 2 Control Register [R/W] */
+#define SIE2_USB_CONTROL 0xC0AA
+
+/* FIELDS */
+#define B_DP_STAT 0x8000 /* Port B D+ status */
+#define B_DM_STAT 0x4000 /* Port B D- status */
+#define A_DP_STAT 0x2000 /* Port A D+ status */
+#define A_DM_STAT 0x1000 /* Port A D- status */
+#define B_SPEED_SEL 0x0800 /* Port B Speed select (See below) */
+#define A_SPEED_SEL 0x0400 /* Port A Speed select (See below) */
+#define MODE_SEL 0x0200 /* Mode (See below) */
+#define B_RES_EN 0x0100 /* Port B Resistors enable */
+#define A_RES_EN 0x0080 /* Port A Resistors enable */
+#define B_FORCE_SEL 0x0060 /* Port B Force D+/- state (See below) */
+#define A_FORCE_SEL 0x0018 /* Port A Force D+/- state (See below) */
+#define SUSP_EN 0x0004 /* Suspend enable */
+#define B_SOF_EOP_EN 0x0002 /* Port B SOF/EOP enable */
+#define A_SOF_EOP_EN 0x0001 /* Port A SOF/EOP enable */
+
+
+/* USB Control Register1 (0xC08A/0xC0AA) bit mask */
+#define bmHOST_CTL1_SOF0 0x0001
+#define bmHOST_CTL1_SOF1 0x0002
+#define bmHOST_CTL1_SUSPEND 0x0004
+#define bmHOST_CTL1_JKState0 0x0008
+#define bmHOST_CTL1_USBReset0 0x0010
+#define bmHOST_CTL1_JKState1 0x0020
+#define bmHOST_CTL1_USBReset1 0x0040
+#define bmHOST_CTL1_UD0 0x0080
+#define bmHOST_CTL1_UD1 0x0100
+#define bmHOST_CTL1_HOST 0x0200
+#define bmHOST_CTL1_LOA 0x0400
+#define bmHOST_CTL1_LOB 0x0800
+#define bmHOST_CTL1_D0m 0x1000
+#define bmHOST_CTL1_D0p 0x2000
+#define bmHOST_CTL1_D1m 0x4000
+#define bmHOST_CTL1_D1p 0x8000
+
+
+/* MODE FIELD VALUES */
+
+#define HOST_MODE 0x0200 /* Host mode */
+#define DEVICE_MODE 0x0000 /* Device mode */
+
+/* p_SPEED SELECT FIELD VALUES */
+
+#define LOW_SPEED 0xFFFF /* Low speed */
+#define FULL_SPEED 0x0000 /* Full speed */
+
+#define B_SPEED_LOW 0x0800
+#define B_SPEED_FULL 0x0000
+#define A_SPEED_LOW 0x0400
+#define A_SPEED_FULL 0x0000
+
+/* FORCEn FIELD VALUES */
+
+#define FORCE_K 0x0078 /* Force K state on associated port */
+#define FORCE_SE0 0x0050 /* Force SE0 state on associated port */
+#define FORCE_J 0x0028 /* Force J state on associated port */
+#define FORCE_NORMAL 0x0000 /* Don't force associated port */
+
+#define A_FORCE_K 0x0018 /* Force K state on A port */
+#define A_FORCE_SE0 0x0010 /* Force SE0 state on associated port */
+#define A_FORCE_J 0x0008 /* Force J state on associated port */
+#define A_FORCE_NORMAL 0x0000 /* Don't force associated port */
+
+#define B_FORCE_K 0x0060 /* Force K state on associated port */
+#define B_FORCE_SE0 0x0040 /* Force SE0 state on associated port */
+#define B_FORCE_J 0x0020 /* Force J state on associated port */
+#define B_FORCE_NORMAL 0x0000 /* Don't force associated port */
+
+
+/*********************************************************/
+/*********************************************************/
+/* HOST REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* HOST n INTERRUPT ENABLE REGISTER [R/W] */
+/*********************************************************/
+
+#define HOST1_IRQ_EN_REG 0xC08C /* Host 1 Interrupt Enable Register [R/W] */
+#define SIE1_INT_EN_REG 0xC08C
+
+#define HOST2_IRQ_EN_REG 0xC0AC /* Host 2 Interrupt Enable Register [R/W] */
+#define SIE2_INT_EN_REG 0xC0AC
+
+/* FIELDS */
+
+#define VBUS_IRQ_EN 0x8000 /* VBUS Interrupt Enable (Available on HOST1 only) */
+#define ID_IRQ_EN 0x4000 /* ID Interrupt Enable (Available on HOST1 only) */
+#define SOF_EOP_IRQ_EN 0x0200 /* SOF/EOP Interrupt Enable */
+#define B_WAKE_IRQ_EN 0x0080 /* Port B Wake Interrupt Enable */
+#define A_WAKE_IRQ_EN 0x0040 /* Port A Wake Interrupt Enable */
+#define B_CHG_IRQ_EN 0x0020 /* Port B Connect Change Interrupt Enable */
+#define A_CHG_IRQ_EN 0x0010 /* Port A Connect Change Interrupt Enable */
+#define DONE_IRQ_EN 0x0001 /* Done Interrupt Enable */
+
+
+/* Host Interrupt enable (0xC08C/0xC0AC) bit mask */
+#define bmHOST_INTEN_XFERDONE 0x0001
+#define bmHOST_INTEN_INSRMV0 0x0010
+#define bmHOST_INTEN_INSRMV1 0x0020
+#define bmHOST_INTEN_WAKEUP0 0x0040
+#define bmHOST_INTEN_WAKEUP1 0x0080
+#define bmHOST_INTEN_SOFINTR 0x0200
+#define bmHOST_INTEN_IEXP 0x0400
+#define bmHOST_INTEN_OTG_ID 0x4000
+#define bmHOST_INTEN_OTG_44V 0x8000
+
+
+
+/*********************************************************/
+/* HOST n STATUS REGISTER [R/W] */
+/*********************************************************/
+/* In order to clear status for a particular IRQ bit, */
+/* write a '1' to that bit location. */
+/*********************************************************/
+
+#define HOST1_STAT_REG 0xC090 /* Host 1 Status Register [R/W] */
+#define SIE1_INT_STATUS_REG 0xC090
+
+#define HOST2_STAT_REG 0xC0B0 /* Host 2 Status Register [R/W] */
+#define SIE2_INT_STATUS_REG 0xC0B0
+
+/* FIELDS */
+
+#define VBUS_IRQ_FLG 0x8000 /* VBUS Interrupt Request (HOST1 only) */
+#define ID_IRQ_FLG 0x4000 /* ID Interrupt Request (HOST1 only) */
+
+#define SOF_EOP_IRQ_FLG 0x0200 /* SOF/EOP Interrupt Request */
+#define B_WAKE_IRQ_FLG 0x0080 /* Port B Wake Interrupt Request */
+#define A_WAKE_IRQ_FLG 0x0040 /* Port A Wake Interrupt Request */
+#define B_CHG_IRQ_FLG 0x0020 /* Port B Connect Change Interrupt Request */
+#define A_CHG_IRQ_FLG 0x0010 /* Port A Connect Change Interrupt Request */
+#define B_SE0_STAT 0x0008 /* Port B SE0 status */
+#define A_SE0_STAT 0x0004 /* Port A SE0 status */
+#define DONE_IRQ_FLG 0x0001 /* Done Interrupt Request */
+
+/* Host interrupt status register (0xC090/0xC0B0) bit mask */
+#define bmHOST_INT_XFERDONE 0x0001
+#define bmHOST_INT_USBRST0 0x0004
+#define bmHOST_INT_USBRST1 0x0008
+#define bmHOST_INT_INSRMV0 0x0010
+#define bmHOST_INT_INSRMV1 0x0020
+#define bmHOST_INT_WAKEUP0 0x0040
+#define bmHOST_INT_WAKEUP1 0x0080
+#define bmHOST_INT_SOFINTR 0x0200
+#define bmHOST_INT_OTG_ID 0x4000
+#define bmHOST_INT_OTG_44V 0x8000
+
+/*********************************************************/
+/* HOST n CONTROL REGISTERS [R/W] */
+/*********************************************************/
+
+#define HOST1_CTL_REG 0xC080 /* Host 1 Control Register [R/W] */
+#define SIE1_USB_CTRL_REG0 0xC080
+#define SIE1_REG_BASE 0xC080 /* Alias for susb.asm */
+
+
+#define HOST2_CTL_REG 0xC0A0 /* Host 2 Control Register [R/W] */
+#define SIE2_USB_CTRL_REG0 0xC0A0
+#define SIE2_REG_BASE 0xC0A0 /* Alias for susb.asm */
+
+
+/* FIELDS */
+#define PREAMBLE_EN 0x0080 /* Preamble enable */
+#define SEQ_SEL 0x0040 /* Data Toggle Sequence Bit Select (Write next/read last) */
+#define SYNC_EN 0x0020 /* (1:Send next packet at SOF/EOP, 0: Send next packet immediately) */
+#define ISO_EN 0x0010 /* Isochronous enable */
+#define TIMEOUT_SEL 0x0008 /* Timeout select (1:22 bit times, 0:18 bit times) */
+#define DIR_SEL 0x0004 /* Transfer direction (1:OUT, 0:IN) */
+#define EN 0x0002 /* Enable operation */
+#define ARM_EN 0x0001 /* Arm operation */
+#define BSY_FLG 0x0001 /* Busy flag */
+
+/* Use in the 0xc080 and 0xc0a0 */
+#define bmHOST_HCTL_ARM 0x0001
+#define bmHOST_HCTL_ISOCH 0x0010
+#define bmHOST_HCTL_AFTERSOF 0x0020
+#define bmHOST_HCTL_DT 0x0040
+#define bmHOST_HCTL_PREAMBLE 0x0080
+
+
+/*********************************************************/
+/* HOST n ADDRESS REGISTERS [R/W] */
+/*********************************************************/
+
+#define HOST1_ADDR_REG 0xC082 /* Host 1 Address Register [R/W] */
+#define SIE1_USB_BASE_ADDR 0xC082
+
+#define HOST2_ADDR_REG 0xC0A2 /* Host 2 Address Register [R/W] */
+#define SIE2_USB_BASE_ADDR 0xC0A2
+
+/*********************************************************/
+/* HOST n COUNT REGISTERS [R/W] */
+/*********************************************************/
+
+#define HOST1_CNT_REG 0xC084 /* Host 1 Count Register [R/W] */
+#define SIE1_USB_LENGTH 0xC084
+
+
+#define HOST2_CNT_REG 0xC0A4 /* Host 2 Count Register [R/W] */
+#define SIE2_USB_LENGTH 0xC0A4
+
+/* FIELDS */
+#define PORT_SEL 0x4000 /* Port Select (1:PortB, 0:PortA) */
+#define HOST_CNT 0x03FF /* Host Count */
+
+/* Base Length register (0xC084/0xC0A4)bit mask */
+#define bmHOST_PORT_SEL 0x4000
+
+/*********************************************************/
+/* HOST n PID REGISTERS [W] */
+/*********************************************************/
+
+#define HOST1_PID_REG 0xC086 /* Host 1 PID Register [W] */
+#define SIE1_USB_HOST_PID 0xC086
+#define SIE1_USB_ERR_STATUS 0xC086 /* When read */
+
+
+#define HOST2_PID_REG 0xC0A6 /* Host 2 PID Register [W] */
+#define SIE2_USB_HOST_PID 0xC0A6
+#define SIE2_USB_ERR_STATUS 0xC0A6 /* When read */
+
+/* Packet status register (0xC086/0xC0A6)bit mask */
+#define bmHOST_STATMASK_ACK 0x0001
+#define bmHOST_STATMASK_ERROR 0x0002
+#define bmHOST_STATMASK_TMOUT 0x0004
+#define bmHOST_STATMASK_SEQ 0x0008
+#define bmHOST_STATMASK_SETUP 0x0010
+#define bmHOST_STATMASK_OVF 0x0020
+#define bmHOST_STATMASK_NAK 0x0040
+#define bmHOST_STATMASK_STALL 0x0080
+
+/* FIELDS */
+#define PID_SEL 0x00F0 /* Packet ID (see below) */
+#define EP_SEL 0x000F /* Endpoint number */
+
+/* PID FIELD VALUES */
+#define SETUP_PID 0x000D /* SETUP */
+#define IN_PID 0x0009 /* IN */
+#define OUT_PID 0x0001 /* OUT */
+#define SOF_PID 0x0005 /* SOF */
+#define PRE_PID 0x000C /* PRE */
+#define NAK_PID 0x000A /* NAK */
+#define STALL_PID 0x000E /* STALL */
+#define DATA0_PID 0x0003 /* DATA0 */
+#define DATA1_PID 0x000B /* DATA1 */
+
+/*********************************************************/
+/* LYBERTY HOST Define value */
+/*********************************************************/
+#define cPortA 0x0000
+#define cPortB 0x0001
+#define cPortC 0x0002
+#define cPortD 0x0003
+
+#define cPID_SETUP 0x000D
+#define cPID_IN 0x0009
+#define cPID_OUT 0x0001
+#define cPID_SOF 0x0005
+#define cPID_PRE 0x000C
+#define cPID_NAK 0x000A
+#define cPID_STALL 0x000E
+#define cPID_DATA0 0x0003
+#define cPID_DATA1 0x000B
+#define cPID_ACK 0x0002
+
+
+
+
+
+/*********************************************************/
+/* HOST n ENDPOINT STATUS REGISTERS [R] */
+/*********************************************************/
+
+#define HOST1_EP_STAT_REG 0xC086 /* Host 1 Endpoint Status Register [R] */
+#define HOST2_EP_STAT_REG 0xC0A6 /* Host 2 Endpoint Status Register [R] */
+
+/* FIELDS */
+
+#define STALL_FLG 0x0080 /* Device returned STALL */
+#define NAK_FLG 0x0040 /* Device returned NAK */
+#define OVERFLOW_FLG 0x0020 /* Receive overflow */
+#define SEQ_STAT 0x0008 /* Data Toggle value */
+#define TIMEOUT_FLG 0x0004 /* Timeout occurred */
+#define ERROR_FLG 0x0002 /* Error occurred */
+#define ACK_FLG 0x0001 /* Transfer ACK'd */
+
+/*********************************************************/
+/* HOST n DEVICE ADDRESS REGISTERS [W] */
+/*********************************************************/
+
+#define HOST1_DEV_ADDR_REG 0xC088 /* Host 1 Device Address Register [W] */
+#define SIE1_USB_HOST_DEV 0xC088
+#define SIE1_USB_LEFT_BYTE 0xC088 /* When read */
+
+
+#define HOST2_DEV_ADDR_REG 0xC0A8 /* Host 2 Device Address Register [W] */
+#define SIE2_USB_HOST_DEV 0xC0A8
+#define SIE2_USB_LEFT_BYTE 0xC0A8 /* When read */
+
+
+/* FIELDS */
+
+#define DEV_ADDR 0x007F /* Device Address */
+
+/*********************************************************/
+/* HOST n COUNT RESULT REGISTERS [R] */
+/*********************************************************/
+
+#define HOST1_CTR_REG 0xC088 /* Host 1 Counter Register [R] */
+#define HOST2_CTR_REG 0xC0A8 /* Host 2 Counter Register [R] */
+
+/* FIELDS*/
+
+#define HOST_RESULT 0x00FF /* Host Count Result */
+
+/*********************************************************/
+/* HOST n SOF/EOP COUNT REGISTER [R/W] */
+/*********************************************************/
+
+#define HOST1_SOF_EOP_CNT_REG 0xC092 /* Host 1 SOF/EOP Count Register [R/W] */
+#define SIE1_USB_SOF_COUNT 0xC092
+
+#define HOST2_SOF_EOP_CNT_REG 0xC0B2 /* Host 2 SOF/EOP Count Register [R/W] */
+#define SIE2_USB_SOF_COUNT 0xC0B2
+
+/* FIELDS */
+
+#define SOF_EOP_CNT 0x3FFF /* SOF/EOP Count */
+
+/*********************************************************/
+/* HOST n SOF/EOP COUNTER REGISTER [R] */
+/*********************************************************/
+
+#define HOST1_SOF_EOP_CTR_REG 0xC094 /* Host 1 SOF/EOP Counter Register [R] */
+#define SIE1_USB_SOF_TIMER 0xC094
+
+
+#define HOST2_SOF_EOP_CTR_REG 0xC0B4 /* Host 2 SOF/EOP Counter Register [R] */
+#define SIE2_USB_SOF_TIMER 0xC0B4
+
+/* FIELDS */
+
+#define SOF_EOP_CTR 0x3FFF /* SOF/EOP Counter */
+
+/*********************************************************/
+/* HOST n FRAME REGISTER [R] */
+/*********************************************************/
+
+#define HOST1_FRAME_REG 0xC096 /* Host 1 Frame Register [R] */
+#define SIE1_USB_FRAME_NO 0xC096
+
+#define HOST2_FRAME_REG 0xC0B6 /* Host 2 Frame Register [R] */
+#define SIE2_USB_FRAME_NO 0xC0B6
+
+/* FIELDS */
+
+#define HOST_FRAME_NUM 0x07FF /* Frame */
+
+
+/*********************************************************/
+/*********************************************************/
+/* DEVICE REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* DEVICE n PORT SELECT REGISTERS [R/W] */
+/*********************************************************/
+
+#define DEV1_SEL_REG 0xC084 /* Device 1 Port Select Register [R/W] */
+#define DEV2_SEL_REG 0xC0A4 /* Device 2 Port Select Register [R/W] */
+
+/* FIELDS */
+
+/*********************************************************/
+/* DEVICE n INTERRUPT ENABLE REGISTER [R/W] */
+/*********************************************************/
+
+#define DEV1_IRQ_EN_REG 0xC08C /* Device 1 Interrupt Enable Register [R/W] */
+#define DEV2_IRQ_EN_REG 0xC0AC /* Device 2 Interrupt Enable Register [R/W] */
+
+/* FIELDS */
+
+/* Defined in Host Interrupt Enable Register */
+/*#define VBUS_IRQ_EN 0x8000 // VBUS Interrupt Enable (DEV1 only) */
+/*#define ID_IRQ_EN 0x4000 // ID Interrupt Enable (DEV1 only) */
+
+#define WAKE_IRQ_EN 0x0400 /* Wake Interrupt Enable */
+#define RST_IRQ_EN 0x0100 /* Reset Interrupt Enable */
+#define EP7_IRQ_EN 0x0080 /* EP7 Interrupt Enable */
+#define EP6_IRQ_EN 0x0040 /* EP6 Interrupt Enable */
+#define EP5_IRQ_EN 0x0020 /* EP5 Interrupt Enable */
+#define EP4_IRQ_EN 0x0010 /* EP4 Interrupt Enable */
+#define EP3_IRQ_EN 0x0008 /* EP3 Interrupt Enable */
+#define EP2_IRQ_EN 0x0004 /* EP2 Interrupt Enable */
+#define EP1_IRQ_EN 0x0002 /* EP1 Interrupt Enable */
+#define EP0_IRQ_EN 0x0001 /* EP0 Interrupt Enable */
+
+/*********************************************************/
+/* DEVICE n STATUS REGISTER [R/W] */
+/*********************************************************/
+/* In order to clear status for a particular IRQ bit, */
+/* write a '1' to that bit location. */
+/*********************************************************/
+
+#define DEV1_STAT_REG 0xC090 /* Device 1 Status Register [R/W] */
+#define DEV2_STAT_REG 0xC0B0 /* Device 2 Status Register [R/W] */
+
+/* FIELDS */
+
+/* Defined in Host Status Register */
+/*#define VBUS_IRQ_FLG 0x8000 // VBUS Interrupt Request (DEV1 only) */
+/*#define ID_IRQ_FLG 0x4000 // ID Interrupt Request (DEV1 only) */
+/*#define SOF_EOP_IRQ_FLG 0x0200 // SOF/EOP Interrupt Request */
+
+#define WAKE_IRQ_FLG 0x0400 /* Wakeup Interrupt Request */
+#define RST_IRQ_FLG 0x0100 /* Reset Interrupt Request */
+#define EP7_IRQ_FLG 0x0080 /* EP7 Interrupt Request */
+#define EP6_IRQ_FLG 0x0040 /* EP6 Interrupt Request */
+#define EP5_IRQ_FLG 0x0020 /* EP5 Interrupt Request */
+#define EP4_IRQ_FLG 0x0010 /* EP4 Interrupt Request */
+#define EP3_IRQ_FLG 0x0008 /* EP3 Interrupt Request */
+#define EP2_IRQ_FLG 0x0004 /* EP2 Interrupt Request */
+#define EP1_IRQ_FLG 0x0002 /* EP1 Interrupt Request */
+#define EP0_IRQ_FLG 0x0001 /* EP0 Interrupt Request */
+
+/*********************************************************/
+/* DEVICE n ADDRESS REGISTERS [R/W] */
+/*********************************************************/
+
+#define DEV1_ADDR_REG 0xC08E /* Device 1 Address Register [R/W] */
+#define DEV2_ADDR_REG 0xC0AE /* Device 2 Address Register [R/W] */
+
+/* FIELDS */
+
+#define DEV_ADDR_SEL 0x007F /* Device Address */
+
+/*********************************************************/
+/* DEVICE n FRAME NUMBER REGISTER [R] */
+/*********************************************************/
+
+#define DEV1_FRAME_REG 0xC092 /* Device 1 Frame Register [R] */
+#define DEV2_FRAME_REG 0xC0B2 /* Device 2 Frame Register [R] */
+
+/* FIELDS */
+
+#define DEV_FRAME_STAT 0x07FF /* Device Frame */
+
+/*********************************************************/
+/* DEVICE n ENDPOINT n CONTROL REGISTERS [R/W] */
+/*********************************************************/
+
+#define DEV1_EP0_CTL_REG 0x0200 /* Device 1 Endpoint 0 Control Register [R/W] */
+#define DEV1_EP1_CTL_REG 0x0210 /* Device 1 Endpoint 1 Control Register [R/W] */
+#define DEV1_EP2_CTL_REG 0x0220 /* Device 1 Endpoint 2 Control Register [R/W] */
+#define DEV1_EP3_CTL_REG 0x0230 /* Device 1 Endpoint 3 Control Register [R/W] */
+#define DEV1_EP4_CTL_REG 0x0240 /* Device 1 Endpoint 4 Control Register [R/W] */
+#define DEV1_EP5_CTL_REG 0x0250 /* Device 1 Endpoint 5 Control Register [R/W] */
+#define DEV1_EP6_CTL_REG 0x0260 /* Device 1 Endpoint 6 Control Register [R/W] */
+#define DEV1_EP7_CTL_REG 0x0270 /* Device 1 Endpoint 7 Control Register [R/W] */
+
+#define DEV2_EP0_CTL_REG 0x0280 /* Device 2 Endpoint 0 Control Register [R/W] */
+#define DEV2_EP1_CTL_REG 0x0290 /* Device 2 Endpoint 1 Control Register [R/W] */
+#define DEV2_EP2_CTL_REG 0x02A0 /* Device 2 Endpoint 2 Control Register [R/W] */
+#define DEV2_EP3_CTL_REG 0x02B0 /* Device 2 Endpoint 3 Control Register [R/W] */
+#define DEV2_EP4_CTL_REG 0x02C0 /* Device 2 Endpoint 4 Control Register [R/W] */
+#define DEV2_EP5_CTL_REG 0x02D0 /* Device 2 Endpoint 5 Control Register [R/W] */
+#define DEV2_EP6_CTL_REG 0x02E0 /* Device 2 Endpoint 6 Control Register [R/W] */
+#define DEV2_EP7_CTL_REG 0x02F0 /* Device 2 Endpoint 7 Control Register [R/W] */
+
+#define SIE1_DEV_REQ 0x0300 /* SIE1 Default Setup packet Address */
+#define SIE2_DEV_REQ 0x0308 /* SIE2 Default Setup packet Address */
+
+
+/* FIELDS */
+
+/* Defined in Host Control Register */
+#define INOUT_IGN_EN 0x0080 /* Ignores IN and OUT requests on EP0 */
+/*#define SEQ_SEL 0x0040 // Endpoint Data Toggle Sequence Bit */
+#define STALL_EN 0x0020 /* Endpoint Stall */
+/*#define ISO_EN 0x0010 // Enpoint Isochronous enable */
+#define NAK_INT_EN 0x0080 /* NAK Response Interrupt enable */
+/*#define DIR_SEL 0x0004 // Endpoint Direction (1:IN, 0:OUT) */
+/*#define EN 0x0002 // Endpoint enable */
+/*#define ARM_EN 0x0001 // Endpoint arm */
+/*#define BSY_FLG 0x0001 // Start host operation (ARM_BUSY?) */
+
+/*********************************************************/
+/* DEVICE n ENDPOINT n ADDRESS REGISTERS [R/W] */
+/*********************************************************/
+
+#define DEV1_EP0_ADDR_REG 0x0202 /* Device 1 Endpoint 0 Address Register [R/W] */
+#define DEV1_EP1_ADDR_REG 0x0212 /* Device 1 Endpoint 1 Address Register [R/W] */
+#define DEV1_EP2_ADDR_REG 0x0222 /* Device 1 Endpoint 2 Address Register [R/W] */
+#define DEV1_EP3_ADDR_REG 0x0232 /* Device 1 Endpoint 3 Address Register [R/W] */
+#define DEV1_EP4_ADDR_REG 0x0242 /* Device 1 Endpoint 4 Address Register [R/W] */
+#define DEV1_EP5_ADDR_REG 0x0252 /* Device 1 Endpoint 5 Address Register [R/W] */
+#define DEV1_EP6_ADDR_REG 0x0262 /* Device 1 Endpoint 6 Address Register [R/W] */
+#define DEV1_EP7_ADDR_REG 0x0272 /* Device 1 Endpoint 7 Address Register [R/W] */
+
+#define DEV2_EP0_ADDR_REG 0x0282 /* Device 2 Endpoint 0 Address Register [R/W] */
+#define DEV2_EP1_ADDR_REG 0x0292 /* Device 2 Endpoint 1 Address Register [R/W] */
+#define DEV2_EP2_ADDR_REG 0x02A2 /* Device 2 Endpoint 2 Address Register [R/W] */
+#define DEV2_EP3_ADDR_REG 0x02B2 /* Device 2 Endpoint 3 Address Register [R/W] */
+#define DEV2_EP4_ADDR_REG 0x02C2 /* Device 2 Endpoint 4 Address Register [R/W] */
+#define DEV2_EP5_ADDR_REG 0x02D2 /* Device 2 Endpoint 5 Address Register [R/W] */
+#define DEV2_EP6_ADDR_REG 0x02E2 /* Device 2 Endpoint 6 Address Register [R/W] */
+#define DEV2_EP7_ADDR_REG 0x02F2 /* Device 2 Endpoint 7 Address Register [R/W] */
+
+/*********************************************************/
+/* DEVICE n ENDPOINT n COUNT REGISTERS [R/W] */
+/*********************************************************/
+
+#define DEV1_EP0_CNT_REG 0x0204 /* Device 1 Endpoint 0 Count Register [R/W] */
+#define DEV1_EP1_CNT_REG 0x0214 /* Device 1 Endpoint 1 Count Register [R/W] */
+#define DEV1_EP2_CNT_REG 0x0224 /* Device 1 Endpoint 2 Count Register [R/W] */
+#define DEV1_EP3_CNT_REG 0x0234 /* Device 1 Endpoint 3 Count Register [R/W] */
+#define DEV1_EP4_CNT_REG 0x0244 /* Device 1 Endpoint 4 Count Register [R/W] */
+#define DEV1_EP5_CNT_REG 0x0254 /* Device 1 Endpoint 5 Count Register [R/W] */
+#define DEV1_EP6_CNT_REG 0x0264 /* Device 1 Endpoint 6 Count Register [R/W] */
+#define DEV1_EP7_CNT_REG 0x0274 /* Device 1 Endpoint 7 Count Register [R/W] */
+
+#define DEV2_EP0_CNT_REG 0x0284 /* Device 2 Endpoint 0 Count Register [R/W] */
+#define DEV2_EP1_CNT_REG 0x0294 /* Device 2 Endpoint 1 Count Register [R/W] */
+#define DEV2_EP2_CNT_REG 0x02A4 /* Device 2 Endpoint 2 Count Register [R/W] */
+#define DEV2_EP3_CNT_REG 0x02B4 /* Device 2 Endpoint 3 Count Register [R/W] */
+#define DEV2_EP4_CNT_REG 0x02C4 /* Device 2 Endpoint 4 Count Register [R/W] */
+#define DEV2_EP5_CNT_REG 0x02D4 /* Device 2 Endpoint 5 Count Register [R/W] */
+#define DEV2_EP6_CNT_REG 0x02E4 /* Device 2 Endpoint 6 Count Register [R/W] */
+#define DEV2_EP7_CNT_REG 0x02F4 /* Device 2 Endpoint 7 Count Register [R/W] */
+
+/* FIELDS */
+
+#define EP_CNT 0x03FF /* Endpoint Count */
+
+/*********************************************************/
+/* DEVICE n ENDPOINT n STATUS REGISTERS [R/W] */
+/*********************************************************/
+
+#define DEV1_EP0_STAT_REG 0x0206 /* Device 1 Endpoint 0 Status Register [R/W] */
+#define DEV1_EP1_STAT_REG 0x0216 /* Device 1 Endpoint 1 Status Register [R/W] */
+#define DEV1_EP2_STAT_REG 0x0226 /* Device 1 Endpoint 2 Status Register [R/W] */
+#define DEV1_EP3_STAT_REG 0x0236 /* Device 1 Endpoint 3 Status Register [R/W] */
+#define DEV1_EP4_STAT_REG 0x0246 /* Device 1 Endpoint 4 Status Register [R/W] */
+#define DEV1_EP5_STAT_REG 0x0256 /* Device 1 Endpoint 5 Status Register [R/W] */
+#define DEV1_EP6_STAT_REG 0x0266 /* Device 1 Endpoint 6 Status Register [R/W] */
+#define DEV1_EP7_STAT_REG 0x0276 /* Device 1 Endpoint 7 Status Register [R/W] */
+
+#define DEV2_EP0_STAT_REG 0x0286 /* Device 2 Endpoint 0 Status Register [R/W] */
+#define DEV2_EP1_STAT_REG 0x0296 /* Device 2 Endpoint 1 Status Register [R/W] */
+#define DEV2_EP2_STAT_REG 0x02A6 /* Device 2 Endpoint 2 Status Register [R/W] */
+#define DEV2_EP3_STAT_REG 0x02B6 /* Device 2 Endpoint 3 Status Register [R/W] */
+#define DEV2_EP4_STAT_REG 0x02C6 /* Device 2 Endpoint 4 Status Register [R/W] */
+#define DEV2_EP5_STAT_REG 0x02D6 /* Device 2 Endpoint 5 Status Register [R/W] */
+#define DEV2_EP6_STAT_REG 0x02E6 /* Device 2 Endpoint 6 Status Register [R/W] */
+#define DEV2_EP7_STAT_REG 0x02F6 /* Device 2 Endpoint 7 Status Register [R/W] */
+
+/* FIELDS */
+
+#define OUT_EXCEPTION_FLG 0x0200 /* OUT received when armed for IN */
+#define IN_EXCEPTION_FLG 0x0100 /* IN received when armed for OUT */
+/*#define STALL_FLG 0x0080 // Stall sent */
+/*#define NAK_FLG 0x0040 // NAK sent */
+/*#define OVERFLOW_FLG 0x0020 // Count exceeded during receive */
+#define SETUP_FLG 0x0010 /* SETUP packet received */
+/*#define SEQ_STAT 0x0008 // Last Data Toggle Sequence bit sent or received */
+/*#define TIMEOUT_FLG 0x0004 // Last transmission timed out */
+/*#define ERROR_FLG 0x0002 // CRC Error detected in last reception */
+/*#define ACK_FLG 0x0001 // Last transaction ACK'D (sent or received) */
+
+/*********************************************************/
+/* DEVICE n ENDPOINT n COUNT RESULT REGISTERS [R] */
+/*********************************************************/
+
+#define DEV1_EP0_CTR_REG 0x0208 /* Device 1 Endpoint 0 Count Result Register [R] */
+#define DEV1_EP1_CTR_REG 0x0218 /* Device 1 Endpoint 1 Count Result Register [R] */
+#define DEV1_EP2_CTR_REG 0x0228 /* Device 1 Endpoint 2 Count Result Register [R] */
+#define DEV1_EP3_CTR_REG 0x0238 /* Device 1 Endpoint 3 Count Result Register [R] */
+#define DEV1_EP4_CTR_REG 0x0248 /* Device 1 Endpoint 4 Count Result Register [R] */
+#define DEV1_EP5_CTR_REG 0x0258 /* Device 1 Endpoint 5 Count Result Register [R] */
+#define DEV1_EP6_CTR_REG 0x0268 /* Device 1 Endpoint 6 Count Result Register [R] */
+#define DEV1_EP7_CTR_REG 0x0278 /* Device 1 Endpoint 7 Count Result Register [R] */
+
+#define DEV2_EP0_CTR_REG 0x0288 /* Device 2 Endpoint 0 Count Result Register [R] */
+#define DEV2_EP1_CTR_REG 0x0298 /* Device 2 Endpoint 1 Count Result Register [R] */
+#define DEV2_EP2_CTR_REG 0x02A8 /* Device 2 Endpoint 2 Count Result Register [R] */
+#define DEV2_EP3_CTR_REG 0x02B8 /* Device 2 Endpoint 3 Count Result Register [R] */
+#define DEV2_EP4_CTR_REG 0x02C8 /* Device 2 Endpoint 4 Count Result Register [R] */
+#define DEV2_EP5_CTR_REG 0x02D8 /* Device 2 Endpoint 5 Count Result Register [R] */
+#define DEV2_EP6_CTR_REG 0x02E8 /* Device 2 Endpoint 6 Count Result Register [R] */
+#define DEV2_EP7_CTR_REG 0x02F8 /* Device 2 Endpoint 7 Count Result Register [R] */
+
+/* FIELDS */
+
+#define EP_RESULT 0x00FF /* Endpoint Count Result */
+
+
+/*********************************************************/
+/*********************************************************/
+/* OTG REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* OTG CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define OTG_CTL_REG 0xC098 /* On-The-Go Control Register [R/W] */
+
+/* FIELDS */
+
+#define OTG_RX_DIS 0x1000 /* Disable OTG receiver */
+#define CHG_PUMP_EN 0x0800 /* OTG Charge Pump enable */
+#define VBUS_DISCH_EN 0x0400 /* VBUS discharge enable */
+#define DPLUS_PULLUP_EN 0x200 /* DPlus Pullup enable */
+#define DMINUS_PULLUP_EN 0x100 /* DMinus Pullup enable */
+#define DPLUS_PULLDOWN_EN 0x80 /* DPlus Pulldown enable */
+#define DMINUS_PULLDOWN_EN 0x40 /* DMinus Pulldown enable */
+#define OTG_DATA_STAT 0x0004 /* TTL logic state of VBUS pin [R] */
+#define OTG_ID_STAT 0x0002 /* Value of OTG ID pin [R] */
+#define VBUS_VALID_FLG 0x0001 /* VBUS > 4.4V [R] */
+
+
+/*********************************************************/
+/*********************************************************/
+/* GPIO REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* GPIO CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define GPIO_CTL_REG 0xC006 /* GPIO Control Register [R/W] */
+#define GPIO_CONFIG 0xC006
+#define GPIO_CNTRL 0xC01C /* Alias for BIOS code */
+
+/* FIELDS */
+#define GPIO_WP_EN 0x8000 /* GPIO Control Register Write-Protect enable (1:WP) */
+#define GPIO_SAS_EN 0x0800 /* 1:SPI SS to GPIO[15] */
+#define GPIO_MODE_SEL 0x0700 /* GPIO Mode */
+#define GPIO_HSS_EN 0x0080 /* Connect HSS to GPIO (Dependent on TQFP_PKG) */
+/* TQFP: GPIO [26, 18:16] */
+/* FBGA: GPIO[15:12] */
+#define GPIO_HSS_XD_EN 0x0040 /* Connect HSS to XD[15:12] (TQFP only) */
+#define GPIO_SPI_EN 0x0020 /* Connect SPI to GPIO[11:8] */
+#define GPIO_SPI_XD_EN 0x0010 /* Connect SPI to XD[11:8] */
+#define GPIO_IRQ1_POL_SEL 0x0008 /* IRQ1 polarity (1:positive, 0:negative) */
+#define GPIO_IRQ1_EN 0x0004 /* IRQ1 enable */
+#define GPIO_IRQ0_POL_SEL 0x0002 /* IRQ0 polarity (1:positive, 0:negative) */
+#define GPIO_IRQ0_EN 0x0001 /* IRQ0 enable */
+
+/* GPIO MODE FIELD VALUES */
+
+#define DIAG_MODE 0x0007 /* Memory Diagnostic mode */
+#define SCAN_MODE 0x0006 /* Boundary Scan mode */
+#define HPI_MODE 0x0005 /* HPI mode */
+#define IDE_MODE 0x0004 /* IDE mode */
+#define EPP_MODE 0x0002 /* EPP mode */
+#define FLASH_MODE 0x0001 /* FLASH mode */
+#define GPIO_MODE 0x0000 /* GPIO only */
+
+/*********************************************************/
+/* GPIO n REGISTERS */
+/*********************************************************/
+
+#define GPIO0_OUT_DATA_REG 0xC01E /* GPIO 0 Output Data Register [R/W] */
+#define GPIO1_OUT_DATA_REG 0xC024 /* GPIO 1 Output Data Register [R/W] */
+
+#define GPIO0_IN_DATA_REG 0xC020 /* GPIO 0 Input Data Register [R] */
+#define GPIO1_IN_DATA_REG 0xC026 /* GPIO 1 Input Data Register [R] */
+
+#define GPIO0_DIR_REG 0xC022 /* GPIO 0 Direction Register [R/W] (1:Output, 0:Input) */
+#define GPIO1_DIR_REG 0xC028 /* GPIO 1 Direction Register [R/W] (1:Output, 0:Input) */
+#define GPIO_HI_IO 0xC024 /* Alias for BIOS */
+#define GPIO_HI_ENB 0xC028 /* Alias for BIOS */
+
+
+/*********************************************************/
+/*********************************************************/
+/* EPP REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* EPP CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define EPP_CTL_REG 0xC046 /* EPP Control Register [R/W] */
+
+/* FIELDS */
+
+#define EPP_MODE_SEL 0x8000 /* 1: EPP_MODE, 0: COMPATABILITY MODE [R/W] */
+#define EPP_SELECT_STAT 0x4000 /* Returns current logic state of the SELECT pin [R] */
+#define EPP_nFAULT_STAT 0x2000 /* Returns current logic state of the nFAULT pin [R] */
+#define EPP_pERROR_STAT 0x1000 /* Returns current logic state of the pERROR pin [R] */
+
+/* EPP MODE ONLY FIELDS (EPP_MODE_EN = 1) */
+
+#define EPP_nRESET_EN 0x0020 /* Reads/Writes current logic state of the nRESET pin [R/W] */
+#define EPP_nDSTRB_EN 0x0010 /* Reads/Writes current logic state of the nDSTRB pin [R/W] */
+#define EPP_nASTRB_EN 0x0008 /* Reads/Writes current logic state of the nASTRB pin [R/W] */
+#define EPP_nWRITE_EN 0x0004 /* Reads/Writes current logic state of the nWRITE pin [R/W] */
+#define EPP_IRQ_STAT 0x0002 /* ??? [R] */
+#define EPP_WAIT_STAT 0x0001 /* ??? [R] */
+
+/* COMPATABILITY MODE ONLY FIELDS (EPP_MODE_EN = 0) */
+
+#define EPP_nINIT_EN 0x0020 /* ??? [R/W] */
+#define EPP_nAUTOFD_EN 0x0010 /* ??? [R/W] */
+#define EPP_ASELECT_EN 0x0008 /* ??? [R/W] */
+#define EPP_nSTROBE_EN 0x0004 /* ??? [R/W] */
+#define EPP_nACK_STAT 0x0002 /* ??? [R] */
+#define EPP_BUSY_STAT 0x0001 /* ??? [R] */
+
+/*********************************************************/
+/* EPP DATA REGISTER [R/W] */
+/*********************************************************/
+
+#define EPP_DATA_REG 0xC040 /* EPP Data Register [R/W] */
+
+/* FIELDS */
+
+#define EPP_DATA 0x00FF /* EPP Data */
+
+/*********************************************************/
+/* EPP BUFFER READ REGISTER [R] */
+/*********************************************************/
+
+#define EPP_BFR_READ_REG 0xC042 /* EPP Buffer Read Register [R] */
+
+/* FIELDS */
+
+#define EPP_BFR 0x00FF /* EPP Buffer */
+
+/*********************************************************/
+/* EPP ADDRESS REGISTER [R/W] */
+/*********************************************************/
+
+#define EPP_ADDR_REG 0xC044 /* EPP Address Register [R/W] */
+
+/* FIELDS */
+
+#define EPP_ADDR 0x00FF /* EPP Address */
+
+
+/*********************************************************/
+/*********************************************************/
+/* IDE REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* IDE MODE REGISTER [R/W] */
+/*********************************************************/
+
+#define IDE_MODE_REG 0xC048 /* IDE Mode Register [R/W] */
+
+/* FIELDS */
+
+#define IDE_MODE_SEL 0x0007 /* IDE Mode (See field values below) */
+
+/* MODE FIELD VALUES */
+
+#define MODE_DIS 0x0007 /* Disabled */
+#define MODE_PIO4 0x0004 /* PIO Mode 4 */
+#define MODE_PIO3 0x0003 /* PIO Mode 3 */
+#define MODE_PIO2 0x0002 /* PIO Mode 2 */
+#define MODE_PIO1 0x0001 /* PIO Mode 1 */
+#define MODE_PIO0 0x0000 /* PIO Mode 0 */
+
+/*********************************************************/
+/* IDE START ADDRESS REGISTER [R/W] */
+/*********************************************************/
+
+#define IDE_START_ADDR_REG 0xC04A /* IDE Start Address Register [R/W] */
+
+/*********************************************************/
+/* IDE STOP ADDRESS REGISTER [R/W] */
+/*********************************************************/
+
+#define IDE_STOP_ADDR_REG 0xC04C /* IDE Stop Address Register [R/W] */
+
+/*********************************************************/
+/* IDE CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define IDE_CTL_REG 0xC04E /* IDE Control Register [R/W] */
+
+/* FIELDS */
+
+#define IDE_DIR_SEL 0x0008 /* IDE Direction Select */
+#define IDE_IRQ_EN 0x0004 /* IDE Interrupt Enable */
+#define IDE_DONE_FLG 0x0002 /* IDE Done Flag (Set by silicon, Cleared by writing 0) */
+#define IDE_EN 0x0001 /* IDE Enable (Set by writing 1, Cleared by silicon) */
+
+/* DIRECTION SELECT FIELD VALUES */
+
+#define WR_EXT 0x0008 /* Write to external device */
+#define RD_EXT 0x0000 /* Read from external device */
+
+/*********************************************************/
+/* IDE PIO PORT REGISTERS [R/W] */
+/*********************************************************/
+
+#define IDE_PIO_DATA_REG 0xC050 /* IDE PIO Data Register [R/W] */
+#define IDE_PIO_ERR_REG 0xC052 /* IDE PIO Error Register [R/W] */
+#define IDE_PIO_SCT_CNT_REG 0xC054 /* IDE PIO Sector Count Register [R/W] */
+#define IDE_PIO_SCT_NUM_REG 0xC056 /* IDE PIO Sector Number Register [R/W] */
+#define IDE_PIO_CYL_LO_REG 0xC058 /* IDE PIO Cylinder Low Register [R/W] */
+#define IDE_PIO_CYL_HI_REG 0xC05A /* IDE PIO Cylinder High Register [R/W] */
+#define IDE_PIO_DEV_HD_REG 0xC05C /* IDE PIO Device/Head Register [R/W] */
+#define IDE_PIO_CMD_REG 0xC05E /* IDE PIO Command Register [R/W] */
+#define IDE_PIO_DEV_CTL_REG 0xC06C /* IDE PIO Device Control Register [R/W] */
+
+
+/*********************************************************/
+/*********************************************************/
+/* MDMA REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* MDMA MODE REGISTER [R/W] */
+/*********************************************************/
+
+#define MDMA_MODE_REG 0xC048 /* MDMA Mode Register [R/W] */
+
+/* FIELDS */
+
+#define MDMA_PROTOCOL_SEL 0x0008 /* 1:MDMA-B, 0:MDMA-A */
+#define MDMA_MODE_SEL 0x0007 /* MDMA Mode (See field values below) */
+
+/* MDMA MODE FIELD VALUES */
+
+#define MDMA_DIS 0x0007 /* Disabled */
+#define MDMA_16 0x0006 /* MDMA Mode, 16-bit */
+#define MDMA_8 0x0005 /* MDMA Mode, 8-bit */
+
+/*********************************************************/
+/* MDMA START ADDRESS REGISTER [R/W] */
+/*********************************************************/
+
+#define MDMA_START_ADDR_REG 0xC04A /* MDMA Start Address Register [R/W] */
+
+/*********************************************************/
+/* MDMA STOP ADDRESS REGISTER [R/W] */
+/*********************************************************/
+
+#define MDMA_STOP_ADDR_REG 0xC04C /* MDMA Stop Address Register [R/W] */
+
+/*********************************************************/
+/* MDMA CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define MDMA_CTL_REG 0xC04E /* MDMA Control Register [R/W] */
+
+/* FIELDS */
+
+#define MDMA_DIR_SEL 0x0008 /* MDMA Direction Select */
+#define MDMA_IRQ_EN 0x0004 /* MDMA Interrupt Enable */
+#define MDMA_DONE_FLG 0x0002 /* MDMA Done Flag (Set by silicon, Cleared by writing 0) */
+#define MDMA_EN 0x0001 /* MDMA Enable (Set by writing 1, Cleared by silicon) */
+
+
+/*********************************************************/
+/*********************************************************/
+/* HSS REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* HSS CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define HSS_Ctl_REG 0xC070 /* HSS Control Register [R/W] */
+
+/* FIELDS */
+
+#define HSS_EN 0x8000 /* HSS Enable */
+#define RTS_POL_SEL 0x4000 /* RTS Polarity Select */
+#define CTS_POL_SEL 0x2000 /* CTS Polarity Select */
+#define XOFF 0x1000 /* XOFF/XON state (1:XOFF received, 0:XON received) [R] */
+#define XOFF_EN 0x0800 /* XOFF/XON protocol Enable */
+#define CTS_EN 0x0400 /* CTS Enable */
+#define RX_IRQ_EN 0x0200 /* RxRdy/RxPktRdy Interrupt Enable */
+#define HSS_DONE_IRQ_EN 0x0100 /* TxDone/RxDone Interrupt Enable */
+#define TX_DONE_IRQ_FLG 0x0080 /* TxDone Interrupt (Write 1 to clear) */
+#define RX_DONE_IRQ_FLG 0x0040 /* RxDone Interrupt (Write 1 to clear) */
+#define ONE_STOP_BIT 0x0020 /* Number of TX Stop bits (1:one TX stop bit, 0:2 TX stop bits) */
+#define HSS_TX_RDY 0x0010 /* Tx ready for next byte */
+#define PACKET_MODE_SEL 0x0008 /* RxIntr Source (1:RxPktRdy, 0:RxRdy) */
+#define RX_OVF_FLG 0x0004 /* Rx FIFO overflow (Write 1 to clear and flush RX FIFO) */
+#define RX_PKT_RDY_FLG 0x0002 /* RX FIFO full */
+#define RX_RDY_FLG 0x0001 /* RX FIFO not empty */
+
+/* RTS POLARITY SELECT FIELD VALUES */
+
+#define RTS_POL_LO 0x4000 /* Low-true polarity */
+#define RTS_POL_HI 0x0000 /* High-true polarity */
+
+/* CTS POLARITY SELECT FIELD VALUES */
+
+#define CTS_POL_LO 0x2000 /* Low-true polarity */
+#define CTS_POL_HI 0x0000 /* High-true polarity */
+
+/*********************************************************/
+/* HSS BAUD RATE REGISTER [???] */
+/*********************************************************/
+/* Baud rate is determined as follows: */
+/* */
+/* 48 MHz */
+/* -------------- */
+/* (HSS_BAUD + 1) */
+/*********************************************************/
+
+#define HSS_BAUD_REG 0xC072 /* HSS Baud Register [???] */
+
+/* FIELDS */
+
+#define HSS_BAUD_SEL 0x1FFF /* HSS Baud */
+
+/*********************************************************/
+/* HSS TX GAP REGISTER [???] */
+/*********************************************************/
+/* This register defines the number of stop bits used */
+/* for block mode transmission ONLY. The number of stop */
+/* bits is determined as follows: */
+/* */
+/* (TX_GAP - 7) */
+/* */
+/* Valid values for TX_GAP are 8-255. */
+/*********************************************************/
+
+#define HSS_TX_GAP_REG 0xC074 /* HSS Transmit Gap Register [???] */
+
+/* FIELDS */
+
+#define TX_GAP_SEL 0x00FF /* HSS Transmit Gap */
+
+/*********************************************************/
+/* HSS DATA REGISTER [R/W] */
+/*********************************************************/
+
+#define HSS_DATA_REG 0xC076 /* HSS Data Register [R/W] */
+
+/* FIELDS */
+
+#define HSS_DATA 0x00FF /* HSS Data */
+
+/*********************************************************/
+/* HSS RECEIVE ADDRESS REGISTER [???] */
+/*********************************************************/
+
+#define HSS_RX_ADDR_REG 0xC078 /* HSS Receive Address Register [???] */
+
+/*********************************************************/
+/* HSS RECEIVE COUNTER REGISTER [R/W] */
+/*********************************************************/
+
+#define HSS_RX_CTR_REG 0xC07A /* HSS Receive Counter Register [R/W] */
+
+/* FIELDS */
+
+#define HSS_RX_CTR 0x03FF /* Counts from (n-1) to (0-1) */
+
+/*********************************************************/
+/* HSS TRANSMIT ADDRESS REGISTER [???] */
+/*********************************************************/
+
+#define HSS_TX_ADDR_REG 0xC07C /* HSS Transmit Address Register [???] */
+
+/*********************************************************/
+/* HSS TRANSMIT COUNTER REGISTER [R/W] */
+/*********************************************************/
+
+#define HSS_TX_CTR_REG 0xC07E /* HSS Transmit Counter Register [R/W] */
+
+/* FIELDS */
+
+#define HSS_TX_CTR 0x03FF /* Counts from (n-1) to (0-1) */
+
+/* ------------------ HIGH SPEED SERIAL INTERFACE ADDRESS ------------------- */
+/* High Speed Serial Control */
+
+#define HSS_RGN 0xC070
+#define HSS_STS_REG 0xC070
+#define HSS_Ctl_ADR 0xC070
+#define HSS_Ctl_MSK 0x0000
+#define HSS_Ctl_RxRst_BIT 0x0002
+#define HSS_Ctl_RxRst_BM 0x0004
+#define HSS_Ctl_PacketMode_BIT 0x0003
+#define HSS_Ctl_PacketMode_BM 0x0008
+#define HSS_Ctl_OneStop_BIT 0x0005
+#define HSS_Ctl_OneStop_BM 0x0020
+#define HSS_Ctl_RBkDoneClr_BIT 0x0006
+#define HSS_Ctl_RBkDoneClr_BM 0x0040
+#define HSS_Ctl_TBkDoneClr_BIT 0x0007
+#define HSS_Ctl_TBkDoneClr_BM 0x0080
+#define HSS_Ctl_DoneIntrEnab_BIT 0x0008
+#define HSS_Ctl_DoneIntrEnab_BM 0x0100
+#define HSS_Ctl_RxIntrEnab_BIT 0x0009
+#define HSS_Ctl_RxIntrEnab_BM 0x0200
+#define HSS_Ctl_CTSenab_BIT 0x000A
+#define HSS_Ctl_CTSenab_BM 0x0400
+#define HSS_Ctl_XOFFenab_BIT 0x000B
+#define HSS_Ctl_XOFFenab_BM 0x0800
+#define HSS_Ctl_CTSpolarity_BIT 0x000D
+#define HSS_Ctl_CTSpolarity_BM 0x2000
+#define HSS_Ctl_RTSpolarity_BIT 0x000E
+#define HSS_Ctl_RTSpolarity_BM 0x4000
+#define HSS_Ctl_Enable_BIT 0x000F
+#define HSS_Ctl_Enable_BM 0x8000
+#define HSS_Ctl_RxRdy_BIT 0x0000
+#define HSS_Ctl_RxRdy_BM 0x0001
+#define HSS_Ctl_RxPktRdy_BIT 0x0001
+#define HSS_Ctl_RxPktRdy_BM 0x0002
+#define HSS_Ctl_RxErr_BIT 0x0002
+#define HSS_Ctl_RxErr_BM 0x0004
+#define HSS_Ctl_TxRdy_BIT 0x0004
+#define HSS_Ctl_TxRdy_BM 0x0010
+#define HSS_Ctl_RBkDone_BIT 0x0006
+#define HSS_Ctl_RBkDone_BM 0x0040
+#define HSS_Ctl_TBkDone_BIT 0x0007
+#define HSS_Ctl_TBkDone_BM 0x0080
+#define HSS_Ctl_XOFFstate_BIT 0x000C
+#define HSS_Ctl_OFFstate_BM 0x1000
+
+/* High Speed Serial BAUD Rate Register */
+#define HSS_BAUDRATE_REG 0xC072
+#define HSS_BAUDRate_ADR 0xC072
+#define HSS_BAUDRate_MSK 0x0000
+#define HSS_BAUDRate_Rate_POS 0x0000
+#define HSS_BAUDRate_Rate_SIZ 0x000D
+
+/* High Speed Serial GAP Register */
+#define HSS_GAP_REG 0xC074
+#define HSS_GAP_ADR 0xC074
+#define HSS_GAP_MSK 0x0000
+#define HSS_GAP_GAP_POS 0x0000
+#define HSS_GAP_GAP_SIZ 0x0010
+
+/* High Speed Serial Data Register */
+#define HSS_RX_DATA_REG 0xC076
+#define HSS_TX_DATA_REG 0xC076
+#define HSS_Data_ADR 0xC076
+#define HSS_Data_MSK 0x0000
+#define HSS_Data_Data_POS 0x0000
+#define HSS_Data_Data_SIZ 0x0008
+
+/* High Speed Serial Block Receive Address Register */
+#define HSS_RX_BLK_ADDR_REG 0xC078
+#define HSS_RxBlkAddr_ADR 0xC078
+#define HSS_RxBlkAddr_MSK 0x0000
+#define HSS_RxBlkAddr_Addr_POS 0x0000
+#define HSS_RxBlkAddr_Addr_SIZ 0x0010
+
+/* High Speed Serial Block Receive Length Register */
+#define HSS_RX_BLK_LEN_REG 0xC07A
+#define HSS_RxBlkLen_ADR 0xC07A
+#define HSS_RxBlkLen_MSK 0x0000
+#define HSS_RxBlkLen_POS 0x0000
+#define HSS_RxBlkLen_SIZ 0x000A
+
+/* High Speed Serial Block Transmit Address Register */
+#define HSS_TX_BLK_ADDR_REG 0xC07C
+#define HSS_TxBlkAddr_ADR 0xC07C
+#define HSS_TxBlkAddr_MSK 0x0000
+#define HSS_TxBlkAddr_Addr_POS 0x0000
+#define HSS_TxBlkAddr_Addr_SIZ 0x0010
+
+/* High Speed Serial Block Transmit Length Register */
+#define HSS_TX_BLK_LEN_REG 0xC07E
+#define HSS_TxBlkLen_ADR 0xC07E
+#define HSS_TxBlkLen_MSK 0x0000
+#define HSS_TxBlkLen_POS 0x0000
+#define HSS_TxBlkLen_SIZ 0x000A
+
+/*********************************************************/
+/*********************************************************/
+/* SPI REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* SPI CONFIGURATION REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_CFG_REG 0xC0C8 /* SPI Config Register [R/W] */
+
+/* FIELDS */
+
+#define c3WIRE_EN 0x8000 /* MISO/MOSI data lines common */
+#define PHASE_SEL 0x0400 /* Advanced SCK phase */
+#define SCK_POL_SEL 0x2000 /* Positive SCK Polarity */
+#define SCALE_SEL 0x1E00 /* SPI Clock Frequency Scaling */
+#define MSTR_ACTIVE_EN 0x0080 /* Master state machine active */
+#define MSTR_EN 0x0040 /* Master/Slave select */
+#define SS_EN 0x0020 /* SS enable */
+#define SS_DLY_SEL 0x001F /* SS delay select */
+
+/* SCALE VALUES */
+#define SPI_SCALE_1E 0x1E00 /* */
+#define SPI_SCALE_1C 0x1C00 /* */
+#define SPI_SCALE_1A 0x1A00 /* */
+#define SPI_SCALE_18 0x1800 /* */
+#define SPI_SCALE_16 0x1600 /* */
+#define SPI_SCALE_14 0x1400 /* */
+#define SPI_SCALE_12 0x1200 /* */
+#define SPI_SCALE_10 0x1000 /* */
+#define SPI_SCALE_0E 0x0E00 /* */
+#define SPI_SCALE_0C 0x0C00 /* */
+#define SPI_SCALE_0A 0x0A00 /* */
+#define SPI_SCALE_08 0x0800 /* */
+#define SPI_SCALE_06 0x0600 /* */
+#define SPI_SCALE_04 0x0400 /* */
+#define SPI_SCALE_02 0x0200 /* */
+#define SPI_SCALE_00 0x0000 /* */
+
+/*********************************************************/
+/* SPI CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_CTL_REG 0xC0CA /* SPI Control Register [R/W] */
+
+/* FIELDS */
+
+#define SCK_STROBE 0x8000 /* SCK Strobe */
+#define FIFO_INIT 0x4000 /* FIFO Init */
+#define BYTE_MODE 0x2000 /* Byte Mode */
+#define FULL_DUPLEX 0x1000 /* Full Duplex */
+#define SS_MANUAL 0x0800 /* SS Manual */
+#define READ_EN 0x0400 /* Read Enable */
+#define SPI_TX_RDY 0x0200 /* Transmit Ready */
+#define RX_DATA_RDY 0x0100 /* Receive Data Ready */
+#define TX_EMPTY 0x0080 /* Transmit Empty */
+#define RX_FULL 0x0020 /* Receive Full */
+#define TX_BIT_LEN 0x0031 /* Transmit Bit Length */
+#define RX_BIT_LEN 0x0007 /* Receive Bit Length */
+
+/*********************************************************/
+/* SPI INTERRUPT ENABLE REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_IRQ_EN_REG 0xC0CC /* SPI Interrupt Enable Register [R/W] */
+
+/* FIELDS */
+
+#define SPI_RX_IRQ_EN 0x0004 /* SPI Receive Interrupt Enable */
+#define SPI_TX_IRQ_EN 0x0002 /* SPI Transmit Interrupt Enable */
+#define SPI_XFR_IRQ_EN 0x0001 /* SPI Transfer Interrupt Enable */
+
+/*********************************************************/
+/* SPI STATUS REGISTER [R] */
+/*********************************************************/
+
+#define SPI_STAT_REG 0xC0CE /* SPI Status Register [R] */
+
+/* FIELDS */
+
+#define SPI_FIFO_ERROR_FLG 0x0100 /* FIFO Error occurred */
+#define SPI_RX_IRQ_FLG 0x0004 /* SPI Receive Interrupt */
+#define SPI_TX_IRQ_FLG 0x0002 /* SPI Transmit Interrupt */
+#define SPI_XFR_IRQ_FLG 0x0001 /* SPI Transfer Interrupt */
+
+/*********************************************************/
+/* SPI INTERRUPT CLEAR REGISTER [W] */
+/*********************************************************/
+/* In order to clear a particular IRQ, write a '1' to */
+/* the appropriate bit location. */
+/*********************************************************/
+
+#define SPI_IRQ_CLR_REG 0xC0D0 /* SPI Interrupt Clear Register [W] */
+
+/* FIELDS */
+
+#define SPI_TX_IRQ_CLR 0x0002 /* SPI Transmit Interrupt Clear */
+#define SPI_XFR_IRQ_CLR 0x0001 /* SPI Transfer Interrupt Clear */
+
+/*********************************************************/
+/* SPI CRC CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_CRC_CTL_REG 0xC0D2 /* SPI CRC Control Register [R/W] */
+
+/* FIELDS */
+
+#define CRC_MODE 0xC000 /* CRC Mode */
+#define CRC_EN 0x2000 /* CRC Enable */
+#define CRC_CLR 0x1000 /* CRC Clear */
+#define RX_CRC 0x0800 /* Receive CRC */
+#define ONE_IN_CRC 0x0400 /* One in CRC [R] */
+#define ZERO_IN_CRC 0x0200 /* Zero in CRC [R] */
+
+/* CRC MODE VALUES */
+
+#define POLYNOMIAL_3 0x0003 /* CRC POLYNOMIAL 1 */
+#define POLYNOMIAL_2 0x0002 /* CRC POLYNOMIAL X^16+X^15+X^2+1 */
+#define POLYNOMIAL_1 0x0001 /* CRC POLYNOMIAL X^7+X^3+1 */
+#define POLYNOMIAL_0 0x0000 /* CRC POLYNOMIAL X^16+X^12+X^5+1 */
+
+/*********************************************************/
+/* SPI CRC VALUE REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_CRC_VALUE_REG 0xC0D4 /* SPI CRC Value Register [R/W] */
+
+/*********************************************************/
+/* SPI DATA REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_DATA_REG 0xC0D6 /* SPI Data Register [R/W] */
+
+/* FIELDS */
+
+#define SPI_DATA 0x00FF /* SPI Data */
+
+/*********************************************************/
+/* SPI TRANSMIT ADDRESS REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_TX_ADDR_REG 0xC0D8 /* SPI Transmit Address Register [R/W] */
+
+/*********************************************************/
+/* SPI TRANSMIT COUNT REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_TX_CNT_REG 0xC0DA /* SPI Transmit Count Register [R/W] */
+
+/* FIELDS */
+
+#define SPI_TX_CNT 0x07FF /* SPI Transmit Count */
+
+/*********************************************************/
+/* SPI RECEIVE ADDRESS REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_RX_ADDR_REG 0xC0DC /* SPI Receive Address Register [R/W] */
+
+/*********************************************************/
+/* SPI RECEIVE COUNT REGISTER [R/W] */
+/*********************************************************/
+
+#define SPI_RX_CNT_REG 0xC0DE /* SPI Receive Count Register [R/W] */
+
+/* FIELDS */
+
+#define SPI_RX_CNT 0x07FF /* SPI Receive Count */
+#define SPI_RGN 0xC0C0 /* SPI memory map start */
+
+/* SPI registers occupies 0xC0C8 to 0xC0DF. */
+/* so SPI_RGN is set to 0xC0C0. The first register is at offset 0x08. */
+/* The last register 0xC0DE is at offset 0x1e. */
+/* SPI register: Lyberty Address AFE offset from 0xC0C0 */
+/* SPI_RxLen 0xC0DE 0x1e */
+/* SPI_RxBlk 0xC0DC 0x1c */
+/* SPI_TxLen 0xC0DA 0x1a */
+/* SPI_TxBlk 0xC0D8 0x18 */
+/* SPI_TxRxData 0xC0D6 0x16 */
+/* SPI_CRCVal 0xC0D4 0x14 */
+/* SPI_CRCCtl 0xC0D2 0x12 */
+/* SPI_IntClr 0xC0D0 0x10 */
+/* SPI_IntVal 0xC0CE 0x0e */
+/* SPI_IntEnab 0xC0CC 0x0c */
+/* SPI_Ctl 0xC0CA 0x0a */
+/* SPI_Cfg 0xC0C8 0x08 */
+
+
+/* SPI 16-bit Configuration Register */
+/*------------------------------------ */
+#define SPI_Cfg_AFE 0x0008
+#define SPI_Cfg_ADR 0xC0C8
+
+/* b i t d e f i n i t i o n s */
+#define SPI_Cfg_3WireNot4_BIT 0x000F
+#define SPI_Cfg_3WireNot4_BM 0x8000
+#define SPI_Cfg_CPHA_BIT 0x000E
+#define SPI_Cfg_CPHA_BM 0x4000
+#define SPI_Cfg_CPOL_BIT 0x000D
+#define SPI_Cfg_CPOL_BM 0x2000
+/* SPI_Cfg_Sel MSB 12 */
+#define SPI_Cfg_Sel_SIZ 0x0004
+#define SPI_Cfg_Sel_POS 0x0009
+/* possible selections */
+#define SPI_Cfg_Sel_250 0x000B
+#define SPI_Cfg_Sel_250_BM 0x1600
+#define SPI_Cfg_Sel_375 0x000A
+#define SPI_Cfg_Sel_375_BM 0x1400
+#define SPI_Cfg_Sel_500 0x0009
+#define SPI_Cfg_Sel_500_BM 0x1200
+#define SPI_Cfg_Sel_750 0x0008
+#define SPI_Cfg_Sel_750_BM 0x1000
+#define SPI_Cfg_Sel_1000 0x0007
+#define SPI_Cfg_Sel_1000_BM 0x0E00
+#define SPI_Cfg_Sel_1500 0x0006
+#define SPI_Cfg_Sel_1500_BM 0x0C00
+#define SPI_Cfg_Sel_2M 0x0005
+#define SPI_Cfg_Sel_2M_BM 0x0A00
+#define SPI_Cfg_Sel_3M 0x0004
+#define SPI_Cfg_Sel_3M_BM 0x0800
+#define SPI_Cfg_Sel_4M 0x0003
+#define SPI_Cfg_Sel_4M_BM 0x0600
+#define SPI_Cfg_Sel_6M 0x0002
+#define SPI_Cfg_Sel_6M_BM 0x0400
+#define SPI_Cfg_Sel_8M 0x0001
+#define SPI_Cfg_Sel_8M_BM 0x0200
+#define SPI_Cfg_Sel_12M 0x0000
+#define SPI_Cfg_Sel_12M_BM 0x0000
+/* end SPI_Cfg_Sel */
+#define SPI_Cfg_RedLine_BIT 0x0008
+#define SPI_Cfg_RedLine_BM 0x0100
+
+#define SPI_Cfg_MstrActive_BIT 0x0007
+#define SPI_Cfg_MstrActive_BM 0x0080
+#define SPI_Cfg_MstrNotSlv_BIT 0x0006
+#define SPI_Cfg_MstrNotSlv_BM 0x0040
+#define SPI_Cfg_SSEn_BIT 0x0005
+#define SPI_Cfg_SSEn_BM 0x0020
+/* SPI_Cfg_SSDly MSB 4 */
+#define SPI_Cfg_SSDly_SIZ 0x0005
+#define SPI_Cfg_SSDly_POS 0x0000
+/* assign to manual */
+#define SPI_Cfg_SSDly_Manual 0x0000
+/* one possible selection */
+#define SPI_Cfg_SSDly_2 0x0002
+#define SPI_Cfg_SSDly_2_BM 0x0002
+
+
+/* SPI 16-bit Control Register */
+/*------------------------------------ */
+#define SPI_Ctl_AFE 0x000A
+#define SPI_Ctl_ADR 0xC0CA
+
+/* b i t d e f i n i t i o n s */
+#define SPI_Ctl_SCKStrobe_BIT 0x000F
+#define SPI_Ctl_SCKStrobe_BM 0x8000
+#define SPI_Ctl_FIFOInit_BIT 0x000E
+#define SPI_Ctl_FIFOInit_BM 0x4000
+#define SPI_Ctl_ByteMode_BIT 0x000D
+#define SPI_Ctl_ByteMode_BM 0x2000
+#define SPI_Ctl_FullDuplex_BIT 0x000C
+#define SPI_Ctl_FullDuplex_BM 0x1000
+#define SPI_Ctl_SSManVal_BIT 0x000B
+#define SPI_Ctl_SSManVal_BM 0x0800
+#define SPI_Ctl_DoRead_BIT 0x000A
+#define SPI_Ctl_DoRead_BM 0x0400
+#define SPI_Ctl_TxRdy_BIT 0x0009
+#define SPI_Ctl_TxRdy_BM 0x0200
+#define SPI_Ctl_RxDatRdy_BIT 0x0008
+#define SPI_Ctl_RxDatRdy_BM 0x0100
+
+#define SPI_Ctl_TxEmpty_BIT 0x0007
+#define SPI_Ctl_TxEmpty_BM 0x0080
+#define SPI_Ctl_RxFull_BIT 0x0006
+#define SPI_Ctl_RxFull_BM 0x0040
+/* SPI_Ctl_TxBitLen MSB 5 */
+#define SPI_Ctl_TxBitLen_POS 0x0003
+#define SPI_Ctl_TxBitLen_SIZ 0x0003
+
+/* zero is full byte */
+#define SPI_Ctl_TxBitLen_FullByte 0x0000
+#define SPI_Ctl_TxBitLen_FullByte_BM 0x0000
+
+/* SPI_Ctl_RxBitLen MSB 2 */
+#define SPI_Ctl_RxBitLen_POS 0x0000
+#define SPI_Ctl_RxBitLen_SIZ 0x0003
+
+/* zero is full byte */
+#define SPI_Ctl_RxBitLen_FullByte 0x0000
+#define SPI_Ctl_RxBitLen_FullByte_BM 0x0000
+
+
+/* SPI Interrupt Type Bits */
+/* for all Interrupt Registers */
+/* ----------------------------------- */
+#define SPI_Int_XfrBk_BIT 0x0000
+#define SPI_Int_Tx_BIT 0x0001
+#define SPI_Int_Rx_BIT 0x0002
+#define SPI_Int_FIFOErr_BIT 0x0007
+
+/* SPI 16-bit Interrupt Enable Register */
+/*------------------------------------ */
+#define SPI_IntEnab_AFE 0x000C
+#define SPI_IntEnab_ADR 0xC0CC
+
+/* b i t d e f i n i t i o n s */
+/* reserved BITS 15 - 8 */
+
+/* reserved BITS 7 - 3 */
+#define SPI_IntEnab_Rx_BM 0x0004
+#define SPI_IntEnab_Tx_BM 0x0002
+#define SPI_IntEnab_XfrBk_BM 0x0001
+
+
+/* SPI 16-bit Interrupt Value Register */
+/*------------------------------------ */
+#define SPI_IntVal_AFE 0x000E
+#define SPI_IntVal_ADR 0xC0CE
+
+/* b i t d e f i n i t i o n s */
+/* reserved BITS 15 - 8 */
+
+#define SPI_IntVal_FIFOErr_BM 0x0080
+
+/* reserved BITS 6 - 3 */
+#define SPI_IntVal_Rx_BM 0x0004
+#define SPI_IntVal_Tx_BM 0x0002
+#define SPI_IntVal_XfrBk_BM 0x0001
+
+/* SPI 16-bit Interrupt Clear Register */
+/*------------------------------------ */
+#define SPI_IntClr_AFE 0x0010
+#define SPI_IntClr_ADR 0xC0D0
+
+/* b i t d e f i n i t i o n s */
+/* reserved BITS 15 - 8 */
+
+/* reserved BITS 7 - 2 */
+#define SPI_IntClr_Tx_BM 0x0002
+#define SPI_IntClr_XfrBk_BM 0x0001
+
+
+/* SPI 16-bit CRC Control Register */
+/*------------------------------------ */
+#define SPI_CRCCtl_AFE 0x0012
+#define SPI_CRCCtl_ADR 0xC0D2
+
+/* b i t d e f i n i t i o n s */
+/* SPI_CRCCtl MSB 15 */
+#define SPI_CRCCtl_Mode_POS 0x000E
+#define SPI_CRCCtl_Mode_SIZ 0x0002
+
+/* Mode selections MMC (CCITT), */
+/* CRC-7, Memory Stick & Reserved */
+#define SPI_CRCCtl_Mode_MMC 0x0000
+#define SPI_CRCCtl_Mode_MMC_BM 0x0000
+#define SPI_CRCCtl_Mode_CRC7 0x0001
+#define SPI_CRCCtl_Mode_CRC7_BM 0x4000
+#define SPI_CRCCtl_Mode_MS 0x0002
+#define SPI_CRCCtl_Mode_MS_BM 0x8000
+#define SPI_CRCCtl_Mode_Res 0x0003
+#define SPI_CRCCtl_Mode_Res_BM 0xC000
+#define SPI_CRCCtl_Active_BIT 0x000D
+#define SPI_CRCCtl_Active_BM 0x2000
+#define SPI_CRCCtl_Clear_BIT 0x000C
+#define SPI_CRCCtl_Clear_BM 0x1000
+#define SPI_CRCCtl_RxNotTx_BIT 0x000B
+#define SPI_CRCCtl_RxNotTx_BM 0x0800
+#define SPI_CRCCtl_OR_BIT 0x000A
+#define SPI_CRCCtl_OR_BM 0x0400
+#define SPI_CRCCtl_NAND_BIT 0x0009
+#define SPI_CRCCtl_NAND_BM 0x0200
+/* reserved BIT 8 */
+
+/* reserved BITS 7 - 0 */
+
+
+/* SPI 16-bit CRC Value Register */
+/*------------------------------------ */
+#define SPI_CRCVal_AFE 0x0014
+#define SPI_CRCVal_ADR 0xC0D4
+#define SPI_CRCVal_Port_POS 0x0000
+#define SPI_CRCVal_Port_SIZ 0x0010
+
+
+/* SPI 8-bit transmit & receive port (PIO) */
+/*------------------------------------ */
+#define SPI_TxRxData_AFE 0x0016
+#define SPI_TxRxData_ADR 0xC0D6
+#define SPI_TxRxData_Port_POS 0x0000
+#define SPI_TxRxData_Port_SIZ 0x0008
+
+
+/* SPI 16-bit DMA transmit base address */
+/*------------------------------------ */
+#define SPI_TxBlk_AFE 0x0018
+#define SPI_TxBlk_ADR 0xC0D8
+#define SPI_TxBlk_Base_POS 0x0000
+#define SPI_TxBlk_Base_SIZ 0x0010
+
+
+/* SPI 11-bit DMA transmit length */
+/*------------------------------------ */
+#define SPI_TxLen_AFE 0x001A
+#define SPI_TxLen_ADR 0xC0DA
+#define SPI_TxLen_Bytes_POS 0x0000
+#define SPI_TxLen_Bytes_SIZ 0x0010
+
+
+/* SPI 16-bit DMA recieve base address */
+/*------------------------------------ */
+#define SPI_RxBlk_AFE 0x001C
+#define SPI_RxBlk_ADR 0xC0DC
+#define SPI_RxBlk_Base_POS 0x0000
+#define SPI_RxBlk_Base_SIZ 0x0010
+
+
+/* SPI 11-bit DMA recieve length */
+/*------------------------------------ */
+#define SPI_RxLen_AFE 0x001E
+#define SPI_RxLen_ADR 0xC0DE
+#define SPI_RxLen_Bytes_POS 0x0000
+#define SPI_RxLen_Bytes_SIZ 0x0010
+
+/* ------------------------- IDE PIO MODES ---------------------------------- */
+/* IDE Memory Map */
+/* -------------------------------------------------------------------------- */
+#define IDE_RGN 0xC050
+/* IDE 16-bit Data Register */
+#define IDE_Data_ADR 0xC050
+#define IDE_Data_MSK 0x0000
+#define IDE_Data_Data_POS 0x0000
+#define IDE_Data_Data_SIZ 0x0010
+
+/* IDE 8-bit Features/Status Register (write) */
+#define IDE_FeaturesStat_ADR 0xC052
+#define IDE_FeaturesStat_MSK 0x0000
+#define IDE_FeaturesStat_Data_POS 0x0000
+#define IDE_FeaturesStat_Data_SIZ 0x0008
+
+/* IDE Sector Count Register */
+#define IDE_SectCount_ADR 0xC054
+#define IDE_SectCount_MSK 0x0000
+#define IDE_SectCount_Count_POS 0x0000
+#define IDE_SectCount_Count_SIZ 0x0008
+
+/* IDE Sector Number Register */
+#define IDE_SectorNum_ADR 0xC056
+#define IDE_SectorNum_MSK 0x0000
+#define IDE_SectorNum_Count_POS 0x0000
+#define IDE_SectorNum_Count_SIZ 0x0008
+
+/* IDE Cylinder Low Register */
+#define IDE_CylLow_ADR 0xC058
+#define IDE_CylLow_MSK 0x0000
+#define IDE_CylLow_Cyl_POS 0x0000
+#define IDE_CylLow_Cyl_SIZ 0x0008
+
+/* IDE Cylinder High Register */
+#define IDE_CylHigh_ADR 0xC05A
+#define IDE_CylHigh_MSK 0x0000
+#define IDE_CylHigh_Cyl_POS 0x0000
+#define IDE_CylHigh_Cyl_SIZ 0x0008
+
+/* IDE Drive/Head Register */
+#define IDE_DrvHead_ADR 0xC05C
+#define IDE_DrvHead_MSK 0x0000
+#define IDE_DrvHead_Reg_POS 0x0000
+#define IDE_DrvHead_Reg_SIZ 0x0008
+
+/* IDE Command/Status Register */
+#define IDE_CmdStatus_ADR 0xC05E
+#define IDE_CmdStatus_MSK 0x0000
+#define IDE_CmdStatus_Reg_POS 0x0000
+#define IDE_CmdStatus_Reg_SIZ 0x0008
+
+/* IDE Status/Alternate Status Register */
+#define IDE_AltStat_ADR 0xC06C
+#define IDE_AltStat_MSK 0x0000
+#define IDE_AltStat_Reg_POS 0x0000
+#define IDE_AltStat_Reg_SIZ 0x0008
+
+
+/*********************************************************/
+/*********************************************************/
+/* UART REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* UART CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define UART_CTL_REG 0xC0E0 /* UART Control Register [R/W] */
+#define UART_CNTL 0xC0E0 /* Alias for BIOS code */
+
+/* bit mask for 0xc0e2 */
+#define UART_RX_BUFF_FULL 0x0002
+
+/* FIELDS */
+
+#define UART_SCALE_SEL 0x0010 /* UART Scale (1:Divide by 8 prescaler for the UART Clock) */
+#define UART_BAUD_SEL 0x000E /* UART Baud */
+#define UART_EN 0x0001 /* UART Enable */
+
+/* BAUD VALUES */
+
+#define UART_7K2 0x000F /* 7.2K Baud (0.9K with DIV8_EN Set) */
+#define UART_9K6 0x000E /* 9.6K Baud (1.2K with DIV8_EN Set) */
+#define UART_14K4 0x000C /* 14.4K Baud (1.8K with DIV8_EN Set) */
+#define UART_19K2 0x000D /* 19.2K Baud (2.4K with DIV8_EN Set) */
+#define UART_28K8 0x000B /* 28.8K Baud (3.6K with DIV8_EN Set) */
+#define UART_38K4 0x000A /* 38.4K Baud (4.8K with DIV8_EN Set) */
+#define UART_57K6 0x0009 /* 57.6K Baud (7.2K with DIV8_EN Set) */
+#define UART_115K2 0x0008 /* 115.2K Baud (14.4K with DIV8_EN Set) */
+
+/*********************************************************/
+/* UART STATUS REGISTER [R] */
+/*********************************************************/
+
+#define UART_STAT_REG 0xC0E2 /* UART Status Register [R] */
+#define UART_STATUS 0xC0E2
+
+/* FIELDS */
+
+#define UART_RX_FULL 0x0002 /* UART Receive Full */
+#define UART_TX_EMPTY 0x0001 /* UART Transmit Empty */
+
+/*********************************************************/
+/* UART DATA REGISTER [R/W] */
+/*********************************************************/
+
+#define UART_DATA_REG 0xC0E4 /* UART Data Register [R/W] */
+#define UART_RX_REG 0xC0E4 /* Alias for BIOS code */
+#define UART_TX_REG 0xC0E4 /* Alias for BIOS code */
+
+/* FIELDS */
+#define UART_DATA 0x00FF /* UART Data */
+
+
+/*********************************************************/
+/*********************************************************/
+/* PWM REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* PWM CONTROL REGISTER [R/W] */
+/*********************************************************/
+
+#define PWM_CTL_REG 0xC0E6 /* PWM Control Register [R/W] */
+
+/* FIELDS */
+
+#define PWM_EN 0x8000 /* 1:Start, 0:Stop */
+#define PWM_PRESCALE_SEL 0x0E00 /* Prescale field (See values below) */
+#define PWM_MODE_SEL 0x0100 /* 1:Single cycle, 0:Repetitive cycle */
+#define PWM3_POL_SEL 0x0080 /* 1:Positive polarity, 0:Negative polarity */
+#define PWM2_POL_SEL 0x0040 /* 1:Positive polarity, 0:Negative polarity */
+#define PWM1_POL_SEL 0x0020 /* 1:Positive polarity, 0:Negative polarity */
+#define PWM0_POL_SEL 0x0010 /* 1:Positive polarity, 0:Negative polarity */
+#define PWM3_EN 0x0008 /* PWM3 Enable */
+#define PWM2_EN 0x0004 /* PWM2 Enable */
+#define PWM1_EN 0x0002 /* PWM1 Enable */
+#define PWM0_EN 0x0001 /* PWM0 Enable */
+
+/* PRESCALER FIELD VALUES */
+
+#define PWM_5K9 0x0007 /* 5.9 KHz */
+#define PWM_23K5 0x0006 /* 23.5 KHz */
+#define PWM_93K8 0x0005 /* 93.8 KHz */
+#define PWM_375K 0x0004 /* 375 KHz */
+#define PWM_1M5 0x0003 /* 1.5 MHz */
+#define PWM_6M 0x0002 /* 6.0 MHz */
+#define PWM_24M 0x0001 /* 24.0 MHz */
+#define PWM_48M 0x0000 /* 48.0 MHz */
+
+/*********************************************************/
+/* PWM MAXIMUM COUNT REGISTER [R/W] */
+/*********************************************************/
+
+#define PWM_MAX_CNT_REG 0xC0E8 /* PWM Maximum Count Register [R/W] */
+
+/* FIELDS */
+
+#define PWM_MAX_CNT 0x03FF /* PWM Maximum Count */
+
+/*********************************************************/
+/* PWM n START REGISTERS [R/W] */
+/*********************************************************/
+
+#define PWM0_START_REG 0xC0EA /* PWM 0 Start Register [R/W] */
+#define PWM1_START_REG 0xC0EE /* PWM 1 Start Register [R/W] */
+#define PWM2_START_REG 0xC0F2 /* PWM 2 Start Register [R/W] */
+#define PWM3_START_REG 0xC0F6 /* PWM 3 Start Register [R/W] */
+
+/* FIELDS */
+
+#define PWM_START_CNT 0x03FF /* */
+
+/*********************************************************/
+/* PWM n STOP REGISTERS [R/W] */
+/*********************************************************/
+
+#define PWM0_STOP_REG 0xC0EC /* PWM 0 Stop Register [R/W] */
+#define PWM1_STOP_REG 0xC0F0 /* PWM 1 Stop Register [R/W] */
+#define PWM2_STOP_REG 0xC0F4 /* PWM 2 Stop Register [R/W] */
+#define PWM3_STOP_REG 0xC0F8 /* PWM 3 Stop Register [R/W] */
+
+/* FIELDS */
+
+#define PWM_STOP_CNT 0x03FF /* PWM Stop Count */
+
+/*********************************************************/
+/* PWM CYCLE COUNT REGISTER [R/W] */
+/*********************************************************/
+
+#define PWM_CYCLE_CNT_REG 0xC0FA /* PWM Cycle Count Register [R/W] */
+
+
+/*********************************************************/
+/*********************************************************/
+/* HPI REGISTERS */
+/*********************************************************/
+/*********************************************************/
+
+/*********************************************************/
+/* HPI MAILBOX REGISTER [R/W] */
+/*********************************************************/
+
+#define HPI_MBX_REG 0xC0C4 /* HPI Mailbox Register [R/W] */
+
+/*********************************************************/
+/* HPI BREAKPOINT REGISTER [R] */
+/*********************************************************/
+
+#define HPI_BKPT_REG 0x0140 /* HPI Breakpoint Register [R] */
+/*********************************************************/
+/* INTERRUPT ROUTING REGISTER [R] */
+/*********************************************************/
+#define HPI_IRQ_ROUTING_REG 0x0142 /* HPI Interrupt Routing Register [R] */
+#define HPI_SIE_IE 0x0142
+#define HPI_SIE1_MSG_ADR 0x0144
+#define HPI_RESERVED 0x0146
+#define HPI_SIE2_MSG_ADR 0x0148
+
+#define HPI_RGN 0xC0C0 /* base address */
+
+/* HPI DMA Control Register */
+#define HPI_DMACtl_ADR 0xC0C0
+#define HPI_DMACtl_MSK 0x0000
+#define HPI_DMACtl_D0_BIT 0x0000
+#define HPI_DMACtl_D1_BIT 0x0001
+#define HPI_DMACtl_DREQ_BIT 0x0002
+
+/* HPI Mailbox Register */
+#define HPI_MAILBOX_REG 0xC0C6
+#define HPI_MailBox_ADR 0xC0C6
+#define HPI_MailBox_MSK 0x0000
+#define HPI_MailBox_POS 0x0000
+#define HPI_MailBox_SIZ 0x0010
+
+#define VBUS_TO_HPI_EN 0x8000 /* Route OTG VBUS Interrupt to HPI */
+#define ID_TO_HPI_EN 0x4000 /* Route OTG ID Interrupt to HPI */
+// cjv the following two definitions were swapped - I fixed.
+#define SOFEOP2_TO_CPU_EN 0x1000 /* Route SIE2 SOF/EOP Interrupt to CPU */
+#define SOFEOP2_TO_HPI_EN 0x2000 /* Route SIE2 SOF/EOP Interrupt to HPI */
+#define SOFEOP1_TO_CPU_EN 0x0400 /* Route SIE1 SOF/EOP Interrupt to CPU */
+#define SOFEOP1_TO_HPI_EN 0x0800 /* Route SIE1 SOF/EOP Interrupt to HPI */
+#define RST2_TO_HPI_EN 0x0200 /* Route SIE2 Reset Interrupt to HPI */
+#define HPI_SWAP_1_EN 0x0100 /* Swap HPI MSB/LSB */
+#define RESUME2_TO_HPI_EN 0x0080 /* Route SIE2 Resume Interrupt to HPI */
+#define RESUME1_TO_HPI_EN 0x0040 /* Route SIE1 Resume Interrupt to HPI */
+#define DONE2_TO_HPI_EN 0x0008 /* Route SIE2 Done Interrupt to HPI */
+#define DONE1_TO_HPI_EN 0x0004 /* Route SIE1 Done Interrupt to HPI */
+#define RST1_TO_HPI_EN 0x0002 /* Route SIE1 Reset Interrupt to HPI */
+#define HPI_SWAP_0_EN 0x0001 /* Swap HPI MSB/LSB (*MUST MATCH HPI_SWAP_1) */
+
+/* ALIASES */
+
+#define HOST2_SOEOP_TO_HPI_EN 0x1000 /* Host 2 SOF/EOP Interrupt */
+#define HOST1_SOFEOP_TO_HPI_EN 0x0400 /* Host 1 SOF/EOP Interrupt */
+#define DEVICE2_SOFEOP_TO_HPI_EN 0x1000 /* Device 2 SOF/EOP Interrupt */
+#define DEVICE1_SOFEOP_TO_HPI_EN 0x0400 /* Device 1 SOF/EOP Interrupt */
+
+#define HOST2_SOFEOP_TO_CPU_EN 0x2000 /* Host 2 SOF/EOP Interrupt */
+#define HOST1_SOFEOP_TO_CPU_EN 0x0800 /* Host 1 SOF/EOP Interrupt */
+#define DEVICE2_SOFEOP_TO_CPU_EN 0x2000 /* Device 2 SOF/EOP Interrupt */
+#define DEVICE1_SOFEOP_TO_CPU_EN 0x0800 /* Device 1 SOF/EOP Interrupt */
+
+#define HOST2_RESUME_TO_HPI_EN 0x0080 /* Host 2 Resume Interrupt */
+#define HOST1_RESUME_TO_HPI_EN 0x0040 /* Host 1 Resume Interrupt */
+#define DEVICE2_RESUME_TO_HPI_EN 0x0080 /* Device 2 Resume Interrupt */
+#define DEVICE1_RESUME_TO_HPI_EN 0x0040 /* Device 1 Resume Interrupt */
+
+#define HOST2_DONE_TO_HPI_EN 0x0008 /* Host 2 Done Interrupt */
+#define HOST1_DONE_TO_HPI_EN 0x0004 /* Host 1 Done Interrupt */
+#define DEVICE2_DONE_TO_HPI_EN 0x0008 /* Device 2 Done Interrupt */
+#define DEVICE1_DONE_TO_HPI_EN 0x0004 /* Device 1 Done Interrupt */
+
+#define HOST2_RESET_TO_HPI_EN 0x0200 /* Host 2 Reset Interrupt */
+#define HOST1_RESET_TO_HPI_EN 0x0002 /* Host 1 Reset Interrupt */
+#define DEVICE2_RESET_TO_HPI_EN 0x0200 /* Device 2 Reset Interrupt */
+#define DEVICE1_RESET_TO_HPI_EN 0x0002 /* Device 1 Reset Interrupt */
+
+/*********************************************************/
+/*********************************************************/
+/* HPI PORTS */
+/*********************************************************/
+/*********************************************************/
+
+//#define HPI_BASE 0x0000
+
+/*********************************************************/
+/* HPI DATA PORT */
+/*********************************************************/
+
+#define HPI_DATA_PORT 0x0000 /* HPI Data Port */
+
+/*********************************************************/
+/* HPI ADDRESS PORT */
+/*********************************************************/
+
+#define HPI_ADDR_PORT 0x0002 /* HPI Address Port */
+
+/*********************************************************/
+/* HPI MAILBOX PORT */
+/*********************************************************/
+
+#define HPI_MBX_PORT 0x0001 /* HPI Mailbox Port */
+
+/*********************************************************/
+/* HPI STATUS PORT */
+/*********************************************************/
+
+/*
+** The HPI Status port is only accessible by an external host over the
+** HPI interface. It is accessed by performing an HPI read at the HPI
+** base address + 3.
+*/
+
+#define HPI_STAT_PORT 0x0003 /* HPI Status Port */
+
+#define VBUS_FLG 0x8000 /* OTG VBUS Interrupt */
+#define ID_FLG 0x4000 /* OTG ID Interrupt */
+#define SOFEOP2_FLG 0x1000 /* Host 2 SOF/EOP Interrupt */
+#define SOFEOP1_FLG 0x0400 /* Host 1 SOF/EOP Interrupt */
+#define RST2_FLG 0x0200 /* Host 2 Reset Interrupt */
+#define MBX_IN_FLG 0x0100 /* Message in pending (awaiting CPU read) */
+#define RESUME2_FLG 0x0080 /* Host 2 Resume Interrupt */
+#define RESUME1_FLG 0x0040 /* Host 1 Resume Interrupt */
+#define DONE2_FLG 0x0008 /* Host 2 Done Interrupt */
+#define DONE1_FLG 0x0004 /* Host 1 Done Interrupt */
+#define RST1_FLG 0x0002 /* Host 1 Reset Interrupt */
+#define MBX_OUT_FLG 0x0001 /* Message out available (awaiting external host read) */
+
+/* Aliases */
+
+#define HOST2_SOF_EOP_FLG 0x1000 /* Host 2 SOF/EOP Interrupt */
+#define HOST1_SOF_EOP_FLG 0x0400 /* Host 1 SOF/EOP Interrupt */
+#define DEV2_SOF_EOP_FLG 0x1000 /* Device 2 SOF/EOP Interrupt */
+#define DEV1_SOF_EOP_FLG 0x0400 /* Device 1 SOF/EOP Interrupt */
+
+#define HOST2_RST_FLG 0x0200 /* Host 2 Reset Interrupt */
+#define HOST1_RST_FLG 0x0002 /* Host 1 Reset Interrupt */
+#define DEV2_RST_FLG 0x0200 /* Device 2 Reset Interrupt */
+#define DEV1_RST_FLG 0x0002 /* Device 1 Reset Interrupt */
+
+#define HOST2_RESUME_FLG 0x0080 /* Host 2 Resume Interrupt */
+#define HOST1_RESUME_FLG 0x0040 /* Host 1 Resume Interrupt */
+#define DEV2_RESUME_FLG 0x0080 /* Device 2 Resume Interrupt */
+#define DEV1_RESUME_FLG 0x0040 /* Device 1 Resume Interrupt */
+
+#define HOST2_DONE_FLG 0x0008 /* Host 2 Done Interrupt */
+#define HOST1_DONE_FLG 0x0004 /* Host 1 Done Interrupt */
+#define DEV2_DONE_FLG 0x0008 /* Device 2 Done Interrupt */
+#define DEV1_DONE_FLG 0x0004 /* Device 1 Done Interrupt */
+
+/*===============================================================*/
+/* usb.inc */
+/* */
+/* A header containing the SL16R slave SIE registers */
+/* Updated 8/16/01 For SIE1 and SIE2 New Address Assigned */
+/*===============================================================*/
+
+#define O_SIE_CTRL0 0x0000
+#define O_SIE_BASE 0x0002
+#define O_SIE_LENGTH 0x0004
+#define O_SIE_PORT_SEL 0x0004
+#define O_SIE_PID 0x0006
+#define O_SIE_CTRL5 0x000A
+#define O_SIE_INT_EN 0x000C
+#define O_SIE_USB_ADDR 0x000E
+#define O_SIE_INT_STATUS 0x0010
+#define O_SIE_SOF_LO 0x0012
+#define O_SIE_PORT_SPD_SEL 0x0012 /* slave mode */
+#define O_SIE_SOF_HI 0x0014
+
+/* Endpoint Register Offsets */
+#define O_EP_BANK 0x0010 /* to EP bank offset */
+
+/* SIE Bases and Offsets */
+#define NUM_EP_PER_SIE 0x0008
+#define O_SIE1_EP_BASE 0x0000
+#define O_SIE2_EP_BASE 0x0080
+
+#define SIE_EP_BASE 0x0200
+#define SIE1_EP_BASE 0x0200
+#define SIE2_EP_BASE 0x0280
+
+/* Bank Offsets wrt SIE Base */
+
+#define O_EP0_BANK 0x0000
+#define O_EP1_BANK 0x0010
+#define O_EP2_BANK 0x0020
+#define O_EP3_BANK 0x0030
+#define O_EP4_BANK 0x0040
+#define O_EP5_BANK 0x0050
+#define O_EP6_BANK 0x0060
+#define O_EP7_BANK 0x0070
+
+/* SIE1 SLAVE EP Register Bank Base Addresses */
+#define SIE1_EP0_BASE 0x0200
+#define SIE1_EP1_BASE 0x0210
+#define SIE1_EP2_BASE 0x0220
+#define SIE1_EP3_BASE 0x0230
+#define SIE1_EP4_BASE 0x0240
+#define SIE1_EP5_BASE 0x0250
+#define SIE1_EP6_BASE 0x0260
+#define SIE1_EP7_BASE 0x0270
+
+/* SIE2 SLAVE EP Register Bank Base Addresses */
+#define SIE2_EP0_BASE 0x0280
+#define SIE2_EP1_BASE 0x0290
+#define SIE2_EP2_BASE 0x02A0
+#define SIE2_EP3_BASE 0x02B0
+#define SIE2_EP4_BASE 0x02C0
+#define SIE2_EP5_BASE 0x02D0
+#define SIE2_EP6_BASE 0x02E0
+#define SIE2_EP7_BASE 0x02F0
+
+/* Endpoint Register Offsets */
+#define O_EP_CONTROL 0x0000
+#define O_EP_BASE_ADDR 0x0002
+#define O_EP_BASE_LENGTH 0x0004
+#define O_EP_PACKET_STAT 0x0006 /* Read */
+#define O_EP_XFER_COUNT 0x0008 /* Read */
+
+/* Generic Processing EP data */
+#define O_EP_MAX_BYTES 0x000A
+#define O_EP_GF_BYTES_LEFT 0x000C
+#define O_EP_P_GF 0x000E
+
+
+/* Endpoint Control Register Bitmasks */
+#define bmEP_CTRL_STICKY 0x0080
+#define bmEP_CTRL_DATA1 0x0040
+#define bmEP_CTRL_STALL 0x0020
+#define bmEP_CTRL_ISO 0x0010
+#define bmEP_CTRL_NDS_B 0x0008
+#define bmEP_CTRL_DIR_IN 0x0004
+#define bmEP_CTRL_ENB 0x0002
+#define bmEP_CTRL_ARM 0x0001
+#define bmEP_CTRL_EP 0x0070
+#define EP_CTRL_OUT 0x0000
+
+/* Endpoint Packet Status Register Bitmasks */
+#define bmEP_PSR_ACK 0x0001
+#define bmEP_PSR_ERR 0x0002
+#define bmEP_PSR_TO 0x0004
+#define bmEP_PSR_DAT1 0x0008
+#define bmEP_PSR_SETUP 0x0010
+#define bmEP_PSR_OVERFLOW 0x0020
+#define bmEP_PSR_NAK 0x0040
+#define bmEP_PSR_STALL 0x0080
+#define bmEP_PSR_IN_ERR 0x0100
+#define bmEP_PSR_OUT_ERR 0x0200
+
+
+/* SIE Interrupt Status/Enable Register Bitmasks */
+#define bmISR_EP0 0x0001
+#define bmISR_EP1 0x0002
+#define bmISR_EP2 0x0004
+#define bmISR_EP3 0x0008
+#define bmISR_EP4 0x0010
+#define bmISR_EP5 0x0020
+#define bmISR_EP6 0x0040
+#define bmISR_EP7 0x0080
+
+#define bmISR_USB_RESET 0x0100
+#define bmISR_SOF 0x0200
+#define bmISR_WAKEUP 0x0400
+
+
+#define bmISR_USBA 0x0001
+#define bmISR_ALL 0x0F6F
+
+/* SIE#_USB_CONTROL Bitmasks */
+#define bmCTRL_USB_ENABLE 0x0001
+#define bmCTRL_SUSPEND 0x0004
+
+#define bmCTRL_STANDBY 0x0040
+#define bmCTRL_PULLUP_AC 0x0080
+#define bmCTRL_PULLUP_BD 0x0100
+#define bmCTRL_HOST_MODE 0x0200
+#define bmCTRL_PORTAC_LOWSPD 0x0400
+#define bmCTRL_PORTBD_LOWSPD 0x0800
+#define CTRL_SLAVE_MODE 0x0000
+
+/* Force State Bits 3,4 */
+#define bmCTRL_FORCE_NORMAL 0x0000
+#define bmCTRL_FORCE_SEO 0x0010
+#define bmCTRL_FORCE_K 0x0018
+#define bmCTRL_FORCE_J 0x0008
+
+/* Port Speed Bitmasks SIE#_USB_PORT_SPEED */
+#define bmPSPD_LOW_SPEED_AC 0x4000
+#define bmPSPD_LOW_SPEED_BD 0x8000
+#define PSPD_FULL_SPEED 0x0000
+
+/* Port Select Bitmasks */
+#define bmPSEL_BD 0x4000
+#define PSEL_AC 0x0000
+
+/* generic definitions for BIOS */
+#define SUSB_NUM_EPS_ALL 0x0010
+#define SUSB_NUM_EPS_PER_SIE 0x0008
+
+/*----------------------------------------- */
+/* */
+/* Chapter 9 Definitions */
+/*----------------------------------------- */
+/* Device Requests */
+#define DR_GET_STATUS 0x0000
+#define DR_CLEAR_FEATURE 0x0001
+#define DR_SET_FEATURE 0x0003
+#define DR_SET_ADDRESS 0x0005
+#define DR_GET_DESCRIPTOR 0x0006
+#define DR_SET_DESCRIPTOR 0x0007
+#define DR_GET_CONFIG 0x0008
+#define DR_SET_CONFIG 0x0009
+#define DR_GET_INTERFACE 0x0010
+#define DR_SET_INTERFACE 0x0011
+
+/* Device Request Offsets */
+#define O_DR_REQTYPE 0x0000
+#define O_DR_REQ 0x0001
+#define O_DR_VALUE 0x0002
+#define O_DR_VALUE_LOBYTE 0x0002
+#define O_DR_VALUE_HIBYTE 0x0003
+#define O_DR_INDEX 0x0004
+#define O_DR_LEN 0x0006
+
+/* Descriptor Types */
+#define DEVICE 0x0001
+#define CONFIGURATION 0x0002
+#define STRING 0x0003
+#define INTERFACE 0x0004
+#define ENDPOINT 0x0005
+
+
+/* Request Type Bitmasks */
+#define bmRT_DEVICE2HOST 0x0080
+#define bmRT_VENDOR_REQ 0x0040 /*Request Type */
+#define bmRT_CLASS_REQ 0x0020
+#define bmRT_INTERFACE 0x0001
+#define bmRT_ENDPOINT 0x0002
+#define bmRT_RECIPIENT_BITS 0x000F
+#define RT_DEVICE 0x0000
+
+/* Endpoint Types */
+#define EP_TYPE_CONTROL 0x0000
+#define EP_TYPE_ISO 0x0001
+#define EP_TYPE_BULK 0x0002
+#define EP_TYPE_INT 0x0003
+
+/* BIOS Specific Default Configuration Definitions */
+#define EP0_BUFFER_LEN 0x0040
+#define EP1_BUFFER_LEN 0x0040
+#define EP2_BUFFER_LEN 0x0040
+
+/* SUSB ERROR CODES */
+#define SUSB_ERR_NONE 0x0000
+#define SUSB_ERR_OUT_OF_RANGE 0x0001
+#define SUSB_ERR_WRONG_DIR 0x0002
+#define SUSB_ERR_NULL_FRAME 0x0003
+#define SUSB_ERR_BAD_TRANS_TYPE 0x0004
+#define SUSB_ERR_OVERFLOW 0x0005
+#define SUSB_ERR_SETUP_TERMINATION 0x0006
+#define SUSB_ERR_EP_Q_FULL 0x0007
+#define SUSB_ERR_EP_STALLED 0x0008
+#define SUSB_ERR_EP_NOT_ENABLED 0x0009
+#define SUSB_ERR_BAD_STATE_REQ 0x000A
+
+/* Generic Ep - endpoint bitmask to indicate */
+/* internal call to Generic EP where */
+/* regs are already loaded */
+#define bmGENEP_REGS_LOADED 0x8000
+
+/* Device Descriptor Offsets */
+#define O_DD_LENGTH 0x0000
+#define O_DD_TYPE 0x0001
+#define O_DD_USB_VERSION 0x0002
+#define O_DD_CLASS 0x0004
+#define O_DD_SUBCLASS 0x0005
+#define O_DD_PROTOCOL 0x0006
+#define O_DD_EP0_MAX_BYTES 0x0007
+#define O_DD_VID 0x0008
+#define O_DD_PID 0x000A
+#define O_DD_DEVICE_VERSION 0x000C
+#define O_DD_MFR_STRING_IDX 0x000E
+#define O_DD_PRODUCT_STRING_IDX 0x000F
+#define O_DD_SN 0x0010
+#define O_DD_NUM_CONFIGS 0x0011
+
+/* Configuration Descriptor Byte Offsets */
+#define O_CD_LENGTH 0x0000
+#define O_CD_TYPE 0x0001
+#define O_CD_TOTAL_LENGTH 0x0002
+#define O_CD_NUM_IFS 0x0004
+#define O_CD_CONFIG_NUM 0x0005
+#define O_CD_STRING_IDX 0x0006
+#define O_CD_ATTRIBUTES 0x0007
+#define O_CD_MAX_POWER 0x0008
+
+/* Configuration Descriptor Attribute Bitmasks */
+#define bmCDATTR_RSVD 0x001F
+#define bmCDATTR_RWAKEUP 0x0020
+#define bmCDATTR_SELF_PWR 0x0040
+#define bmCDATTR_BUS_PWR 0x0080
+
+/* Interface Descriptor Byte Offsets */
+#define O_ID_LENGTH 0x0000
+#define O_ID_TYPE 0x0001
+#define O_ID_IF_NUM 0x0002
+#define O_ID_ALT_SETTING 0x0003
+#define O_ID_NUM_EPS 0x0004
+#define O_ID_IF_CLASS 0x0005
+#define O_ID_IF_SUBCLASS 0x0006
+#define O_ID_IF_PROTO 0x0007
+#define O_ID_STRING_IDX 0x0008
+
+/* Endpoint Descriptor Byte Offsets */
+#define O_ED_LENGTH 0x0000
+#define O_ED_TYPE 0x0001
+#define O_ED_ADDRESS 0x0002
+#define O_ED_ATTRIBUTES 0x0003
+#define O_ED_MAX_BYTES 0x0004
+#define O_ED_ITERVAL 0x0006
+
+#define O_SD_LENGTH 0x0000
+#define O_SD_TYPE 0x0001
+
+/* EP Descriptor Address Bitmasks */
+#define bmEDADDR_EP_NUM 0x0007
+#define bmEDADDR_UNUSED 0x0070
+#define bmEDADDR_DIR_IN 0x0080
+
+/* EP Descriptor Attribute Bitmasks */
+#define bmEDATTR_CONTROL 0x0000
+#define bmEDATTR_ISO 0x0001
+#define bmEDATTR_BULK 0x0010
+#define bmEDATTR_INT 0x0011
+#define bmEDATTR_UNUSED 0x00FC
+
+/* GetStatus Bitmasks */
+#define bmGS_REMOTE_WAKEUP 0x0002
+#define bmGS_SELF_POWERED 0x0001
+#define bmGS_EP_HALT 0x0001
+
+/* Feature Selectors */
+#define F_SEL_EP_HALT 0x0000
+#define F_SEL_RMT_WAKEUP 0x0001
+#define F_SEL_TEST_MODE 0x0002
+
+/* SUSB Device States */
+#define SUSB_STATE_DEFAULT 0x0000
+#define SUSB_STATE_ADDRESSED 0x000C
+#define SUSB_STATE_CONFIGD 0x0018
+
+/*********************************************************/
+/* Hardware/Software Interrupt vectors */
+/*********************************************************/
+/* ========= HARWDARE INTERRUPTS =========== */
+#define TIMER0_INT 0x0000
+#define TIMER0_VEC 0x0000 /* Vector location */
+#define TIMER1_INT 0x0001
+#define TIMER1_VEC 0x0002
+
+#define GP_IRQ0_INT 0x0002
+#define GP_IRQ0_VEC 0x0004
+#define GP_IRQ1_INT 0x0003
+#define GP_IRQ1_VEC 0x0006
+
+#define UART_TX_INT 0x0004
+#define UART_TX_VEC 0x0008
+#define UART_RX_INT 0x0005
+#define UART_RX_VEC 0x000A
+
+
+#define HSS_BLK_DONE_INT 0x0006
+#define HSS_BLK_DONE_VEC 0x000C
+#define HSS_RX_FULL_INT 0x0007
+#define HSS_RX_FULL_VEC 0x000E
+
+#define IDE_DMA_DONE_INT 0x0008
+#define IDE_DMA_DONE_VEC 0x0010
+
+#define Reserved9 0x0009
+
+#define HPI_MBOX_RX_FULL_INT 0x000A
+#define HPI_MBOX_RX_FULL_VEC 0x0014
+#define HPI_MBOX_TX_EMPTY_INT 0x000B
+#define HPI_MBOX_TX_EMPTY_VEC 0x0016
+
+#define SPI_TX_INT 0x000C
+#define SPI_TX_VEC 0x0018
+#define SPI_RX_INT 0x000D
+#define SPI_RX_VEC 0x001A
+#define SPI_DMA_DONE_INT 0x000E
+#define SPI_DMA_DONE_VEC 0x001C
+
+#define OTG_ID_VBUS_VALID_INT 0x000F
+#define OTG_ID_VBUS_VALID_VEC 0x001E
+
+#define SIE1_HOST_DONE_INT 0x0010
+#define SIE1_HOST_DONE_VEC 0x0020
+#define SIE1_HOST_SOF_INT 0x0011
+#define SIE1_HOST_SOF_VEC 0x0022
+#define SIE1_HOST_INS_REM_INT 0x0012
+#define SIE1_HOST_INS_REM_VEC 0x0024
+
+#define Reserved19 0x0013
+
+#define SIE1_SLAVE_RESET_INT 0x0014
+#define SIE1_SLAVE_RESET_VEC 0x0028
+#define SIE1_SLAVE_SOF_INT 0x0015
+#define SIE1_SLAVE_SOF_VEC 0x002A
+
+#define Reserved22 0x0016
+#define Reserved23 0x0017
+
+#define SIE2_HOST_DONE_INT 0x0018
+#define SIE2_HOST_DONE_VEC 0x0030
+#define SIE2_HOST_SOF_INT 0x0019
+#define SIE2_HOST_SOF_VEC 0x0032
+#define SIE2_HOST_INS_REM_INT 0x001A
+#define SIE2_HOST_INS_REM_VEC 0x0034
+
+#define Reserved27 0x001B
+
+#define SIE2_SLAVE_RESET_INT 0x001C
+#define SIE2_SLAVE_RESET_VEC 0x0038
+#define SIE2_SLAVE_SOF_INT 0x001D
+#define SIE2_SLAVE_SOF_VEC 0x003A
+
+#define Reserved30 0x001E
+#define Reserved31 0x001F
+
+#define SIE1_EP0_INT 0x0020
+#define SIE1_EP0_VEC 0x0040
+#define SIE1_EP1_INT 0x0021
+#define SIE1_EP1_VEC 0x0042
+#define SIE1_EP2_INT 0x0022
+#define SIE1_EP2_VEC 0x0044
+#define SIE1_EP3_INT 0x0023
+#define SIE1_EP3_VEC 0x0046
+#define SIE1_EP4_INT 0x0024
+#define SIE1_EP4_VEC 0x0048
+#define SIE1_EP5_INT 0x0025
+#define SIE1_EP5_VEC 0x004A
+#define SIE1_EP6_INT 0x0026
+#define SIE1_EP6_VEC 0x004C
+#define SIE1_EP7_INT 0x0027
+#define SIE1_EP7_VEC 0x004E
+
+#define SIE2_EP0_INT 0x0028
+#define SIE2_EP0_VEC 0x0050
+#define SIE2_EP1_INT 0x0029
+#define SIE2_EP1_VEC 0x0052
+#define SIE2_EP2_INT 0x002A
+#define SIE2_EP2_VEC 0x0054
+#define SIE2_EP3_INT 0x002B
+#define SIE2_EP3_VEC 0x0056
+#define SIE2_EP4_INT 0x002C
+#define SIE2_EP4_VEC 0x0058
+#define SIE2_EP5_INT 0x002D
+#define SIE2_EP5_VEC 0x005A
+#define SIE2_EP6_INT 0x002E
+#define SIE2_EP6_VEC 0x005C
+#define SIE2_EP7_INT 0x002F
+#define SIE2_EP7_VEC 0x005E
+
+/*********************************************************/
+/* Interrupts 48 - 63 are reserved for future HW */
+/*********************************************************/
+/* ========= SOFTWARE INTERRUPTS =========== */
+
+#define I2C_INT 0x0040
+#define LI2C_INT 0x0041
+#define UART_INT 0x0042
+#define SCAN_INT 0x0043
+#define ALLOC_INT 0x0044
+#define IDLE_INT 0x0046
+#define IDLER_INT 0x0047
+#define INSERT_IDLE_INT 0x0048
+#define PUSHALL_INT 0x0049
+#define POPALL_INT 0x004A
+#define FREE_INT 0x004B
+#define REDO_ARENA 0x004C
+#define HW_SWAP_REG 0x004D
+#define HW_REST_REG 0x004E
+#define SCAN_DECODE_INT 0x004F
+
+/*********************************************************/
+/* -- INTs 80 to 115 for SUSB --- */
+/*********************************************************/
+#define SUSB1_SEND_INT 0x0050
+#define SUSB1_RECEIVE_INT 0x0051
+#define SUSB1_STALL_INT 0x0052
+#define SUSB1_STANDARD_INT 0x0053
+#define SUSB1_STANDARD_LOADER_VEC 0x00A8
+#define SUSB1_VENDOR_INT 0x0055
+#define SUSB1_VENDOR_LOADER_VEC 0x00AC
+#define SUSB1_CLASS_INT 0x0057
+#define SUSB1_CLASS_LOADER_VEC 0x00B0
+#define SUSB1_FINISH_INT 0x0059
+#define SUSB1_DEV_DESC_VEC 0x00B4
+#define SUSB1_CONFIG_DESC_VEC 0x00B6
+#define SUSB1_STRING_DESC_VEC 0x00B8
+#define SUSB1_PARSE_CONFIG_INT 0x005D
+#define SUSB1_LOADER_INT 0x005E
+#define SUSB1_DELTA_CONFIG_INT 0x005F
+
+#define SUSB2_SEND_INT 0x0060
+#define SUSB2_RECEIVE_INT 0x0061
+#define SUSB2_STALL_INT 0x0062
+#define SUSB2_STANDARD_INT 0x0063
+#define SUSB2_STANDARD_LOADER_VEC 0x00C8
+#define SUSB2_VENDOR_INT 0x0065
+#define SUSB2_VENDOR_LOADER_VEC 0x00CC
+#define SUSB2_CLASS_INT 0x0067
+#define SUSB2_CLASS_LOADER_VEC 0x00D0
+#define SUSB2_FINISH_INT 0x0069
+#define SUSB2_DEV_DESC_VEC 0x00D4
+#define SUSB2_CONFIG_DESC_VEC 0x00D6
+#define SUSB2_STRING_DESC_VEC 0x00D8
+#define SUSB2_PARSE_CONFIG_INT 0x006D
+#define SUSB2_LOADER_INT 0x006E
+#define SUSB2_DELTA_CONFIG_INT 0x006F
+#define USB_INIT_INT 0x0070
+#define SUSB_INIT_INT 0x0071
+#define REMOTE_WAKEUP_INT 0x0077
+#define START_SRP_INT 0x0078
+
+/* SW INT OFFSETS */
+/* _VEC suffix indicates value is an address */
+/* _INT suffix indicates the sw INT value (1/2 of address) */
+#define SUSB2_SWINT_BASE 0x00C0
+#define SUSB1_SWINT_BASE 0x00A0
+#define SUSB_SWINT_BASE 0x00A0
+#define O_SWINT_SUSB1 0x0000
+#define O_SWINT_SUSB2 0x0020
+
+#define O_SWINT_SEND 0x0000
+#define O_SWINT_RECEIVE 0x0002
+#define O_SWINT_STALL 0x0004
+#define O_SWINT_STANDARD 0x0006
+#define O_SWINT_STD_LDR 0x0008
+#define O_SWINT_VENDOR_INT 0x000A
+#define O_SWINT_VENDOR_LDR 0x000C
+#define O_SWINT_CLASS 0x000E
+#define O_SWINT_CLASS_LDR 0x0010
+#define O_SWINT_FINISH 0x0012
+#define O_SWINT_DEV_DESC 0x0014
+#define O_SWINT_CONFIG_DESC 0x0016
+#define O_SWINT_STRING_DESC 0x0018
+#define O_SWINT_PARSE_CONFIG 0x001A
+#define O_SWINT_LDR 0x001C
+#define O_SWINT_DELTA_CONFIG 0x001E
+
+/*********************************************************/
+/* --- 114 - 117 for Host SW INT's --- */
+/*********************************************************/
+#define HUSB_SIE1_INIT_INT 0x0072
+#define HUSB_SIE2_INIT_INT 0x0073
+#define HUSB_RESET_INT 0x0074
+
+#define SUSB1_OTG_DESC_VEC 0x00EE
+#define PWR_DOWN_INT 0x0078
+
+/*********************************************************/
+/* -- CMD Processor INTs --- */
+/*********************************************************/
+#define SEND_HOST_CMD_INT 0x0079
+#define PROCESS_PORT_CMD_INT 0x007A
+#define PROCESS_CRB_INT 0x007B
+
+/*********************************************************/
+/*--- INT 125, 126 and 127 for Debugger ---- */
+/*********************************************************/
+
+
+
+#endif
+
diff --git a/software/usb/src/io_handler.c b/software/usb/src/io_handler.c
new file mode 100644
index 0000000000000000000000000000000000000000..79905d3d434209f893f8cd0e3facded5413cc2a8
--- /dev/null
+++ b/software/usb/src/io_handler.c
@@ -0,0 +1,43 @@
+//io_handler.c
+#include "io_handler.h"
+#include <stdio.h>
+#include "alt_types.h"
+#include "system.h"
+
+#define otg_hpi_address (volatile int*) OTG_HPI_ADDRESS_BASE
+#define otg_hpi_data (volatile int*) OTG_HPI_DATA_BASE
+#define otg_hpi_r (volatile char*) OTG_HPI_R_BASE
+#define otg_hpi_cs (volatile char*) OTG_HPI_CS_BASE //FOR SOME REASON CS BASE BEHAVES WEIRDLY MIGHT HAVE TO SET MANUALLY
+#define otg_hpi_w (volatile char*) OTG_HPI_W_BASE
+
+
+void IO_init(void)
+{
+ *otg_hpi_cs = 0;
+ *otg_hpi_r = 1;
+ *otg_hpi_w = 1;
+ *otg_hpi_address = 0;
+ *otg_hpi_data = 0;
+}
+
+void IO_write(alt_u8 Address, alt_u16 Data)
+{
+ *otg_hpi_cs = 0;
+ *otg_hpi_r = 1;
+ *otg_hpi_address = Address;
+ *otg_hpi_data = Data;
+ *otg_hpi_w = 0;
+ *otg_hpi_w = 1;
+}
+
+alt_u16 IO_read(alt_u8 Address)
+{
+ alt_u16 ret;
+ *otg_hpi_cs = 0;
+ *otg_hpi_address = Address;
+ *otg_hpi_w = 1;
+ *otg_hpi_r = 0;
+ ret = *otg_hpi_data;
+ *otg_hpi_r = 1;
+ return ret;
+}
diff --git a/software/usb/src/io_handler.h b/software/usb/src/io_handler.h
new file mode 100644
index 0000000000000000000000000000000000000000..4916b00cb0209db644e5c90da7dde2a42b1d3fa6
--- /dev/null
+++ b/software/usb/src/io_handler.h
@@ -0,0 +1,10 @@
+#ifndef IO_HANDLER_H_
+#define IO_HANDLER_H_
+#include "alt_types.h"
+
+void IO_write(alt_u8 Address, alt_u16 Data);
+alt_u16 IO_read(alt_u8 Address);
+void IO_init(void);
+
+
+#endif
diff --git a/software/usb/src/lcp_cmd.h b/software/usb/src/lcp_cmd.h
new file mode 100644
index 0000000000000000000000000000000000000000..46a409de6e92fa6f05e149f0aa73e9f28b21365d
--- /dev/null
+++ b/software/usb/src/lcp_cmd.h
@@ -0,0 +1,101 @@
+#ifndef __Generatedlcp_cmd_
+#define __Generatedlcp_cmd_
+
+/*
+ * This file is machine generated as part of CDS.
+ *
+ * DO NOT EDIT!
+ *
+ * Generated on 01/31/2003, 13:41:00
+ * by program "cds2inc" version 1.15 Beta
+ * from source file "lcp_cmd.cds".
+ *
+ */
+
+/************************************************************ */
+/* LCP COMMUNICATION EQUATES - Common for HPI, HSS and SPI */
+/************************************************************ */
+/* THESE DEFINITIONS DEFINE THE LYBERTY CONTROL PROTOCOL (LCP) */
+/* SBN: Jan/28/03 Update Host/Slave SIEx Message codde handle */
+/* SBN: Jan/26/03 Remove CRB code */
+
+
+/* ====== Default DTL Ports and CMDS ====== */
+#define PORT_CMD_PROC 0x0000
+
+/* --- CMDS --- */
+#define CP_GET_PORT_LIST 0x0000
+#define CP_SINGLE_PORT_MODE 0x0001 /*-- One port at a time access */
+#define CP_MULTI_PORT_MODE 0x0002 /*-- Multiple Ports Active at a time */
+
+#define PORT_HUSB 0x0001 /* SIE1/SIE2 and USB_A-USB_D controlled via CMDs */
+
+#define PORT_SUSB 0x0002 /* SIE1/SIE2 and USB_A-USB_D controlled via CMDs */
+
+#define PORT_SPI 0x0003
+
+#define PORT_HSS 0x0004
+
+#define PORT_IDE 0x0005
+
+#define PORT_HPI 0x0006 /* HPI Master Mode DMA and MailBox control */
+
+#define PORT_DRAM 0x0007
+
+
+/* ====== HOST TO LYBERTY PORT COMMAND EQUATES ====== */
+
+/* -- CMDs common to all ports -- */
+#define COMM_RESET 0xFA50
+#define COMM_JUMP2CODE 0xCE00 /* CE = CMD Equate */
+#define COMM_EXEC_INT 0xCE01
+#define COMM_READ_CTRL_REG 0xCE02
+#define COMM_WRITE_CTRL_REG 0xCE03
+#define COMM_CALL_CODE 0xCE04
+#define COMM_READ_XMEM 0xCE05 /* Can access IRAM too but uses a small buffer */
+#define COMM_WRITE_XMEM 0xCE06 /* compared to READ_MEM and WRITE_MEM */
+#define COMM_CONFIG 0xCE07 /* Uses COMM_BAUD_RATE to change HSS BaudRate etc */
+
+/* -- CMDs for HSS and SPI -- */
+#define COMM_READ_MEM 0xCE08 /* Addr and Len sent as part of CMD packet */
+#define COMM_WRITE_MEM 0xCE09 /* Addr and Len sent as part of CMD packet */
+
+/* ====== LYBERTY TO HOST RESPONSE AND COMMAND EQUATES ====== */
+/* ----- Response Equates should Use 0xCxxx, 0xDxxx, 0xExxx, 0xFxxx --- */
+/* General Responses */
+#define COMM_ACK 0x0FED /* I ate it just fine. */
+#define COMM_NAK 0xDEAD /* Sorry I'm not feeling well. */
+
+/* Message for SIE1 and SIE2 in register 0x144 and 0x148 */
+#define SUSB_EP0_MSG 0x0001
+#define SUSB_EP1_MSG 0x0002
+#define SUSB_EP2_MSG 0x0004
+#define SUSB_EP3_MSG 0x0008
+#define SUSB_EP4_MSG 0x0010
+#define SUSB_EP5_MSG 0x0020
+#define SUSB_EP6_MSG 0x0040
+#define SUSB_EP7_MSG 0x0080
+#define SUSB_RST_MSG 0x0100
+#define SUSB_SOF_MSG 0x0200
+#define SUSB_CFG_MSG 0x0400 /* send these flags to external processor */
+#define SUSB_SUS_MSG 0x0800
+#define SUSB_VBUS_MSG 0x8000
+#define SUSB_ID_MSG 0x4000
+
+/* ----- Commands To Host (HPI Only) ----- (use -0x00xx - 0x0Fxx) where top byte is Port Num) */
+/* NDX new bit map for Host in both register 0x144 and 0x148 */
+#define HUSB_TDListDone 0x1000 /*TDListDone message */
+
+/* Sharing bits */
+#define HUSB_SOF 0x2000 /*SOF message */
+#define HUSB_ARMV 0x0001 /*Device Remove message */
+#define HUSB_AINS_FS 0x0002 /*Full Speed Device Insert message */
+#define HUSB_AINS_LS 0x0004 /*Low Speed Device Insert message */
+#define HUSB_AWakeUp 0x0008 /*WakeUp message */
+#define HUSB_BRMV 0x0010 /*Device Remove message */
+#define HUSB_BINS_FS 0x0020 /*Full Speed Device Insert message */
+#define HUSB_BINS_LS 0x0040 /*Low Speed Device Insert message */
+#define HUSB_BWakeUp 0x0080 /*WakeUp message */
+
+
+#endif /* __Generatedlcp_cmd_ */
diff --git a/software/usb/src/lcp_data.h b/software/usb/src/lcp_data.h
new file mode 100644
index 0000000000000000000000000000000000000000..5857912c32a3add9ede34d3c06c2d1ea5d545d99
--- /dev/null
+++ b/software/usb/src/lcp_data.h
@@ -0,0 +1,79 @@
+#ifndef __Generatedlcp_data_
+#define __Generatedlcp_data_
+
+/*
+ * This file is machine generated as part of CDS.
+ *
+ * DO NOT EDIT!
+ *
+ * Generated on 01/31/2003, 13:41:14
+ * by program "cds2inc" version 1.15 Beta
+ * from source file "lcp_data.cds".
+ *
+ */
+
+/************************************************************ */
+/* Lyberty Data Pointers for Common Data Area */
+/************************************************************ */
+/* SBN: Jan/27/03 update for new LCP code */
+
+#define _start_of_comm 0x019A
+#define lcp_table 0x019A /* COMM_TRANSPORT */
+#define snd_msg 0x019C /* common send msg routine */
+#define lcp_sema 0x019E /* lcp_semaphore */
+#define lcp_chain 0x01A0 /* chain for lcp idle loop */
+#define lcp_rsp 0x01A2 /* CommConfig: location 0x1a4-0x1ae are free */
+
+
+/* -----Memory adress for send the TD list pointer and Semaphore in USB HOST */
+/* -----OWNER: NDX. */
+#define HUSB_SIE1_pCurrentTDPtr 0x01B0 /* Address to SIE1 current TD pointer */
+#define HUSB_SIE2_pCurrentTDPtr 0x01B2 /* Address to SIE2 current TD pointer */
+#define HUSB_pEOT 0x01B4 /* Address to End Of Transfer */
+#define HUSB_SIE1_pTDListDone_Sem 0x01B6 /* Address to SIE1 TD List Done semaphore */
+#define HUSB_SIE2_pTDListDone_Sem 0x01B8 /* Address to SIE2 TD List Done semaphore */
+
+/* ===== CMD DATA AREA - UNION for ALL COMMANDS ============ */
+/* --- 8 byte HSS/SPI FIFO Data goes in here --- */
+#define COMM_PORT_CMD 0x01BA
+#define COMM_PORT_DATA 0x01BC /* Generic Ptr to CMD data in HSS FIFO */
+
+/* -- DATA UNION FOR SIMPLE PORT CMDS -- */
+#define COMM_MEM_ADDR 0x01BC /* -- For COMM_RD/WR_MEM */
+#define COMM_MEM_LEN 0x01BE /* -- For COMM_RD/WR_MEM */
+#define COMM_LAST_DATA 0x01C0 /* -- UNUSED but HSS FiFo can handle this last data */
+
+#define COMM_CTRL_REG_ADDR 0x01BC /* -- For COMM_RD/WR_CTRL_REG */
+#define COMM_CTRL_REG_DATA 0x01BE /* -- For COMM_RD/WR_CTRL_REG */
+#define COMM_CTRL_REG_LOGIC 0x01C0 /* -- User to AND/OR Reg */
+#define REG_WRITE_FLG 0x0000
+#define REG_AND_FLG 0x0001
+#define REG_OR_FLG 0x0002
+
+#define COMM_BAUD_RATE 0x01BC /* -- For COMM_SET_BAUD in scalar units for the given I/F */
+#define COMM_TIMEOUT 0x01BE /* -- For using Timerout on Sending Response to host. */
+#define COMM_CODE_ADDR 0x01BC /* -- For COMM_CALL_CODE and COMM_JUMP2CODE */
+
+/* !!! NOTE: For HSS/SPI all of the above are sent in FIFO */
+/* For HPI done with HW Access. */
+/* --- Register Buffers for EXEC_INT Commands */
+#define COMM_INT_NUM 0x01C2 /* -- For COMM_EXEC_INT */
+#define COMM_R0 0x01C4 /* This data struct must be written via MEM_WRITE commands for HSS and SPI */
+#define COMM_R1 0x01C6
+#define COMM_R2 0x01C8
+#define COMM_R3 0x01CA
+#define COMM_R4 0x01CC
+#define COMM_R5 0x01CE
+#define COMM_R6 0x01D0
+#define COMM_R7 0x01D2
+#define COMM_R8 0x01D4
+#define COMM_R9 0x01D6
+#define COMM_R10 0x01D8
+#define COMM_R11 0x01DA
+#define COMM_R12 0x01DC
+#define COMM_R13 0x01DE
+
+/*============================================================= */
+/* BIOS free memory area: 0x1E0 - 0x1FE */
+
+#endif /* __Generatedlcp_data_ */
diff --git a/software/usb/src/main.c b/software/usb/src/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..9071444fad1f6bcd28fd06a8b32155c026498e1a
--- /dev/null
+++ b/software/usb/src/main.c
@@ -0,0 +1,565 @@
+/*---------------------------------------------------------------------------
+ -- main.c --
+ -- Christine Chen --
+ -- Ref. DE2-115 Demonstrations by Terasic Technologies Inc. --
+ -- Fall 2014 --
+ -- --
+ -- For use with ECE 298 Experiment 7 --
+ -- UIUC ECE Department --
+ ---------------------------------------------------------------------------*/
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <io.h>
+#include <fcntl.h>
+
+#include "system.h"
+#include "alt_types.h"
+#include <unistd.h> // usleep
+#include "sys/alt_irq.h"
+#include "io_handler.h"
+
+#include "cy7c67200.h"
+#include "usb.h"
+#include "lcp_cmd.h"
+#include "lcp_data.h"
+
+
+//----------------------------------------------------------------------------------------//
+//
+// Main function
+//
+//----------------------------------------------------------------------------------------//
+int main(void)
+{
+ IO_init();
+
+ /*while(1)
+ {
+ IO_write(HPI_MAILBOX,COMM_EXEC_INT);
+ printf("[ERROR]:routine mailbox data is %x\n",IO_read(HPI_MAILBOX));
+ //UsbWrite(0xc008,0x000f);
+ //UsbRead(0xc008);
+ usleep(10*10000);
+ }*/
+
+ alt_u16 intStat;
+ alt_u16 usb_ctl_val;
+ static alt_u16 ctl_reg = 0;
+ static alt_u16 no_device = 0;
+ alt_u16 fs_device = 0;
+ int keycode = 0;
+ alt_u8 toggle = 0;
+ alt_u8 data_size;
+ alt_u8 hot_plug_count;
+ alt_u16 code;
+
+ printf("USB keyboard setup...\n\n");
+
+ //----------------------------------------SIE1 initial---------------------------------------------------//
+ USB_HOT_PLUG:
+ UsbSoftReset();
+
+ // STEP 1a:
+ UsbWrite (HPI_SIE1_MSG_ADR, 0);
+ UsbWrite (HOST1_STAT_REG, 0xFFFF);
+
+ /* Set HUSB_pEOT time */
+ UsbWrite(HUSB_pEOT, 600); // adjust the according to your USB device speed
+
+ usb_ctl_val = SOFEOP1_TO_CPU_EN | RESUME1_TO_HPI_EN;// | SOFEOP1_TO_HPI_EN;
+ UsbWrite(HPI_IRQ_ROUTING_REG, usb_ctl_val);
+
+ intStat = A_CHG_IRQ_EN | SOF_EOP_IRQ_EN ;
+ UsbWrite(HOST1_IRQ_EN_REG, intStat);
+ // STEP 1a end
+
+ // STEP 1b begin
+ UsbWrite(COMM_R0,0x0000);//reset time
+ UsbWrite(COMM_R1,0x0000); //port number
+ UsbWrite(COMM_R2,0x0000); //r1
+ UsbWrite(COMM_R3,0x0000); //r1
+ UsbWrite(COMM_R4,0x0000); //r1
+ UsbWrite(COMM_R5,0x0000); //r1
+ UsbWrite(COMM_R6,0x0000); //r1
+ UsbWrite(COMM_R7,0x0000); //r1
+ UsbWrite(COMM_R8,0x0000); //r1
+ UsbWrite(COMM_R9,0x0000); //r1
+ UsbWrite(COMM_R10,0x0000); //r1
+ UsbWrite(COMM_R11,0x0000); //r1
+ UsbWrite(COMM_R12,0x0000); //r1
+ UsbWrite(COMM_R13,0x0000); //r1
+ UsbWrite(COMM_INT_NUM,HUSB_SIE1_INIT_INT); //HUSB_SIE1_INIT_INT
+ IO_write(HPI_MAILBOX,COMM_EXEC_INT);
+
+ while (!(IO_read(HPI_STATUS) & 0xFFFF) ) //read sie1 msg register
+ {
+ }
+ while (IO_read(HPI_MAILBOX) != COMM_ACK)
+ {
+ printf("[ERROR]:routine mailbox data is %x\n",IO_read(HPI_MAILBOX));
+ goto USB_HOT_PLUG;
+ }
+ // STEP 1b end
+
+ printf("STEP 1 Complete");
+ // STEP 2 begin
+ UsbWrite(COMM_INT_NUM,HUSB_RESET_INT); //husb reset
+ UsbWrite(COMM_R0,0x003c);//reset time
+ UsbWrite(COMM_R1,0x0000); //port number
+ UsbWrite(COMM_R2,0x0000); //r1
+ UsbWrite(COMM_R3,0x0000); //r1
+ UsbWrite(COMM_R4,0x0000); //r1
+ UsbWrite(COMM_R5,0x0000); //r1
+ UsbWrite(COMM_R6,0x0000); //r1
+ UsbWrite(COMM_R7,0x0000); //r1
+ UsbWrite(COMM_R8,0x0000); //r1
+ UsbWrite(COMM_R9,0x0000); //r1
+ UsbWrite(COMM_R10,0x0000); //r1
+ UsbWrite(COMM_R11,0x0000); //r1
+ UsbWrite(COMM_R12,0x0000); //r1
+ UsbWrite(COMM_R13,0x0000); //r1
+
+ IO_write(HPI_MAILBOX,COMM_EXEC_INT);
+
+ while (IO_read(HPI_MAILBOX) != COMM_ACK)
+ {
+ printf("[ERROR]:routine mailbox data is %x\n",IO_read(HPI_MAILBOX));
+ goto USB_HOT_PLUG;
+ }
+ // STEP 2 end
+
+ ctl_reg = USB1_CTL_REG;
+ no_device = (A_DP_STAT | A_DM_STAT);
+ fs_device = A_DP_STAT;
+ usb_ctl_val = UsbRead(ctl_reg);
+
+ if (!(usb_ctl_val & no_device))
+ {
+ for(hot_plug_count = 0 ; hot_plug_count < 5 ; hot_plug_count++)
+ {
+ usleep(5*1000);
+ usb_ctl_val = UsbRead(ctl_reg);
+ if(usb_ctl_val & no_device) break;
+ }
+ if(!(usb_ctl_val & no_device))
+ {
+ printf("\n[INFO]: no device is present in SIE1!\n");
+ printf("[INFO]: please insert a USB keyboard in SIE1!\n");
+ while (!(usb_ctl_val & no_device))
+ {
+ usb_ctl_val = UsbRead(ctl_reg);
+ if(usb_ctl_val & no_device)
+ goto USB_HOT_PLUG;
+
+ usleep(2000);
+ }
+ }
+ }
+ else
+ {
+ /* check for low speed or full speed by reading D+ and D- lines */
+ if (usb_ctl_val & fs_device)
+ {
+ printf("[INFO]: full speed device\n");
+ }
+ else
+ {
+ printf("[INFO]: low speed device\n");
+ }
+ }
+
+
+
+ // STEP 3 begin
+ //------------------------------------------------------set address -----------------------------------------------------------------
+ UsbSetAddress();
+
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ UsbSetAddress();
+ usleep(10*1000);
+ }
+
+ UsbWaitTDListDone();
+
+ IO_write(HPI_ADDR,0x0506); // i
+ printf("[ENUM PROCESS]:step 3 TD Status Byte is %x\n",IO_read(HPI_DATA));
+
+ IO_write(HPI_ADDR,0x0508); // n
+ usb_ctl_val = IO_read(HPI_DATA);
+ printf("[ENUM PROCESS]:step 3 TD Control Byte is %x\n",usb_ctl_val);
+ while (usb_ctl_val != 0x03) // retries occurred
+ {
+ usb_ctl_val = UsbGetRetryCnt();
+
+ goto USB_HOT_PLUG;
+ }
+
+ printf("------------[ENUM PROCESS]:set address done!---------------\n");
+
+ // STEP 4 begin
+ //-------------------------------get device descriptor-1 -----------------------------------//
+ // TASK: Call the appropriate function for this step.
+ UsbGetDeviceDesc1(); // Get Device Descriptor -1
+
+ //usleep(10*1000);
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ // TASK: Call the appropriate function again if it wasn't processed successfully.
+ UsbGetDeviceDesc1();
+ usleep(10*1000);
+ }
+
+ UsbWaitTDListDone();
+
+ IO_write(HPI_ADDR,0x0506);
+ printf("[ENUM PROCESS]:step 4 TD Status Byte is %x\n",IO_read(HPI_DATA));
+
+ IO_write(HPI_ADDR,0x0508);
+ usb_ctl_val = IO_read(HPI_DATA);
+ printf("[ENUM PROCESS]:step 4 TD Control Byte is %x\n",usb_ctl_val);
+ while (usb_ctl_val != 0x03)
+ {
+ usb_ctl_val = UsbGetRetryCnt();
+ }
+
+ printf("---------------[ENUM PROCESS]:get device descriptor-1 done!-----------------\n");
+
+
+ //--------------------------------get device descriptor-2---------------------------------------------//
+ //get device descriptor
+ // TASK: Call the appropriate function for this step.
+ UsbGetDeviceDesc2(); // Get Device Descriptor -2
+
+ //if no message
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ //resend the get device descriptor
+ //get device descriptor
+ // TASK: Call the appropriate function again if it wasn't processed successfully.
+ UsbGetDeviceDesc2();
+ usleep(10*1000);
+ }
+
+ UsbWaitTDListDone();
+
+ IO_write(HPI_ADDR,0x0506);
+ printf("[ENUM PROCESS]:step 4 TD Status Byte is %x\n",IO_read(HPI_DATA));
+
+ IO_write(HPI_ADDR,0x0508);
+ usb_ctl_val = IO_read(HPI_DATA);
+ printf("[ENUM PROCESS]:step 4 TD Control Byte is %x\n",usb_ctl_val);
+ while (usb_ctl_val != 0x03)
+ {
+ usb_ctl_val = UsbGetRetryCnt();
+ }
+
+ printf("------------[ENUM PROCESS]:get device descriptor-2 done!--------------\n");
+
+
+ // STEP 5 begin
+ //-----------------------------------get configuration descriptor -1 ----------------------------------//
+ // TASK: Call the appropriate function for this step.
+ UsbGetConfigDesc1(); // Get Configuration Descriptor -1
+
+ //if no message
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ //resend the get device descriptor
+ //get device descriptor
+
+ // TASK: Call the appropriate function again if it wasn't processed successfully.
+ UsbGetConfigDesc1();
+ usleep(10*1000);
+ }
+
+ UsbWaitTDListDone();
+
+ IO_write(HPI_ADDR,0x0506);
+ printf("[ENUM PROCESS]:step 5 TD Status Byte is %x\n",IO_read(HPI_DATA));
+
+ IO_write(HPI_ADDR,0x0508);
+ usb_ctl_val = IO_read(HPI_DATA);
+ printf("[ENUM PROCESS]:step 5 TD Control Byte is %x\n",usb_ctl_val);
+ while (usb_ctl_val != 0x03)
+ {
+ usb_ctl_val = UsbGetRetryCnt();
+ }
+ printf("------------[ENUM PROCESS]:get configuration descriptor-1 pass------------\n");
+
+ // STEP 6 begin
+ //-----------------------------------get configuration descriptor-2------------------------------------//
+ //get device descriptor
+ // TASK: Call the appropriate function for this step.
+ UsbGetConfigDesc2(); // Get Configuration Descriptor -2
+
+ usleep(100*1000);
+ //if no message
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ // TASK: Call the appropriate function again if it wasn't processed successfully.
+ UsbGetConfigDesc2();
+ usleep(10*1000);
+ }
+
+ UsbWaitTDListDone();
+
+ IO_write(HPI_ADDR,0x0506);
+ printf("[ENUM PROCESS]:step 6 TD Status Byte is %x\n",IO_read(HPI_DATA));
+
+ IO_write(HPI_ADDR,0x0508);
+ usb_ctl_val = IO_read(HPI_DATA);
+ printf("[ENUM PROCESS]:step 6 TD Control Byte is %x\n",usb_ctl_val);
+ while (usb_ctl_val != 0x03)
+ {
+ usb_ctl_val = UsbGetRetryCnt();
+ }
+
+
+ printf("-----------[ENUM PROCESS]:get configuration descriptor-2 done!------------\n");
+
+
+ // ---------------------------------get device info---------------------------------------------//
+
+ // TASK: Write the address to read from the memory for byte 7 of the interface descriptor to HPI_ADDR.
+ IO_write(HPI_ADDR,0x056c);
+ code = IO_read(HPI_DATA);
+ code = code & 0x003;
+ printf("\ncode = %x\n", code);
+
+ if (code == 0x02)
+ {
+ printf("\n[INFO]:check TD rec data7 \n[INFO]:Mouse Detected!!!\n\n");
+ }
+ else
+ {
+ printf("\n[INFO]:Mouse Not Detected!!! \n\n");
+ }
+
+ // TASK: Write the address to read from the memory for the endpoint descriptor to HPI_ADDR.
+
+ IO_write(HPI_ADDR,0x0576);
+ IO_write(HPI_DATA,0x073F);
+ IO_write(HPI_DATA,0x8105);
+ IO_write(HPI_DATA,0x0003);
+ IO_write(HPI_DATA,0x0008);
+ IO_write(HPI_DATA,0xAC0A);
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0576); //HUSB_SIE1_pCurrentTDPtr
+
+ //data_size = (IO_read(HPI_DATA)>>8)&0x0ff;
+ //data_size = 0x08;//(IO_read(HPI_DATA))&0x0ff;
+ //UsbPrintMem();
+ IO_write(HPI_ADDR,0x057c);
+ data_size = (IO_read(HPI_DATA))&0x0ff;
+ printf("[ENUM PROCESS]:data packet size is %d\n",data_size);
+ // STEP 7 begin
+ //------------------------------------set configuration -----------------------------------------//
+ // TASK: Call the appropriate function for this step.
+ UsbSetConfig(); // Set Configuration
+
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ // TASK: Call the appropriate function again if it wasn't processed successfully.
+ UsbSetConfig(); // Set Configuration
+ usleep(10*1000);
+ }
+
+ UsbWaitTDListDone();
+
+ IO_write(HPI_ADDR,0x0506);
+ printf("[ENUM PROCESS]:step 7 TD Status Byte is %x\n",IO_read(HPI_DATA));
+
+ IO_write(HPI_ADDR,0x0508);
+ usb_ctl_val = IO_read(HPI_DATA);
+ printf("[ENUM PROCESS]:step 7 TD Control Byte is %x\n",usb_ctl_val);
+ while (usb_ctl_val != 0x03)
+ {
+ usb_ctl_val = UsbGetRetryCnt();
+ }
+
+ printf("------------[ENUM PROCESS]:set configuration done!-------------------\n");
+
+ //----------------------------------------------class request out ------------------------------------------//
+ // TASK: Call the appropriate function for this step.
+ UsbClassRequest();
+
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ // TASK: Call the appropriate function again if it wasn't processed successfully.
+ UsbClassRequest();
+ usleep(10*1000);
+ }
+
+ UsbWaitTDListDone();
+
+ IO_write(HPI_ADDR,0x0506);
+ printf("[ENUM PROCESS]:step 8 TD Status Byte is %x\n",IO_read(HPI_DATA));
+
+ IO_write(HPI_ADDR,0x0508);
+ usb_ctl_val = IO_read(HPI_DATA);
+ printf("[ENUM PROCESS]:step 8 TD Control Byte is %x\n",usb_ctl_val);
+ while (usb_ctl_val != 0x03)
+ {
+ usb_ctl_val = UsbGetRetryCnt();
+ }
+
+
+ printf("------------[ENUM PROCESS]:class request out done!-------------------\n");
+
+ // STEP 8 begin
+ //----------------------------------get descriptor(class 0x21 = HID) request out --------------------------------//
+ // TASK: Call the appropriate function for this step.
+ UsbGetHidDesc();
+
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ // TASK: Call the appropriate function again if it wasn't processed successfully.
+ UsbGetHidDesc();
+ usleep(10*1000);
+ }
+
+ UsbWaitTDListDone();
+
+ IO_write(HPI_ADDR,0x0506);
+ printf("[ENUM PROCESS]:step 8 TD Status Byte is %x\n",IO_read(HPI_DATA));
+
+ IO_write(HPI_ADDR,0x0508);
+ usb_ctl_val = IO_read(HPI_DATA);
+ printf("[ENUM PROCESS]:step 8 TD Control Byte is %x\n",usb_ctl_val);
+ while (usb_ctl_val != 0x03)
+ {
+ usb_ctl_val = UsbGetRetryCnt();
+ }
+
+ printf("------------[ENUM PROCESS]:get descriptor (class 0x21) done!-------------------\n");
+
+ // STEP 9 begin
+ //-------------------------------get descriptor (class 0x22 = report)-------------------------------------------//
+ // TASK: Call the appropriate function for this step.
+ UsbGetReportDesc();
+ //if no message
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ // TASK: Call the appropriate function again if it wasn't processed successfully.
+ UsbGetReportDesc();
+ usleep(10*1000);
+ }
+
+ UsbWaitTDListDone();
+
+ IO_write(HPI_ADDR,0x0506);
+ printf("[ENUM PROCESS]: step 9 TD Status Byte is %x\n",IO_read(HPI_DATA));
+
+ IO_write(HPI_ADDR,0x0508);
+ usb_ctl_val = IO_read(HPI_DATA);
+ printf("[ENUM PROCESS]: step 9 TD Control Byte is %x\n",usb_ctl_val);
+ while (usb_ctl_val != 0x03)
+ {
+ usb_ctl_val = UsbGetRetryCnt();
+ }
+
+ printf("---------------[ENUM PROCESS]:get descriptor (class 0x22) done!----------------\n");
+
+
+
+ //-----------------------------------get keycode value------------------------------------------------//
+ usleep(10000);
+ while(1)
+ {
+ toggle++;
+ IO_write(HPI_ADDR,0x0500); //the start address
+ //data phase IN-1
+ IO_write(HPI_DATA,0x051c); //500
+
+ IO_write(HPI_DATA,0x000f & data_size);//2 data length
+
+ IO_write(HPI_DATA,0x0291);//4 //endpoint 1
+ if(toggle%2)
+ {
+ IO_write(HPI_DATA,0x0001);//6 //data 1
+ }
+ else
+ {
+ IO_write(HPI_DATA,0x0041);//6 //data 1
+ }
+ IO_write(HPI_DATA,0x0013);//8
+ IO_write(HPI_DATA,0x0000);//a
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ IO_write(HPI_ADDR,0x0500); //the start address
+ //data phase IN-1
+ IO_write(HPI_DATA,0x051c); //500
+
+ IO_write(HPI_DATA,0x000f & data_size);//2 data length
+
+ IO_write(HPI_DATA,0x0291);//4 //endpoint 1
+ if(toggle%2)
+ {
+ IO_write(HPI_DATA,0x0001);//6 //data 1
+ }
+ else
+ {
+ IO_write(HPI_DATA,0x0041);//6 //data 1
+ }
+ IO_write(HPI_DATA,0x0013);//8
+ IO_write(HPI_DATA,0x0000);//
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+ usleep(10*1000);
+ }//end while
+
+
+
+ usb_ctl_val = UsbWaitTDListDone();
+
+ // packet starts from 0x051c, reading third byte
+ // TASK: Write the address to read from the memory for byte 3 of the report descriptor to HPI_ADDR.
+ IO_write(HPI_ADDR,0x051e); //the start address
+ keycode = IO_read(HPI_DATA);
+ printf("\nfirst two keycode values are %04x\n",keycode);
+// IOWR(KEYCODE_BASE, 0, keycode & 0xff);
+
+
+ usleep(200);//usleep(5000);
+ usb_ctl_val = UsbRead(ctl_reg);
+
+ if(!(usb_ctl_val & no_device))
+ {
+ //USB hot plug routine
+ for(hot_plug_count = 0 ; hot_plug_count < 7 ; hot_plug_count++)
+ {
+ usleep(5*1000);
+ usb_ctl_val = UsbRead(ctl_reg);
+ if(usb_ctl_val & no_device) break;
+ }
+ if(!(usb_ctl_val & no_device))
+ {
+ printf("\n[INFO]: the keyboard has been removed!!! \n");
+ printf("[INFO]: please insert again!!! \n");
+ }
+ }
+
+ while (!(usb_ctl_val & no_device))
+ {
+
+ usb_ctl_val = UsbRead(ctl_reg);
+ usleep(5*1000);
+ usb_ctl_val = UsbRead(ctl_reg);
+ usleep(5*1000);
+ usb_ctl_val = UsbRead(ctl_reg);
+ usleep(5*1000);
+
+ if(usb_ctl_val & no_device)
+ goto USB_HOT_PLUG;
+
+ usleep(200);
+ }
+
+ }//end while
+
+ return 0;
+}
+
diff --git a/software/usb/src/usb.c b/software/usb/src/usb.c
new file mode 100644
index 0000000000000000000000000000000000000000..f8e2f37d5fd00b8f972fea43b05c95d82260e25a
--- /dev/null
+++ b/software/usb/src/usb.c
@@ -0,0 +1,581 @@
+/*---------------------------------------------------------------------------
+ -- usb.c --
+ -- Christine Chen --
+ -- Ref. DE2-115 Demonstrations by Terasic Technologies Inc. --
+ -- Fall 2014 --
+ -- --
+ -- For use with ECE 298 Experiment 7 --
+ -- UIUC ECE Department --
+ ---------------------------------------------------------------------------*/
+
+#include "usb.h"
+
+#include "system.h"
+#include "alt_types.h"
+#include <unistd.h> // usleep
+#include <stdio.h>
+//#include <io.h>
+
+#include "io_handler.h"
+#include "cy7c67200.h"
+#include "lcp_cmd.h"
+#include "lcp_data.h"
+
+//#define CY7C67200_0_BASE CY7C67200_IF_0_BASE
+
+//-------------USB operation sub function-----------
+/*****************************************************************************/
+/**
+ *
+ * This function writes data to the internal registers of the Cypress
+ * CY7C67200 USB controller.
+ *
+ * @param Address is the address of the register.
+ * @param Data is the data to be written to the register.
+ *
+ * @return None
+ *
+ * @note None
+ *
+ ******************************************************************************/
+void UsbWrite(alt_u16 Address, alt_u16 Data)
+{
+ IO_write(HPI_ADDR, Address);
+ IO_write(HPI_DATA, Data);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This function reads data from the internal registers of the Cypress
+ * CY7C67200 USB controller.
+ *
+ * @param Address is the address of the register.
+ *
+ * @return The data read from the specified address
+ *
+ * @note None
+ *
+ ******************************************************************************/
+alt_u16 UsbRead(alt_u16 Address)
+{
+ IO_write(HPI_ADDR, Address);
+ return IO_read(HPI_DATA);
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function does a software reset of the Cypress CY7C67200 USB controller.
+ *
+ * @param UsbBaseAddress is the starting location of the USB internal memory
+ * to which this bin file data is written.
+ *
+ * @return None
+ *
+ * @note None
+ *
+ ******************************************************************************/
+void UsbSoftReset()
+{
+ //XIo_Out16(USB_MAILBOX, COMM_RESET);
+ IO_write(HPI_MAILBOX,COMM_RESET); //COMM_JUMP2CODE
+ usleep(100000);
+ printf("[USB INIT]:reset finished!\n");
+
+ usleep(500000);
+ printf("[USB INIT]:Clear up the interrupt\r\n");
+ IO_read(HPI_MAILBOX);
+ IO_read(HPI_STATUS);
+
+ // Had to add the write due to a bug in BIOS where they overwrite
+ // the mailbox after initialization with garbage. The read clears
+ // any pending interrupts.
+ UsbRead (HPI_SIE1_MSG_ADR);
+ UsbWrite (HPI_SIE1_MSG_ADR, 0);
+ UsbRead (HPI_SIE2_MSG_ADR);
+ UsbWrite (HPI_SIE2_MSG_ADR, 0);
+
+
+ UsbWrite (HOST1_STAT_REG, 0xFFFF);
+ UsbWrite (HOST2_STAT_REG, 0xFFFF);
+}
+
+
+void UsbSetAddress()
+{
+ //the starting address
+ IO_write(HPI_ADDR,0x0500); //the start address
+ // TD #1: 6 writes
+ IO_write(HPI_DATA,0x050C);
+ IO_write(HPI_DATA,0x0008); //4 port number
+ // TASK: Complete with 4 more IOWR functions
+ IO_write(HPI_DATA,0x00D0);
+ IO_write(HPI_DATA,0x0001);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0514);
+ // TD #2: 4 writes
+ // TASK: Complete with 4 IOWR functions
+ IO_write(HPI_DATA,0x0500);
+ IO_write(HPI_DATA,0x0002);
+ IO_write(HPI_DATA,0x0000);
+ IO_write(HPI_DATA,0x0000);
+ // TD #3: 6 writes
+ // TASK: Complete with 6 IOWR functions
+ IO_write(HPI_DATA,0x0000); //
+ IO_write(HPI_DATA,0x0000);//
+ IO_write(HPI_DATA,0x0090);//
+ IO_write(HPI_DATA,0x0041);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0000);
+
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+}
+
+
+void UsbGetDeviceDesc1()
+{
+ //the starting address
+ IO_write(HPI_ADDR,0x0500); //the start address
+ IO_write(HPI_DATA,0x050C);
+ IO_write(HPI_DATA,0x0008); //4 port number
+ IO_write(HPI_DATA,0x02D0); //device address
+ IO_write(HPI_DATA,0x0001);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0514);
+
+ //td content 4 bytes
+ IO_write(HPI_DATA,0x0680);//c
+ IO_write(HPI_DATA,0x0100); //device 0x01
+ IO_write(HPI_DATA,0x0000);
+ IO_write(HPI_DATA,0x0008);
+
+ //data phase IN
+ IO_write(HPI_DATA,0x052C); //
+ IO_write(HPI_DATA,0x0008);//
+ IO_write(HPI_DATA,0x0290);//
+ IO_write(HPI_DATA,0x0041);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0520);
+
+ // //status phase
+ IO_write(HPI_DATA,0x0000); //don't care
+ IO_write(HPI_DATA,0x0000);//port number
+ IO_write(HPI_DATA,0x0210);//device address
+ IO_write(HPI_DATA,0x0041);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0000);
+
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+}
+
+void UsbGetDeviceDesc2()
+{
+ //the starting address
+ IO_write(HPI_ADDR,0x0500); //the start address
+ IO_write(HPI_DATA,0x050C);
+ IO_write(HPI_DATA,0x0008); //4 port number
+ IO_write(HPI_DATA,0x02D0); //device address
+ IO_write(HPI_DATA,0x0001);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0514);
+
+ //td content 4 bytes
+ IO_write(HPI_DATA,0x0680);//c
+ IO_write(HPI_DATA,0x0100);//e //device 0x01
+ IO_write(HPI_DATA,0x0000);//0
+ IO_write(HPI_DATA,0x0012);//2
+
+ //data phase IN-1
+ IO_write(HPI_DATA,0x0544); //514
+ IO_write(HPI_DATA,0x0008);//6
+ IO_write(HPI_DATA,0x0290);//8
+ IO_write(HPI_DATA,0x0041);//a
+ IO_write(HPI_DATA,0x0013);//c
+ IO_write(HPI_DATA,0x0520);//e
+
+ //data phase IN-2
+ IO_write(HPI_DATA,0x054c); //520
+ IO_write(HPI_DATA,0x0008);//2
+ IO_write(HPI_DATA,0x0290);//4
+ IO_write(HPI_DATA,0x0001);//6
+ IO_write(HPI_DATA,0x0013);//8
+ IO_write(HPI_DATA,0x052c);//a
+
+ //data phase IN-3
+ IO_write(HPI_DATA,0x0554); //c
+ IO_write(HPI_DATA,0x0002);//e
+ IO_write(HPI_DATA,0x0290);//530
+ IO_write(HPI_DATA,0x0041);//2
+ IO_write(HPI_DATA,0x0013);//4
+ IO_write(HPI_DATA,0x0538);//6
+
+ //status phase
+ IO_write(HPI_DATA,0x0000); //538
+ IO_write(HPI_DATA,0x0000);//a
+ IO_write(HPI_DATA,0x0210);//c
+ IO_write(HPI_DATA,0x0041);//e
+ IO_write(HPI_DATA,0x0013);//540
+ IO_write(HPI_DATA,0x0000);//2
+
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+}
+
+
+void UsbGetConfigDesc1()
+{
+ //the starting address
+ IO_write(HPI_ADDR,0x0500); //the start address
+ IO_write(HPI_DATA,0x050C);
+ IO_write(HPI_DATA,0x0008); //4 port number
+ IO_write(HPI_DATA,0x02D0); //device address
+ IO_write(HPI_DATA,0x0001);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0514);
+
+ //td content 4 bytes
+ IO_write(HPI_DATA,0x0680);//c
+ IO_write(HPI_DATA,0x0200);//e //config 0x02
+ IO_write(HPI_DATA,0x0000);//0
+ IO_write(HPI_DATA,0x0009);//2
+
+ //data phase IN-1
+ IO_write(HPI_DATA,0x0544); //514
+ IO_write(HPI_DATA,0x0008);//6
+ IO_write(HPI_DATA,0x0290);//8
+ IO_write(HPI_DATA,0x0041);//a
+ IO_write(HPI_DATA,0x0013);//c
+ IO_write(HPI_DATA,0x0520);//e
+
+ //data phase IN-2
+ IO_write(HPI_DATA,0x054c); //520
+ IO_write(HPI_DATA,0x0001);//2
+ IO_write(HPI_DATA,0x0290);//4
+ IO_write(HPI_DATA,0x0001);//6 //data0
+ IO_write(HPI_DATA,0x0013);//8
+ IO_write(HPI_DATA,0x052c);//a
+
+ //status phase
+ IO_write(HPI_DATA,0x0000); //52c
+ IO_write(HPI_DATA,0x0000);//e
+ IO_write(HPI_DATA,0x0210);//530
+ IO_write(HPI_DATA,0x0041);//2
+ IO_write(HPI_DATA,0x0013);//4
+ IO_write(HPI_DATA,0x0000);//6
+
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+}
+
+
+void UsbGetConfigDesc2()
+{
+ //the starting address
+ IO_write(HPI_ADDR,0x0500); //the start address
+ IO_write(HPI_DATA,0x050C);
+ IO_write(HPI_DATA,0x0008); //4 port number
+ IO_write(HPI_DATA,0x02D0); //device address
+ IO_write(HPI_DATA,0x0001);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0514);
+
+ //td content 4 bytes
+ IO_write(HPI_DATA,0x0680);//c
+ IO_write(HPI_DATA,0x0200);//e //config 0x02
+ IO_write(HPI_DATA,0x0000);//0
+ IO_write(HPI_DATA,0x00FF);//2
+
+ //data phase IN-1
+ IO_write(HPI_DATA,0x055c); //514
+ IO_write(HPI_DATA,0x0008);//6
+ IO_write(HPI_DATA,0x0290);//8
+ IO_write(HPI_DATA,0x0041);//a
+ IO_write(HPI_DATA,0x0013);//c
+ IO_write(HPI_DATA,0x0520);//e
+
+ //data phase IN-2
+ IO_write(HPI_DATA,0x0564); //520
+ IO_write(HPI_DATA,0x0008);//2
+ IO_write(HPI_DATA,0x0290);//4
+ IO_write(HPI_DATA,0x0001);//6 //data0
+ IO_write(HPI_DATA,0x0013);//8
+ IO_write(HPI_DATA,0x052c);//a
+
+ //data phase IN-3
+ IO_write(HPI_DATA,0x056c); //52c
+ IO_write(HPI_DATA,0x0008);//e
+ IO_write(HPI_DATA,0x0290);//530
+ IO_write(HPI_DATA,0x0041);//2
+ IO_write(HPI_DATA,0x0013);//4
+ IO_write(HPI_DATA,0x0538);//6
+
+ //data phase IN-4
+ IO_write(HPI_DATA,0x0574); //538
+ IO_write(HPI_DATA,0x0008);//a
+ IO_write(HPI_DATA,0x0290);//c
+ IO_write(HPI_DATA,0x0001);//e //data0
+ IO_write(HPI_DATA,0x0013);//540
+ IO_write(HPI_DATA,0x0544);//2
+
+ //data phase IN-5
+ IO_write(HPI_DATA,0x057c); //544
+ IO_write(HPI_DATA,0x0002);//6
+ IO_write(HPI_DATA,0x0290);//8
+ IO_write(HPI_DATA,0x0041);//a //data1
+ IO_write(HPI_DATA,0x0013);//c
+ IO_write(HPI_DATA,0x0550);//e
+
+ //status phase
+ IO_write(HPI_DATA,0x0000); //550
+ IO_write(HPI_DATA,0x0000);//2
+ IO_write(HPI_DATA,0x0210);//4
+ IO_write(HPI_DATA,0x0041);//6
+ IO_write(HPI_DATA,0x0013);//8
+ IO_write(HPI_DATA,0x0000);//a
+
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+}
+
+void UsbSetConfig()
+{
+ //the starting address
+ IO_write(HPI_ADDR,0x0500); //the start address
+ IO_write(HPI_DATA,0x050C);
+ IO_write(HPI_DATA,0x0008); //4 port number
+ IO_write(HPI_DATA,0x02D0); //port address
+ IO_write(HPI_DATA,0x0001);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0514);
+
+ //td content 4 bytes
+ IO_write(HPI_DATA,0x0900);
+ IO_write(HPI_DATA,0x0001);//device address
+ IO_write(HPI_DATA,0x0000);
+ IO_write(HPI_DATA,0x0000);
+ //in packet
+ IO_write(HPI_DATA,0x0000); //don't care
+ IO_write(HPI_DATA,0x0000);//port number
+ IO_write(HPI_DATA,0x0290);//device address
+ IO_write(HPI_DATA,0x0041); //data 1
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0000);
+
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+
+}
+
+void UsbClassRequest()
+{
+ //the starting address
+ IO_write(HPI_ADDR,0x0500); //the start address
+ IO_write(HPI_DATA,0x050C);
+ IO_write(HPI_DATA,0x0008); //4 port number
+ IO_write(HPI_DATA,0x02D0); //port address
+ IO_write(HPI_DATA,0x0001);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0514);
+
+ //td content 4 bytes
+ IO_write(HPI_DATA,0x0A21);
+ IO_write(HPI_DATA,0x0000);//device address
+ IO_write(HPI_DATA,0x0000);
+ IO_write(HPI_DATA,0x0000);
+ //in packet
+ IO_write(HPI_DATA,0x0000); //don't care
+ IO_write(HPI_DATA,0x0000);//port number /data length
+ IO_write(HPI_DATA,0x0290);//device address
+ IO_write(HPI_DATA,0x0041); //data 1
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0000);
+
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+}
+
+
+void UsbGetHidDesc()
+{
+ //the starting address
+ IO_write(HPI_ADDR,0x0500); //the start address
+ IO_write(HPI_DATA,0x050C);
+ IO_write(HPI_DATA,0x0008); //4 port number
+ IO_write(HPI_DATA,0x02D0); //port address
+ IO_write(HPI_DATA,0x0001);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0514);
+
+ //td content 4 bytes
+ IO_write(HPI_DATA,0x0681);//c
+ IO_write(HPI_DATA,0x2100);//e //HID 0x21
+ IO_write(HPI_DATA,0x0000);//0
+ IO_write(HPI_DATA,0x007B);//2
+
+ //data phase IN-1
+ IO_write(HPI_DATA,0x0544); //514
+ IO_write(HPI_DATA,0x0008);//6
+ IO_write(HPI_DATA,0x0290);//8
+ IO_write(HPI_DATA,0x0041);//a
+ IO_write(HPI_DATA,0x0013);//c
+ IO_write(HPI_DATA,0x0520);//e
+
+ //status phase
+ IO_write(HPI_DATA,0x0000); //52c
+ IO_write(HPI_DATA,0x0000);//e
+ IO_write(HPI_DATA,0x0210);//530
+ IO_write(HPI_DATA,0x0041);//2
+ IO_write(HPI_DATA,0x0013);//4
+ IO_write(HPI_DATA,0x0000);//6
+
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+
+}
+
+
+void UsbGetReportDesc()
+{
+ //the starting address
+ IO_write(HPI_ADDR,0x0500); //the start address
+ IO_write(HPI_DATA,0x050C);
+ IO_write(HPI_DATA,0x0008); //4 port number
+ IO_write(HPI_DATA,0x02D0); //device address
+ IO_write(HPI_DATA,0x0001);
+ IO_write(HPI_DATA,0x0013);
+ IO_write(HPI_DATA,0x0514);
+
+ //td content 4 bytes
+ IO_write(HPI_DATA,0x0681);//c
+ IO_write(HPI_DATA,0x2200);//e //report 0x22
+ IO_write(HPI_DATA,0x0000);//0
+ IO_write(HPI_DATA,0x007B);//2
+
+ //data phase IN-1
+ IO_write(HPI_DATA,0x0580); //514
+ IO_write(HPI_DATA,0x0008);//6
+ IO_write(HPI_DATA,0x0290);//8
+ IO_write(HPI_DATA,0x0041);//a
+ IO_write(HPI_DATA,0x0013);//c
+ IO_write(HPI_DATA,0x0520);//e
+
+ //data phase IN-2
+ IO_write(HPI_DATA,0x0588); //520
+ IO_write(HPI_DATA,0x0008);//2
+ IO_write(HPI_DATA,0x0290);//4
+ IO_write(HPI_DATA,0x0001);//6 //data0
+ IO_write(HPI_DATA,0x0013);//8
+ IO_write(HPI_DATA,0x052c);//a
+
+ //data phase IN-3
+ IO_write(HPI_DATA,0x0590); //52c
+ IO_write(HPI_DATA,0x0008);//e
+ IO_write(HPI_DATA,0x0290);//530
+ IO_write(HPI_DATA,0x0041);//2
+ IO_write(HPI_DATA,0x0013);//4
+ IO_write(HPI_DATA,0x0538);//6
+
+ //data phase IN-4
+ IO_write(HPI_DATA,0x0598); //538
+ IO_write(HPI_DATA,0x0008);//a
+ IO_write(HPI_DATA,0x0290);//c
+ IO_write(HPI_DATA,0x0001);//e //data0
+ IO_write(HPI_DATA,0x0013);//540
+ IO_write(HPI_DATA,0x0544);//2
+
+ //data phase IN-5
+ IO_write(HPI_DATA,0x05a0); //544
+ IO_write(HPI_DATA,0x0008);//6
+ IO_write(HPI_DATA,0x0290);//8
+ IO_write(HPI_DATA,0x0041);//a //data1
+ IO_write(HPI_DATA,0x0013);//c
+ IO_write(HPI_DATA,0x0550);//e
+
+ //data phase IN-6
+ IO_write(HPI_DATA,0x05a8); //550
+ IO_write(HPI_DATA,0x0008);//2
+ IO_write(HPI_DATA,0x0290);//4
+ IO_write(HPI_DATA,0x0001);//6 //data0
+ IO_write(HPI_DATA,0x0013);//8
+ IO_write(HPI_DATA,0x055c);//a
+
+ //data phase IN-7
+ IO_write(HPI_DATA,0x05b0); //c
+ IO_write(HPI_DATA,0x0008);//e
+ IO_write(HPI_DATA,0x0290);//560
+ IO_write(HPI_DATA,0x0041);//2 //data1
+ IO_write(HPI_DATA,0x0013);//4
+ IO_write(HPI_DATA,0x0568);//6
+
+ //data phase IN-8
+ IO_write(HPI_DATA,0x05b8); //8
+ IO_write(HPI_DATA,0x0003);//a
+ IO_write(HPI_DATA,0x0290);//c
+ IO_write(HPI_DATA,0x0001);//e //data0
+ IO_write(HPI_DATA,0x0013);//570
+ IO_write(HPI_DATA,0x0574);//2
+
+ //status phase
+ IO_write(HPI_DATA,0x0000); //574
+ IO_write(HPI_DATA,0x0000);//6
+ IO_write(HPI_DATA,0x0210);//8
+ IO_write(HPI_DATA,0x0041);//a
+ IO_write(HPI_DATA,0x0013);//c
+ IO_write(HPI_DATA,0x0000);//e
+
+ UsbWrite(HUSB_SIE1_pCurrentTDPtr,0x0500); //HUSB_SIE1_pCurrentTDPtr
+
+}
+
+
+alt_u16 UsbWaitTDListDone()
+{
+ alt_u16 usb_ctl_val;
+
+ usb_ctl_val = UsbRead(HPI_SIE1_MSG_ADR); // STEP 3 j
+ UsbWrite(HPI_SIE1_MSG_ADR, 0);
+ while (usb_ctl_val != HUSB_TDListDone) // k, read sie1 msg register
+ {
+ if(usb_ctl_val == 0x0000)
+ {
+ }
+ else
+ {
+ printf("[SIE1 MSG]:SIE1 msg reg is %x\n",usb_ctl_val);
+ }
+ usb_ctl_val = UsbRead(HPI_SIE1_MSG_ADR);
+ UsbWrite(HPI_SIE1_MSG_ADR, 0);
+ }
+
+ return usb_ctl_val;
+}
+
+
+alt_u16 UsbGetRetryCnt()
+{
+ alt_u16 usb_ctl_val;
+
+ IO_read(HPI_STATUS);
+ if(UsbRead(HPI_SIE1_MSG_ADR) == HUSB_TDListDone)
+ {
+ UsbWrite(HPI_SIE1_MSG_ADR, 0);
+
+ while (!(IO_read(HPI_STATUS) & HPI_STATUS_SIE1msg_FLAG) ) //read sie1 msg register
+ {
+ }
+ }
+ //usleep(1000);
+ IO_write(HPI_ADDR,0x0508);
+ usb_ctl_val = IO_read(HPI_DATA);
+
+ return usb_ctl_val;
+}
+
+
+void UsbPrintMem()
+{
+ int i, code;
+ IO_write(HPI_ADDR,0x0500); //the start address
+ for (i = 0; i <= 200; i += 2)
+ {
+ code = IO_read(HPI_DATA);
+ printf("\naddr %x = %04x\n", 0x0500+i, code);
+ }
+}
+
diff --git a/software/usb/src/usb.h b/software/usb/src/usb.h
new file mode 100644
index 0000000000000000000000000000000000000000..5d1b0fb64aa14f88724fad72ce82c20d7d4380b8
--- /dev/null
+++ b/software/usb/src/usb.h
@@ -0,0 +1,100 @@
+/*---------------------------------------------------------------------------
+ -- usb.h --
+ -- Christine Chen --
+ -- Ref. DE2-115 Demonstrations by Terasic Technologies Inc. --
+ -- Fall 2014 --
+ -- --
+ -- For use with ECE 298 Experiment 7 --
+ -- UIUC ECE Department --
+ ---------------------------------------------------------------------------*/
+
+#ifndef USB_H_
+#define USB_H_
+
+#include "alt_types.h"
+
+/* -----------------------------------------------------------------------
+ * HPI implementation
+ *
+ * The c67x00 chip also support control via SPI or HSS serial
+ * interfaces. However, this driver assumes that register access can
+ * be performed from IRQ context. While this is a safe assuption with
+ * the HPI interface, it is not true for the serial interfaces.
+ */
+
+/* HPI registers */
+#define HPI_DATA 0
+#define HPI_MAILBOX 1
+#define HPI_ADDR 2
+#define HPI_STATUS 3
+
+#define CY7C67200_0_BASE CY7C67200_IF_0_BASE
+
+void IO_write(alt_u8 Address, alt_u16 Data);
+alt_u16 IO_read(alt_u8 Address);
+void IO_init(void);
+
+//------------------------------ function declaration ----------------------------//
+//-------------USB operation -----------
+/*****************************************************************************/
+/**
+*
+* This function writes data to the internal registers of the Cypress
+* CY7C67200 USB controller.
+*
+* @param Address is the address of the register.
+* @param Data is the data to be written to the register.
+*
+* @return None
+*
+* @note None
+*
+******************************************************************************/
+void UsbWrite(alt_u16 Address, alt_u16 Data);
+
+/*****************************************************************************/
+/**
+*
+* This function reads data from the internal registers of the Cypress
+* CY7C67200 USB controller.
+*
+* @param Address is the address of the register.
+*
+* @return The data read from the specified address
+*
+* @note None
+*
+******************************************************************************/
+alt_u16 UsbRead(alt_u16 Address);
+
+/*****************************************************************************/
+/**
+*
+* This function does a software reset of the Cypress CY7C67200 USB controller.
+*
+* @param UsbBaseAddress is the starting location of the USB internal memory
+* to which this bin file data is written.
+*
+* @return None
+*
+* @note None
+*
+******************************************************************************/
+void UsbSoftReset();
+
+void UsbSetAddress(); // Set Address
+void UsbGetDeviceDesc1(); // Get Device Descriptor -1
+void UsbGetDeviceDesc2(); // Get Device Descriptor -2
+void UsbGetConfigDesc1(); // Get Configuration Descriptor -1
+void UsbGetConfigDesc2(); // Get Configuration Descriptor -2
+void UsbSetConfig(); // Set Configuration
+void UsbClassRequest(); // Class Request
+void UsbGetHidDesc(); // Get HID Descriptor
+void UsbGetReportDesc(); // Get Report Descriptor
+
+alt_u16 UsbWaitTDListDone(); // Check and wait until HUSB_TDListDone is read from HPI Data
+alt_u16 UsbGetRetryCnt(); // Get RetryCnt for sending the TD
+
+void UsbPrintMem(); // Print the memory contents of EZ-OTG
+
+#endif /* USB_H_ */
diff --git a/timing.sdc b/timing.sdc
index fc32e3a482c5cc466c614af8e678d7c6235007dc..52da2025cb602ac2f9f1cfe3f0a7c81f936f1c30 100644
--- a/timing.sdc
+++ b/timing.sdc
@@ -1,6 +1,8 @@
# Create Clocks
create_clock -name {Clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
-# create_generated_clock -name {lab9_qsystem|altpll_0|sd1|pll|clk[0]} -source [get_pins {lab9_qsystem|altpll_0|sd1|pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -phase -54.000 -master_clock {CLOCK_50} [get_pins {lab9_qsystem|altpll_0|sd1|pll|clk[0]}]
+create_generated_clock -name {PLL_SDRAM} -source [get_pins {main_soc|pll|sd1|pll7|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -phase -54.000 -master_clock {CLOCK_50} [get_pins {PLL_SDRAM}]
+create_generated_clock -name {PLL_USB} -source [get_pins {main_soc|pll|sd1|pll7|clk[1]}] -duty_cycle 50.000 -divide_by 5 -master_clock {CLOCK_50} [get_pins {PLL_SDRAM}]
+create_generated_clock -name {PLL_SRAM} -source [get_pins {main_soc|pll|sd1|pll7|clk[2]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {CLOCK_50} [get_pins {PLL_SDRAM}]
# Constrain the input I/O path
set_input_delay -clock {Clk} -max 3 [all_inputs]
@@ -17,6 +19,109 @@ set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {PS2
set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {PS2_KBCLK}]
set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {PS2_KBDAT}]
set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {PS2_KBDAT}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[0]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[0]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[1]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[1]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[2]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[2]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[3]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[3]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[4]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[4]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[5]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[5]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[6]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[6]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[7]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[7]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[8]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[8]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[9]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[9]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[10]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[10]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[11]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[11]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[12]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[12]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[13]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[13]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[14]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[14]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[15]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[15]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[16]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[16]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[17]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[17]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[18]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[18]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[19]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[19]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[20]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[20]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[21]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[21]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[22]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[22]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[23]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[23]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[24]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[24]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[25]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[25]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[26]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[26]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[27]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[27]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[28]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[28]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[29]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[29]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[30]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[30]}]
+set_input_delay -add_delay -max -clock [get_clocks {PLL_SDRAM}] 3.000 [get_ports {DRAM_DQ[31]}]
+set_input_delay -add_delay -min -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[31]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[0]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[0]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[1]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[1]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[2]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[2]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[3]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[3]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[4]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[4]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[5]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[5]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[6]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[6]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[7]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[7]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[8]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[8]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[9]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[9]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[10]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[10]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[11]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[11]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[12]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[12]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[13]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[13]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[14]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[14]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {OTG_DATA[15]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[15]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {altera_reserved_tck}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {altera_reserved_tck}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {altera_reserved_tdi}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {altera_reserved_tdi}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {altera_reserved_tms}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {altera_reserved_tms}]
+
# Constrain the output I/O path
set_output_delay -clock {Clk} 2 [all_outputs]
@@ -28,6 +133,24 @@ set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[4
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[5]}]
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[6]}]
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[7]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[7]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[8]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[9]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[10]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[11]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[12]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[13]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[14]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[15]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[16]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDR[17]}]
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[0]}]
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[1]}]
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[2]}]
@@ -56,5 +179,118 @@ set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[3
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[4]}]
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[5]}]
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX4[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX4[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX4[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX4[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX4[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX4[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX4[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX5[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX5[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX5[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX5[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX5[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX5[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX5[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX6[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX6[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX6[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX6[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX6[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX6[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX6[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX7[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX7[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX7[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX7[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX7[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX7[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX7[6]}]
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {PS2_KBCLK}]
set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {PS2_KBDAT}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[0]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[1]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[2]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[3]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[4]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[5]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[6]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[7]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[8]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[9]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[10]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[11]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_ADDR[12]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_BA[0]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_BA[1]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_CAS_N}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_CKE}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_CS_N}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQM[0]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQM[1]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQM[2]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQM[3]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[0]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[1]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[2]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[3]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[4]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[5]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[6]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[7]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[8]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[9]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[10]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[11]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[12]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[13]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[14]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[15]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[16]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[17]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[18]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[19]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[20]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[21]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[22]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[23]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[24]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[25]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[26]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[27]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[28]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[29]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[30]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_DQ[31]}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_RAS_N}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_WE_N}]
+set_output_delay -add_delay -clock [get_clocks {PLL_SDRAM}] 2.000 [get_ports {DRAM_CLK}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_ADDR[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_ADDR[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_CS_N}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_RST_N}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_RD_N}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_WR_N}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[7]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[8]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[9]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[10]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[11]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[12]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[13]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[14]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {OTG_DATA[15]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {VGA_CLK}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {altera_reserved_tdo}]
+
+# Clock groups
+set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
+set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]