diff --git a/.gitignore b/.gitignore
index d35ba51e12ebc314b5f6d61e095c368f7f2feec5..3b88ec77130670016f05cd84f17ecd38cfe6dba8 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,3 +11,6 @@ otogame/
*.sopcinfo
*.tcl~
.metadata/
+*.qdf
+audio_test/
+RemoteSystemsTempFiles/
\ No newline at end of file
diff --git a/Audio_Controller/Altera_UP_Audio_Bit_Counter.v b/Audio_Controller/Altera_UP_Audio_Bit_Counter.v
new file mode 100644
index 0000000000000000000000000000000000000000..8ee3164bb05b9ba95735b87b79695912ee5d1f36
--- /dev/null
+++ b/Audio_Controller/Altera_UP_Audio_Bit_Counter.v
@@ -0,0 +1,110 @@
+/*****************************************************************************
+ * *
+ * Module: Altera_UP_Audio_Bit_Counter *
+ * Description: *
+ * This module counts which bits for serial audio transfers. The module *
+ * assume that the data format is I2S, as it is described in the audio *
+ * chip's datasheet. *
+ * *
+ *****************************************************************************/
+
+module Altera_UP_Audio_Bit_Counter (
+ // Inputs
+ clk,
+ reset,
+
+ bit_clk_rising_edge,
+ bit_clk_falling_edge,
+ left_right_clk_rising_edge,
+ left_right_clk_falling_edge,
+
+ // Bidirectionals
+
+ // Outputs
+ counting
+);
+
+/*****************************************************************************
+ * Parameter Declarations *
+ *****************************************************************************/
+
+parameter BIT_COUNTER_INIT = 5'd31;
+
+/*****************************************************************************
+ * Port Declarations *
+ *****************************************************************************/
+
+// Inputs
+input clk;
+input reset;
+
+input bit_clk_rising_edge;
+input bit_clk_falling_edge;
+input left_right_clk_rising_edge;
+input left_right_clk_falling_edge;
+
+// Bidirectionals
+
+// Outputs
+output reg counting;
+
+/*****************************************************************************
+ * Constant Declarations *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Internal wires and registers Declarations *
+ *****************************************************************************/
+
+// Internal Wires
+wire reset_bit_counter;
+
+// Internal Registers
+reg [4:0] bit_counter;
+
+// State Machine Registers
+
+
+/*****************************************************************************
+ * Finite State Machine(s) *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Sequential logic *
+ *****************************************************************************/
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ bit_counter <= 5'h00;
+ else if (reset_bit_counter == 1'b1)
+ bit_counter <= BIT_COUNTER_INIT;
+ else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
+ bit_counter <= bit_counter - 5'h01;
+end
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ counting <= 1'b0;
+ else if (reset_bit_counter == 1'b1)
+ counting <= 1'b1;
+ else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
+ counting <= 1'b0;
+end
+
+/*****************************************************************************
+ * Combinational logic *
+ *****************************************************************************/
+
+assign reset_bit_counter = left_right_clk_rising_edge |
+ left_right_clk_falling_edge;
+
+/*****************************************************************************
+ * Internal Modules *
+ *****************************************************************************/
+
+endmodule
+
diff --git a/Audio_Controller/Altera_UP_Audio_In_Deserializer.v b/Audio_Controller/Altera_UP_Audio_In_Deserializer.v
new file mode 100644
index 0000000000000000000000000000000000000000..de0a20dfb13ba580e251dab6aa85c6793980f875
--- /dev/null
+++ b/Audio_Controller/Altera_UP_Audio_In_Deserializer.v
@@ -0,0 +1,212 @@
+/*****************************************************************************
+ * *
+ * Module: Altera_UP_Audio_In_Deserializer *
+ * Description: *
+ * This module read data from the Audio ADC on the Altera DE2 board. *
+ * *
+ *****************************************************************************/
+
+module Altera_UP_Audio_In_Deserializer (
+ // Inputs
+ clk,
+ reset,
+
+ bit_clk_rising_edge,
+ bit_clk_falling_edge,
+ left_right_clk_rising_edge,
+ left_right_clk_falling_edge,
+
+ done_channel_sync,
+
+ serial_audio_in_data,
+
+ read_left_audio_data_en,
+ read_right_audio_data_en,
+
+ // Bidirectionals
+
+ // Outputs
+ left_audio_fifo_read_space,
+ right_audio_fifo_read_space,
+
+ left_channel_data,
+ right_channel_data
+);
+
+/*****************************************************************************
+ * Parameter Declarations *
+ *****************************************************************************/
+
+parameter AUDIO_DATA_WIDTH = 32;
+parameter BIT_COUNTER_INIT = 5'd31;
+
+/*****************************************************************************
+ * Port Declarations *
+ *****************************************************************************/
+// Inputs
+input clk;
+input reset;
+
+input bit_clk_rising_edge;
+input bit_clk_falling_edge;
+input left_right_clk_rising_edge;
+input left_right_clk_falling_edge;
+
+input done_channel_sync;
+
+input serial_audio_in_data;
+
+input read_left_audio_data_en;
+input read_right_audio_data_en;
+
+// Bidirectionals
+
+// Outputs
+output reg [7:0] left_audio_fifo_read_space;
+output reg [7:0] right_audio_fifo_read_space;
+
+output [AUDIO_DATA_WIDTH:1] left_channel_data;
+output [AUDIO_DATA_WIDTH:1] right_channel_data;
+
+/*****************************************************************************
+ * Internal wires and registers Declarations *
+ *****************************************************************************/
+// Internal Wires
+wire valid_audio_input;
+
+wire left_channel_fifo_is_empty;
+wire right_channel_fifo_is_empty;
+
+wire left_channel_fifo_is_full;
+wire right_channel_fifo_is_full;
+
+wire [6:0] left_channel_fifo_used;
+wire [6:0] right_channel_fifo_used;
+
+// Internal Registers
+reg [AUDIO_DATA_WIDTH:1] data_in_shift_reg;
+
+// State Machine Registers
+
+
+/*****************************************************************************
+ * Finite State Machine(s) *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Sequential logic *
+ *****************************************************************************/
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ left_audio_fifo_read_space <= 8'h00;
+ else
+ begin
+ left_audio_fifo_read_space[7] <= left_channel_fifo_is_full;
+ left_audio_fifo_read_space[6:0] <= left_channel_fifo_used;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ right_audio_fifo_read_space <= 8'h00;
+ else
+ begin
+ right_audio_fifo_read_space[7] <= right_channel_fifo_is_full;
+ right_audio_fifo_read_space[6:0] <= right_channel_fifo_used;
+ end
+end
+
+
+
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ data_in_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
+ else if (bit_clk_rising_edge & valid_audio_input)
+ data_in_shift_reg <=
+ {data_in_shift_reg[(AUDIO_DATA_WIDTH - 1):1],
+ serial_audio_in_data};
+end
+
+/*****************************************************************************
+ * Combinational logic *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Internal Modules *
+ *****************************************************************************/
+
+Altera_UP_Audio_Bit_Counter Audio_Out_Bit_Counter (
+ // Inputs
+ .clk (clk),
+ .reset (reset),
+
+ .bit_clk_rising_edge (bit_clk_rising_edge),
+ .bit_clk_falling_edge (bit_clk_falling_edge),
+ .left_right_clk_rising_edge (left_right_clk_rising_edge),
+ .left_right_clk_falling_edge (left_right_clk_falling_edge),
+
+ // Bidirectionals
+
+ // Outputs
+ .counting (valid_audio_input)
+);
+defparam
+ Audio_Out_Bit_Counter.BIT_COUNTER_INIT = BIT_COUNTER_INIT;
+
+Altera_UP_SYNC_FIFO Audio_In_Left_Channel_FIFO(
+ // Inputs
+ .clk (clk),
+ .reset (reset),
+
+ .write_en (left_right_clk_falling_edge & ~left_channel_fifo_is_full & done_channel_sync),
+ .write_data (data_in_shift_reg),
+
+ .read_en (read_left_audio_data_en & ~left_channel_fifo_is_empty),
+
+ // Bidirectionals
+
+ // Outputs
+ .fifo_is_empty (left_channel_fifo_is_empty),
+ .fifo_is_full (left_channel_fifo_is_full),
+ .words_used (left_channel_fifo_used),
+
+ .read_data (left_channel_data)
+);
+defparam
+ Audio_In_Left_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
+ Audio_In_Left_Channel_FIFO.DATA_DEPTH = 128,
+ Audio_In_Left_Channel_FIFO.ADDR_WIDTH = 7;
+
+Altera_UP_SYNC_FIFO Audio_In_Right_Channel_FIFO(
+ // Inputs
+ .clk (clk),
+ .reset (reset),
+
+ .write_en (left_right_clk_rising_edge & ~right_channel_fifo_is_full & done_channel_sync),
+ .write_data (data_in_shift_reg),
+
+ .read_en (read_right_audio_data_en & ~right_channel_fifo_is_empty),
+
+ // Bidirectionals
+
+ // Outputs
+ .fifo_is_empty (right_channel_fifo_is_empty),
+ .fifo_is_full (right_channel_fifo_is_full),
+ .words_used (right_channel_fifo_used),
+
+ .read_data (right_channel_data)
+);
+defparam
+ Audio_In_Right_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
+ Audio_In_Right_Channel_FIFO.DATA_DEPTH = 128,
+ Audio_In_Right_Channel_FIFO.ADDR_WIDTH = 7;
+
+endmodule
+
diff --git a/Audio_Controller/Altera_UP_Audio_Out_Serializer.v b/Audio_Controller/Altera_UP_Audio_Out_Serializer.v
new file mode 100644
index 0000000000000000000000000000000000000000..9545ad9374c4fb046f8836fc92efd3d9e57f65e8
--- /dev/null
+++ b/Audio_Controller/Altera_UP_Audio_Out_Serializer.v
@@ -0,0 +1,217 @@
+/*****************************************************************************
+ * *
+ * Module: Altera_UP_Audio_Out_Serializer *
+ * Description: *
+ * This module writes data to the Audio DAC on the Altera DE2 board. *
+ * *
+ *****************************************************************************/
+
+module Altera_UP_Audio_Out_Serializer (
+ // Inputs
+ clk,
+ reset,
+
+ bit_clk_rising_edge,
+ bit_clk_falling_edge,
+ left_right_clk_rising_edge,
+ left_right_clk_falling_edge,
+
+ left_channel_data,
+ left_channel_data_en,
+
+ right_channel_data,
+ right_channel_data_en,
+
+ // Bidirectionals
+
+ // Outputs
+ left_channel_fifo_write_space,
+ right_channel_fifo_write_space,
+
+ serial_audio_out_data
+);
+
+/*****************************************************************************
+ * Parameter Declarations *
+ *****************************************************************************/
+
+parameter AUDIO_DATA_WIDTH = 32;
+
+/*****************************************************************************
+ * Port Declarations *
+ *****************************************************************************/
+// Inputs
+input clk;
+input reset;
+
+input bit_clk_rising_edge;
+input bit_clk_falling_edge;
+input left_right_clk_rising_edge;
+input left_right_clk_falling_edge;
+
+input [AUDIO_DATA_WIDTH:1] left_channel_data;
+input left_channel_data_en;
+
+input [AUDIO_DATA_WIDTH:1] right_channel_data;
+input right_channel_data_en;
+
+// Bidirectionals
+
+// Outputs
+output reg [7:0] left_channel_fifo_write_space;
+output reg [7:0] right_channel_fifo_write_space;
+
+output reg serial_audio_out_data;
+
+
+/*****************************************************************************
+ * Internal wires and registers Declarations *
+ *****************************************************************************/
+
+// Internal Wires
+wire read_left_channel;
+wire read_right_channel;
+
+wire left_channel_fifo_is_empty;
+wire right_channel_fifo_is_empty;
+
+wire left_channel_fifo_is_full;
+wire right_channel_fifo_is_full;
+
+wire [6:0] left_channel_fifo_used;
+wire [6:0] right_channel_fifo_used;
+
+wire [AUDIO_DATA_WIDTH:1] left_channel_from_fifo;
+wire [AUDIO_DATA_WIDTH:1] right_channel_from_fifo;
+
+// Internal Registers
+reg left_channel_was_read;
+reg [AUDIO_DATA_WIDTH:1] data_out_shift_reg;
+
+// State Machine Registers
+
+/*****************************************************************************
+ * Finite State Machine(s) *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Sequential logic *
+ *****************************************************************************/
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ left_channel_fifo_write_space <= 8'h00;
+ else
+ left_channel_fifo_write_space <= 8'h80 - {left_channel_fifo_is_full,left_channel_fifo_used};
+end
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ right_channel_fifo_write_space <= 8'h00;
+ else
+ right_channel_fifo_write_space <= 8'h80 - {right_channel_fifo_is_full,right_channel_fifo_used};
+end
+
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ serial_audio_out_data <= 1'b0;
+ else
+ serial_audio_out_data <= data_out_shift_reg[AUDIO_DATA_WIDTH];
+end
+
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ left_channel_was_read <= 1'b0;
+ else if (read_left_channel)
+ left_channel_was_read <=1'b1;
+ else if (read_right_channel)
+ left_channel_was_read <=1'b0;
+end
+
+
+always @(posedge clk)
+begin
+ if (reset == 1'b1)
+ data_out_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
+ else if (read_left_channel)
+ data_out_shift_reg <= left_channel_from_fifo;
+ else if (read_right_channel)
+ data_out_shift_reg <= right_channel_from_fifo;
+ else if (left_right_clk_rising_edge | left_right_clk_falling_edge)
+ data_out_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
+ else if (bit_clk_falling_edge)
+ data_out_shift_reg <=
+ {data_out_shift_reg[(AUDIO_DATA_WIDTH - 1):1], 1'b0};
+end
+
+/*****************************************************************************
+ * Combinational logic *
+ *****************************************************************************/
+
+assign read_left_channel = left_right_clk_rising_edge &
+ ~left_channel_fifo_is_empty &
+ ~right_channel_fifo_is_empty;
+assign read_right_channel = left_right_clk_falling_edge &
+ left_channel_was_read;
+
+/*****************************************************************************
+ * Internal Modules *
+ *****************************************************************************/
+
+Altera_UP_SYNC_FIFO Audio_Out_Left_Channel_FIFO(
+ // Inputs
+ .clk (clk),
+ .reset (reset),
+
+ .write_en (left_channel_data_en & ~left_channel_fifo_is_full),
+ .write_data (left_channel_data),
+
+ .read_en (read_left_channel),
+
+ // Bidirectionals
+
+ // Outputs
+ .fifo_is_empty (left_channel_fifo_is_empty),
+ .fifo_is_full (left_channel_fifo_is_full),
+ .words_used (left_channel_fifo_used),
+
+ .read_data (left_channel_from_fifo)
+);
+defparam
+ Audio_Out_Left_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
+ Audio_Out_Left_Channel_FIFO.DATA_DEPTH = 128,
+ Audio_Out_Left_Channel_FIFO.ADDR_WIDTH = 7;
+
+Altera_UP_SYNC_FIFO Audio_Out_Right_Channel_FIFO(
+ // Inputs
+ .clk (clk),
+ .reset (reset),
+
+ .write_en (right_channel_data_en & ~right_channel_fifo_is_full),
+ .write_data (right_channel_data),
+
+ .read_en (read_right_channel),
+
+ // Bidirectionals
+
+ // Outputs
+ .fifo_is_empty (right_channel_fifo_is_empty),
+ .fifo_is_full (right_channel_fifo_is_full),
+ .words_used (right_channel_fifo_used),
+
+ .read_data (right_channel_from_fifo)
+);
+defparam
+ Audio_Out_Right_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
+ Audio_Out_Right_Channel_FIFO.DATA_DEPTH = 128,
+ Audio_Out_Right_Channel_FIFO.ADDR_WIDTH = 7;
+
+endmodule
+
diff --git a/Audio_Controller/Altera_UP_Clock_Edge.v b/Audio_Controller/Altera_UP_Clock_Edge.v
new file mode 100644
index 0000000000000000000000000000000000000000..aaa4aa87d1b4e098461e90be117da30258d63978
--- /dev/null
+++ b/Audio_Controller/Altera_UP_Clock_Edge.v
@@ -0,0 +1,93 @@
+/*****************************************************************************
+ * *
+ * Module: Altera_UP_Clock_Edge *
+ * Description: *
+ * This module finds clock edges of one clock at the frquency of *
+ * another clock. *
+ * *
+ *****************************************************************************/
+
+module Altera_UP_Clock_Edge (
+ // Inputs
+ clk,
+ reset,
+
+ test_clk,
+
+ // Bidirectionals
+
+ // Outputs
+ rising_edge,
+ falling_edge
+);
+
+/*****************************************************************************
+ * Parameter Declarations *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Port Declarations *
+ *****************************************************************************/
+
+// Inputs
+input clk;
+input reset;
+
+input test_clk;
+
+// Bidirectionals
+
+// Outputs
+output rising_edge;
+output falling_edge;
+
+/*****************************************************************************
+ * Constant Declarations *
+ *****************************************************************************/
+
+/*****************************************************************************
+ * Internal wires and registers Declarations *
+ *****************************************************************************/
+
+// Internal Wires
+wire found_edge;
+
+// Internal Registers
+reg cur_test_clk;
+reg last_test_clk;
+
+// State Machine Registers
+
+/*****************************************************************************
+ * Finite State Machine(s) *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Sequential logic *
+ *****************************************************************************/
+
+always @(posedge clk)
+ cur_test_clk <= test_clk;
+
+always @(posedge clk)
+ last_test_clk <= cur_test_clk;
+
+/*****************************************************************************
+ * Combinational logic *
+ *****************************************************************************/
+
+// Output Assignments
+assign rising_edge = found_edge & cur_test_clk;
+assign falling_edge = found_edge & last_test_clk;
+
+// Internal Assignments
+assign found_edge = last_test_clk ^ cur_test_clk;
+
+/*****************************************************************************
+ * Internal Modules *
+ *****************************************************************************/
+
+endmodule
+
diff --git a/Audio_Controller/Altera_UP_SYNC_FIFO.v b/Audio_Controller/Altera_UP_SYNC_FIFO.v
new file mode 100644
index 0000000000000000000000000000000000000000..acbc5c98bb109a2ec42c16d0bf9b4d03b1186627
--- /dev/null
+++ b/Audio_Controller/Altera_UP_SYNC_FIFO.v
@@ -0,0 +1,129 @@
+/*****************************************************************************
+ * *
+ * Module: Altera_UP_SYNC_FIFO *
+ * Description: *
+ * This module is a FIFO with same clock for both reads and writes. *
+ * *
+ *****************************************************************************/
+
+module Altera_UP_SYNC_FIFO (
+ // Inputs
+ clk,
+ reset,
+
+ write_en,
+ write_data,
+
+ read_en,
+
+ // Bidirectionals
+
+ // Outputs
+ fifo_is_empty,
+ fifo_is_full,
+ words_used,
+
+ read_data
+);
+
+/*****************************************************************************
+ * Parameter Declarations *
+ *****************************************************************************/
+
+parameter DATA_WIDTH = 32;
+parameter DATA_DEPTH = 128;
+parameter ADDR_WIDTH = 7;
+
+/*****************************************************************************
+ * Port Declarations *
+ *****************************************************************************/
+
+// Inputs
+input clk;
+input reset;
+
+input write_en;
+input [DATA_WIDTH:1] write_data;
+
+input read_en;
+
+// Bidirectionals
+
+// Outputs
+output fifo_is_empty;
+output fifo_is_full;
+output [ADDR_WIDTH:1] words_used;
+
+output [DATA_WIDTH:1] read_data;
+
+/*****************************************************************************
+ * Internal wires and registers Declarations *
+ *****************************************************************************/
+
+// Internal Wires
+
+// Internal Registers
+
+// State Machine Registers
+
+/*****************************************************************************
+ * Finite State Machine(s) *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Sequential logic *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Combinational logic *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Internal Modules *
+ *****************************************************************************/
+
+
+scfifo Sync_FIFO (
+ // Inputs
+ .clock (clk),
+ .sclr (reset),
+
+ .data (write_data),
+ .wrreq (write_en),
+
+ .rdreq (read_en),
+
+ // Bidirectionals
+
+ // Outputs
+ .empty (fifo_is_empty),
+ .full (fifo_is_full),
+ .usedw (words_used),
+
+ .q (read_data)
+
+ // Unused
+ // synopsys translate_off
+ ,
+ .aclr (),
+ .almost_empty (),
+ .almost_full ()
+ // synopsys translate_on
+);
+defparam
+ Sync_FIFO.add_ram_output_register = "OFF",
+ Sync_FIFO.intended_device_family = "Cyclone II",
+ Sync_FIFO.lpm_numwords = DATA_DEPTH,
+ Sync_FIFO.lpm_showahead = "ON",
+ Sync_FIFO.lpm_type = "scfifo",
+ Sync_FIFO.lpm_width = DATA_WIDTH,
+ Sync_FIFO.lpm_widthu = ADDR_WIDTH,
+ Sync_FIFO.overflow_checking = "OFF",
+ Sync_FIFO.underflow_checking = "OFF",
+ Sync_FIFO.use_eab = "ON";
+
+endmodule
+
diff --git a/Audio_Controller/Audio_Clock.v b/Audio_Controller/Audio_Clock.v
new file mode 100644
index 0000000000000000000000000000000000000000..f5f582fefcef077896cb8aaa5763826cc4a45e80
--- /dev/null
+++ b/Audio_Controller/Audio_Clock.v
@@ -0,0 +1,312 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: Audio_Clock.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Build 151 09/26/2007 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Audio_Clock (
+ areset,
+ inclk0,
+ c0,
+ locked);
+
+ input areset;
+ input inclk0;
+ output c0;
+ output locked;
+
+ wire [5:0] sub_wire0;
+ wire sub_wire2;
+ wire [0:0] sub_wire5 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire locked = sub_wire2;
+ wire sub_wire3 = inclk0;
+ wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+ altpll altpll_component (
+ .inclk (sub_wire4),
+ .areset (areset),
+ .clk (sub_wire0),
+ .locked (sub_wire2),
+ .activeclock (),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 4,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.gate_lock_signal = "NO",
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=Audio_Clock",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_USED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "4"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "Audio_Clock.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_Clock.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_Clock.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_Clock.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_Clock.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_Clock.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_Clock_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_Clock_bb.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_Clock_waveforms.html TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_Clock_wave*.jpg FALSE FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Audio_Controller/Audio_Controller.v b/Audio_Controller/Audio_Controller.v
new file mode 100644
index 0000000000000000000000000000000000000000..db6f27f3297d45fda54db50ea4a1b2b26f4fd4df
--- /dev/null
+++ b/Audio_Controller/Audio_Controller.v
@@ -0,0 +1,280 @@
+/*****************************************************************************
+ * *
+ * Module: Altera_UP_Avalon_Audio *
+ * Description: *
+ * This module reads and writes data to the Audio chip on Altera's DE2 *
+ * Development and Education Board. The audio chip must be in master mode *
+ * and the digital format must be left justified. *
+ * *
+ *****************************************************************************/
+
+module Audio_Controller(
+ // Inputs
+ CLOCK_50,
+ reset,
+
+ clear_audio_in_memory,
+ read_audio_in,
+
+ clear_audio_out_memory,
+ left_channel_audio_out,
+ right_channel_audio_out,
+ write_audio_out,
+
+ AUD_ADCDAT,
+
+ // Bidirectionals
+ AUD_BCLK,
+ AUD_ADCLRCK,
+ AUD_DACLRCK,
+
+ // Outputs
+ left_channel_audio_in,
+ right_channel_audio_in,
+ audio_in_available,
+
+ audio_out_allowed,
+
+ AUD_XCK,
+ AUD_DACDAT
+);
+
+/*****************************************************************************
+ * Parameter Declarations *
+ *****************************************************************************/
+
+localparam AUDIO_DATA_WIDTH = 32;
+localparam BIT_COUNTER_INIT = 5'd31;
+
+/*****************************************************************************
+ * Port Declarations *
+ *****************************************************************************/
+// Inputs
+input CLOCK_50;
+input reset;
+
+input clear_audio_in_memory;
+input read_audio_in;
+
+input clear_audio_out_memory;
+input [AUDIO_DATA_WIDTH:1] left_channel_audio_out;
+input [AUDIO_DATA_WIDTH:1] right_channel_audio_out;
+input write_audio_out;
+
+input AUD_ADCDAT;
+
+// Bidirectionals
+inout AUD_BCLK;
+inout AUD_ADCLRCK;
+inout AUD_DACLRCK;
+
+// Outputs
+output reg audio_in_available;
+output [AUDIO_DATA_WIDTH:1] left_channel_audio_in;
+output [AUDIO_DATA_WIDTH:1] right_channel_audio_in;
+
+output reg audio_out_allowed;
+
+output AUD_XCK;
+output AUD_DACDAT;
+
+/*****************************************************************************
+ * Internal wires and registers Declarations *
+ *****************************************************************************/
+
+// Internal Wires
+wire bclk_rising_edge;
+wire bclk_falling_edge;
+
+wire adc_lrclk_rising_edge;
+wire adc_lrclk_falling_edge;
+
+wire dac_lrclk_rising_edge;
+wire dac_lrclk_falling_edge;
+
+wire [7:0] left_channel_read_available;
+wire [7:0] right_channel_read_available;
+
+wire [7:0] left_channel_write_space;
+wire [7:0] right_channel_write_space;
+
+// Internal Registers
+reg done_adc_channel_sync;
+reg done_dac_channel_sync;
+
+// State Machine Registers
+
+
+/*****************************************************************************
+ * Finite State Machine(s) *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ * Sequential logic *
+ *****************************************************************************/
+
+// Output Registers
+always @ (posedge CLOCK_50)
+begin
+ if (reset == 1'b1)
+ audio_in_available <= 1'b0;
+ else if ((left_channel_read_available[7] | left_channel_read_available[6])
+ & (right_channel_read_available[7] | right_channel_read_available[6]))
+ audio_in_available <= 1'b1;
+ else
+ audio_in_available <= 1'b0;
+end
+
+always @ (posedge CLOCK_50)
+begin
+ if (reset == 1'b1)
+ audio_out_allowed <= 1'b0;
+ else if ((left_channel_write_space[7] | left_channel_write_space[6])
+ & (right_channel_write_space[7] | right_channel_write_space[6]))
+ audio_out_allowed <= 1'b1;
+ else
+ audio_out_allowed <= 1'b0;
+end
+
+// Internal Registers
+always @ (posedge CLOCK_50)
+begin
+ if (reset == 1'b1)
+ done_adc_channel_sync <= 1'b0;
+ else if (adc_lrclk_rising_edge == 1'b1)
+ done_adc_channel_sync <= 1'b1;
+end
+
+always @ (posedge CLOCK_50)
+begin
+ if (reset == 1'b1)
+ done_dac_channel_sync <= 1'b0;
+ else if (dac_lrclk_falling_edge == 1'b1)
+ done_dac_channel_sync <= 1'b1;
+end
+
+/*****************************************************************************
+ * Combinational logic *
+ *****************************************************************************/
+
+assign AUD_BCLK = 1'bZ;
+assign AUD_ADCLRCK = 1'bZ;
+assign AUD_DACLRCK = 1'bZ;
+
+
+/*****************************************************************************
+ * Internal Modules *
+ *****************************************************************************/
+
+Altera_UP_Clock_Edge Bit_Clock_Edges (
+ // Inputs
+ .clk (CLOCK_50),
+ .reset (reset),
+
+ .test_clk (AUD_BCLK),
+
+ // Bidirectionals
+
+ // Outputs
+ .rising_edge (bclk_rising_edge),
+ .falling_edge (bclk_falling_edge)
+);
+
+Altera_UP_Clock_Edge ADC_Left_Right_Clock_Edges (
+ // Inputs
+ .clk (CLOCK_50),
+ .reset (reset),
+
+ .test_clk (AUD_ADCLRCK),
+
+ // Bidirectionals
+
+ // Outputs
+ .rising_edge (adc_lrclk_rising_edge),
+ .falling_edge (adc_lrclk_falling_edge)
+);
+
+Altera_UP_Clock_Edge DAC_Left_Right_Clock_Edges (
+ // Inputs
+ .clk (CLOCK_50),
+ .reset (reset),
+
+ .test_clk (AUD_DACLRCK),
+
+ // Bidirectionals
+
+ // Outputs
+ .rising_edge (dac_lrclk_rising_edge),
+ .falling_edge (dac_lrclk_falling_edge)
+);
+
+Altera_UP_Audio_In_Deserializer Audio_In_Deserializer (
+ // Inputs
+ .clk (CLOCK_50),
+ .reset (reset | clear_audio_in_memory),
+
+ .bit_clk_rising_edge (bclk_rising_edge),
+ .bit_clk_falling_edge (bclk_falling_edge),
+ .left_right_clk_rising_edge (adc_lrclk_rising_edge),
+ .left_right_clk_falling_edge (adc_lrclk_falling_edge),
+
+ .done_channel_sync (done_adc_channel_sync),
+
+ .serial_audio_in_data (AUD_ADCDAT),
+
+ .read_left_audio_data_en (read_audio_in & audio_in_available),
+ .read_right_audio_data_en (read_audio_in & audio_in_available),
+
+ // Bidirectionals
+
+ // Outputs
+ .left_audio_fifo_read_space (left_channel_read_available),
+ .right_audio_fifo_read_space (right_channel_read_available),
+
+ .left_channel_data (left_channel_audio_in),
+ .right_channel_data (right_channel_audio_in)
+);
+defparam
+ Audio_In_Deserializer.AUDIO_DATA_WIDTH = AUDIO_DATA_WIDTH,
+ Audio_In_Deserializer.BIT_COUNTER_INIT = BIT_COUNTER_INIT;
+
+Altera_UP_Audio_Out_Serializer Audio_Out_Serializer (
+ // Inputs
+ .clk (CLOCK_50),
+ .reset (reset | clear_audio_out_memory),
+
+ .bit_clk_rising_edge (bclk_rising_edge),
+ .bit_clk_falling_edge (bclk_falling_edge),
+ .left_right_clk_rising_edge (done_dac_channel_sync & dac_lrclk_rising_edge),
+ .left_right_clk_falling_edge (done_dac_channel_sync & dac_lrclk_falling_edge),
+
+ .left_channel_data (left_channel_audio_out),
+ .left_channel_data_en (write_audio_out & audio_out_allowed),
+
+ .right_channel_data (right_channel_audio_out),
+ .right_channel_data_en (write_audio_out & audio_out_allowed),
+
+ // Bidirectionals
+
+ // Outputs
+ .left_channel_fifo_write_space (left_channel_write_space),
+ .right_channel_fifo_write_space (right_channel_write_space),
+
+ .serial_audio_out_data (AUD_DACDAT)
+);
+defparam
+ Audio_Out_Serializer.AUDIO_DATA_WIDTH = AUDIO_DATA_WIDTH;
+
+Audio_Clock Audio_Clock (
+ // Inputs
+ .inclk0 (CLOCK_50),
+ .areset (),
+
+ // Outputs
+ .c0 (AUD_XCK),
+ .locked ()
+);
+
+endmodule
+
diff --git a/audio.sv b/audio.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5c9a66b963b8881fa22012c3611dc86f1e6ef02f
--- /dev/null
+++ b/audio.sv
@@ -0,0 +1,123 @@
+module audio(
+ input logic CLK,RESET,
+
+ input logic [1:0]AVL_ADDR,
+ input logic AVL_CS,
+ input logic AVL_RD,AVL_WR,
+ input logic [31:0] AVL_WDATA,
+ output logic [31:0] AVL_RDATA,
+
+ output logic AUD_MCLK,
+ AUD_DACDAT,
+
+ I2C_SCLK,
+
+ input logic AUD_ADCDAT,
+
+
+ inout wire AUD_BCLK,
+ AUD_ADCLRCK,
+ AUD_DACLRCK,
+ I2C_SDAT,
+
+ output logic [15:0] LEDR
+);
+
+
+
+logic INIT_FINISH,audio_out_allowed,write_audio_out, write_audio_out_next;
+
+logic [31:0] data [2], data_next[2];
+
+//logic audio_ready,audio_ready_next;
+
+//logic audio_out_allowed;
+assign LEDR = data[0][31:16];
+
+always_ff @(negedge CLK) begin
+ if(RESET) begin
+ data[0] <= 32'h0;
+ data[1] <= 32'h0;
+ write_audio_out <= 0;
+ end else begin
+ data[0] <= data_next[0];
+ data[1] <= data_next[1];
+ write_audio_out <= write_audio_out_next;
+ end
+end
+
+always_comb begin
+ //audio_ready_next = audio_ready;
+ data_next[0] = data[0];
+ data_next[1] = data[1];
+ //INIT = 1'b0;
+ AVL_RDATA = 31'hCCCC;
+ write_audio_out_next = 1'b0;
+
+ if (AVL_WR && AVL_CS) begin
+ if (AVL_ADDR == 2'b00) begin
+ data_next[0] = AVL_WDATA;
+ end
+ if (AVL_ADDR == 2'b01) begin
+ data_next[1] = AVL_WDATA;
+ end
+ // else if (AVL_ADDR == 2'b10)
+ write_audio_out_next = 1'b1;
+ end
+
+
+ if (AVL_RD && AVL_CS) begin
+ if (AVL_ADDR == 2'b00) begin
+ AVL_RDATA = data[0];
+ end
+ if (AVL_ADDR == 2'b11)
+ AVL_RDATA = {31'h0,audio_out_allowed};
+ end
+
+// if (audio_out_allowed) begin
+// audio_ready_next = 1'b1;
+// end else
+// audio_ready_next = 1'b0;
+end
+
+
+Audio_Controller Audio_Controller (
+ // Inputs
+ .CLOCK_50 (CLK),
+ .reset (RESET),
+
+ .clear_audio_in_memory (),
+ .read_audio_in (1'b0),
+
+ .clear_audio_out_memory (),
+ .left_channel_audio_out (data[0]),
+ .right_channel_audio_out (32'b0),
+ .write_audio_out (write_audio_out),
+
+ .AUD_ADCDAT (AUD_ADCDAT),
+
+ // Bidirectionals
+ .AUD_BCLK (AUD_BCLK),
+ .AUD_ADCLRCK (AUD_ADCLRCK),
+ .AUD_DACLRCK (AUD_DACLRCK),
+
+
+ // Outputs
+ .audio_in_available (),
+ .left_channel_audio_in (),
+ .right_channel_audio_in (),
+
+ .audio_out_allowed (audio_out_allowed),
+
+ .AUD_XCK (AUD_MCLK),
+ .AUD_DACDAT (AUD_DACDAT),
+
+);
+
+avconf #(.USE_MIC_INPUT(0)) avc (
+ .I2C_SCLK (I2C_SCLK),
+ .I2C_SDAT (I2C_SDAT),
+ .CLOCK_50 (CLK),
+ .reset (RESET)
+);
+endmodule
diff --git a/audioTop.sv b/audioTop.sv
new file mode 100644
index 0000000000000000000000000000000000000000..78f70ebea969a8276d4d1bbf7d1f1b37e444be4b
--- /dev/null
+++ b/audioTop.sv
@@ -0,0 +1,6 @@
+module audiotest(
+ output
+
+);
+
+endmodule
diff --git a/audio_hw.tcl b/audio_hw.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4ac5fdaf140056e5175a491098085d9a35714827
--- /dev/null
+++ b/audio_hw.tcl
@@ -0,0 +1,168 @@
+# TCL File Generated by Component Editor 17.1
+# Tue Nov 21 02:55:44 CST 2017
+# DO NOT MODIFY
+
+
+#
+# audio "audio" v1.0
+# 2017.11.21.02:55:44
+#
+#
+
+#
+# request TCL package from ACDS 16.1
+#
+package require -exact qsys 16.1
+
+
+#
+# module audio
+#
+set_module_property DESCRIPTION ""
+set_module_property NAME audio
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "Final-osu Custom IPs "
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME audio
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL new_component
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file audio.sv SYSTEM_VERILOG PATH audio.sv TOP_LEVEL_FILE
+add_fileset_file Altera_UP_Audio_Bit_Counter.v VERILOG PATH Audio_Controller/Altera_UP_Audio_Bit_Counter.v
+add_fileset_file Altera_UP_Audio_In_Deserializer.v VERILOG PATH Audio_Controller/Altera_UP_Audio_In_Deserializer.v
+add_fileset_file Altera_UP_Audio_Out_Serializer.v VERILOG PATH Audio_Controller/Altera_UP_Audio_Out_Serializer.v
+add_fileset_file Altera_UP_Clock_Edge.v VERILOG PATH Audio_Controller/Altera_UP_Clock_Edge.v
+add_fileset_file Altera_UP_SYNC_FIFO.v VERILOG PATH Audio_Controller/Altera_UP_SYNC_FIFO.v
+add_fileset_file Audio_Clock.v VERILOG PATH Audio_Controller/Audio_Clock.v
+add_fileset_file Audio_Controller.v VERILOG PATH Audio_Controller/Audio_Controller.v
+add_fileset_file I2C_Controller.v VERILOG PATH avconf/I2C_Controller.v
+add_fileset_file avconf.v VERILOG PATH avconf/avconf.v
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file audio.sv SYSTEM_VERILOG PATH audio.sv
+add_fileset_file Altera_UP_Audio_Bit_Counter.v VERILOG PATH Audio_Controller/Altera_UP_Audio_Bit_Counter.v
+add_fileset_file Altera_UP_Audio_In_Deserializer.v VERILOG PATH Audio_Controller/Altera_UP_Audio_In_Deserializer.v
+add_fileset_file Altera_UP_Audio_Out_Serializer.v VERILOG PATH Audio_Controller/Altera_UP_Audio_Out_Serializer.v
+add_fileset_file Altera_UP_Clock_Edge.v VERILOG PATH Audio_Controller/Altera_UP_Clock_Edge.v
+add_fileset_file Altera_UP_SYNC_FIFO.v VERILOG PATH Audio_Controller/Altera_UP_SYNC_FIFO.v
+add_fileset_file Audio_Clock.v VERILOG PATH Audio_Controller/Audio_Clock.v
+add_fileset_file Audio_Controller.v VERILOG PATH Audio_Controller/Audio_Controller.v
+add_fileset_file I2C_Controller.v VERILOG PATH avconf/I2C_Controller.v
+add_fileset_file avconf.v VERILOG PATH avconf/avconf.v
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point CLK
+#
+add_interface CLK clock end
+set_interface_property CLK clockRate 50000000
+set_interface_property CLK ENABLED true
+set_interface_property CLK EXPORT_OF ""
+set_interface_property CLK PORT_NAME_MAP ""
+set_interface_property CLK CMSIS_SVD_VARIABLES ""
+set_interface_property CLK SVD_ADDRESS_GROUP ""
+
+add_interface_port CLK CLK clk Input 1
+
+
+#
+# connection point RESET
+#
+add_interface RESET reset end
+set_interface_property RESET associatedClock CLK
+set_interface_property RESET synchronousEdges DEASSERT
+set_interface_property RESET ENABLED true
+set_interface_property RESET EXPORT_OF ""
+set_interface_property RESET PORT_NAME_MAP ""
+set_interface_property RESET CMSIS_SVD_VARIABLES ""
+set_interface_property RESET SVD_ADDRESS_GROUP ""
+
+add_interface_port RESET RESET reset Input 1
+
+
+#
+# connection point Audio_Slave
+#
+add_interface Audio_Slave avalon end
+set_interface_property Audio_Slave addressUnits WORDS
+set_interface_property Audio_Slave associatedClock CLK
+set_interface_property Audio_Slave associatedReset RESET
+set_interface_property Audio_Slave bitsPerSymbol 8
+set_interface_property Audio_Slave burstOnBurstBoundariesOnly false
+set_interface_property Audio_Slave burstcountUnits WORDS
+set_interface_property Audio_Slave explicitAddressSpan 0
+set_interface_property Audio_Slave holdTime 0
+set_interface_property Audio_Slave linewrapBursts false
+set_interface_property Audio_Slave maximumPendingReadTransactions 0
+set_interface_property Audio_Slave maximumPendingWriteTransactions 0
+set_interface_property Audio_Slave readLatency 0
+set_interface_property Audio_Slave readWaitStates 0
+set_interface_property Audio_Slave readWaitTime 0
+set_interface_property Audio_Slave setupTime 0
+set_interface_property Audio_Slave timingUnits Cycles
+set_interface_property Audio_Slave writeWaitTime 0
+set_interface_property Audio_Slave ENABLED true
+set_interface_property Audio_Slave EXPORT_OF ""
+set_interface_property Audio_Slave PORT_NAME_MAP ""
+set_interface_property Audio_Slave CMSIS_SVD_VARIABLES ""
+set_interface_property Audio_Slave SVD_ADDRESS_GROUP ""
+
+add_interface_port Audio_Slave AVL_ADDR address Input 2
+add_interface_port Audio_Slave AVL_CS chipselect Input 1
+add_interface_port Audio_Slave AVL_RD read Input 1
+add_interface_port Audio_Slave AVL_WR write Input 1
+add_interface_port Audio_Slave AVL_RDATA readdata Output 32
+add_interface_port Audio_Slave AVL_WDATA writedata Input 32
+set_interface_assignment Audio_Slave embeddedsw.configuration.isFlash 0
+set_interface_assignment Audio_Slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment Audio_Slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment Audio_Slave embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point EXPORT_DATA
+#
+add_interface EXPORT_DATA conduit end
+set_interface_property EXPORT_DATA associatedClock CLK
+set_interface_property EXPORT_DATA associatedReset RESET
+set_interface_property EXPORT_DATA ENABLED true
+set_interface_property EXPORT_DATA EXPORT_OF ""
+set_interface_property EXPORT_DATA PORT_NAME_MAP ""
+set_interface_property EXPORT_DATA CMSIS_SVD_VARIABLES ""
+set_interface_property EXPORT_DATA SVD_ADDRESS_GROUP ""
+
+add_interface_port EXPORT_DATA AUD_MCLK mclk Output 1
+add_interface_port EXPORT_DATA AUD_BCLK bclk Bidir 1
+add_interface_port EXPORT_DATA AUD_ADCDAT adc_data Input 1
+add_interface_port EXPORT_DATA AUD_DACDAT dac_data Output 1
+add_interface_port EXPORT_DATA AUD_DACLRCK dac_clk Bidir 1
+add_interface_port EXPORT_DATA AUD_ADCLRCK adc_clk Bidir 1
+add_interface_port EXPORT_DATA I2C_SDAT i2c_sdat Bidir 1
+add_interface_port EXPORT_DATA I2C_SCLK i2c_sclk Output 1
+add_interface_port EXPORT_DATA LEDR ledr Output 16
+
diff --git a/audio_test.qsys b/audio_test.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..f5d5f83df7453b3c71c0593e9230cf7705a1dd7e
--- /dev/null
+++ b/audio_test.qsys
@@ -0,0 +1,725 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element audio_0
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ }
+ element audio_0.avalon_audio_slave
+ {
+ datum baseAddress
+ {
+ value = "48";
+ type = "String";
+ }
+ }
+ element audio_pll_0
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element nios2_qsys_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element nios2_qsys_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "2048";
+ type = "String";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "0";
+ type = "String";
+ }
+ }
+ element sdram
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ }
+ element sdram.s1
+ {
+ datum baseAddress
+ {
+ value = "268435456";
+ type = "String";
+ }
+ }
+ element sdram_pll
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ }
+ element sdram_pll.pll_slave
+ {
+ datum baseAddress
+ {
+ value = "64";
+ type = "String";
+ }
+ }
+ element sysid_qsys_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ }
+ element sysid_qsys_0.control_slave
+ {
+ datum baseAddress
+ {
+ value = "88";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4CE115F29C7" />
+ <parameter name="deviceFamily" value="Cyclone IV E" />
+ <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="osu_fpga.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="audio_clock"
+ internal="audio_pll_0.audio_clk"
+ type="clock"
+ dir="start" />
+ <interface
+ name="aux"
+ internal="audio_0.external_interface"
+ type="conduit"
+ dir="end" />
+ <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
+ <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
+ <interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
+ <module
+ name="audio_0"
+ kind="altera_up_avalon_audio"
+ version="17.1"
+ enabled="1">
+ <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ <parameter name="audio_in" value="true" />
+ <parameter name="audio_out" value="false" />
+ <parameter name="avalon_bus_type" value="Memory Mapped" />
+ <parameter name="dw" value="32" />
+ </module>
+ <module
+ name="audio_pll_0"
+ kind="altera_up_avalon_audio_pll"
+ version="17.1"
+ enabled="1">
+ <parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+ <parameter name="audio_clk_freq" value="16.9344" />
+ <parameter name="device_family" value="Cyclone IV E" />
+ <parameter name="gui_refclk" value="50.0" />
+ </module>
+ <module name="clk_0" kind="clock_source" version="17.1" enabled="1">
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+ name="nios2_qsys_0"
+ kind="altera_nios2_qsys"
+ version="16.1"
+ enabled="1">
+ <parameter name="bht_ramBlockType" value="Automatic" />
+ <parameter name="breakOffset" value="32" />
+ <parameter name="breakSlave">nios2_qsys_0.jtag_debug_module</parameter>
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="cpuID_stored" value="0" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="dataAddrWidth" value="29" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x0' end='0x10' /><slave name='audio_0.avalon_audio_slave' start='0x30' end='0x40' /><slave name='sdram_pll.pll_slave' start='0x40' end='0x50' /><slave name='sysid_qsys_0.control_slave' start='0x58' end='0x60' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x800' end='0x1000' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dcache_lineSize" value="32" />
+ <parameter name="dcache_numTCDM" value="0" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_size" value="2048" />
+ <parameter name="dcache_tagramBlockType" value="Automatic" />
+ <parameter name="dcache_victim_buf_impl" value="ram" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="deviceFamilyName" value="Cyclone IV E" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="exceptionSlave" value="sdram.s1" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="icache_numTCIM" value="0" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_size" value="4096" />
+ <parameter name="icache_tagramBlockType" value="Automatic" />
+ <parameter name="impl" value="Tiny" />
+ <parameter name="instAddrWidth" value="29" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x0' end='0x10' /><slave name='audio_0.avalon_audio_slave' start='0x30' end='0x40' /><slave name='sdram_pll.pll_slave' start='0x40' end='0x50' /><slave name='sysid_qsys_0.control_slave' start='0x58' end='0x60' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x800' end='0x1000' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
+ <parameter name="internalIrqMaskSystemInfo" value="0" />
+ <parameter name="manuallyAssignCpuID" value="true" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="mmu_TLBMissExcSlave" value="None" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_processIDNumBits" value="8" />
+ <parameter name="mmu_ramBlockType" value="Automatic" />
+ <parameter name="mmu_tlbNumWays" value="16" />
+ <parameter name="mmu_tlbPtrSz" value="7" />
+ <parameter name="mmu_udtlbNumEntries" value="6" />
+ <parameter name="mmu_uitlbNumEntries" value="4" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mpu_minDataRegionSize" value="12" />
+ <parameter name="mpu_minInstRegionSize" value="12" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
+ <parameter name="ocimem_ramBlockType" value="Automatic" />
+ <parameter name="regfile_ramBlockType" value="Automatic" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="resetSlave" value="sdram.s1" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTrace_user" value="false" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_asic_enabled" value="false" />
+ <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_bhtPtrSz" value="8" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_breakslaveoveride" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_dc_ecc_present" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_dtcm_ecc_present" value="false" />
+ <parameter name="setting_ecc_present" value="false" />
+ <parameter name="setting_ecc_sim_test_ports" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_export_large_RAMs" value="false" />
+ <parameter name="setting_exportvectors" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_ic_ecc_present" value="true" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_itcm_ecc_present" value="false" />
+ <parameter name="setting_mmu_ecc_present" value="true" />
+ <parameter name="setting_oci_export_jtag_signals" value="false" />
+ <parameter name="setting_perfCounterWidth" value="32" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_removeRAMinit" value="false" />
+ <parameter name="setting_rf_ecc_present" value="true" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+ name="onchip_memory2_0"
+ kind="altera_avalon_onchip_memory2"
+ version="17.1"
+ enabled="1">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
+ <parameter name="blockType" value="AUTO" />
+ <parameter name="copyInitFile" value="false" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="dataWidth2" value="32" />
+ <parameter name="deviceFamily" value="Cyclone IV E" />
+ <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="dualPort" value="false" />
+ <parameter name="ecc_enabled" value="false" />
+ <parameter name="enPRInitMode" value="false" />
+ <parameter name="enableDiffWidth" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_mem.hex" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="16" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="false" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ name="sdram"
+ kind="altera_avalon_new_sdram_controller"
+ version="17.1"
+ enabled="1">
+ <parameter name="TAC" value="5.5" />
+ <parameter name="TMRD" value="3" />
+ <parameter name="TRCD" value="20.0" />
+ <parameter name="TRFC" value="70.0" />
+ <parameter name="TRP" value="20.0" />
+ <parameter name="TWR" value="14.0" />
+ <parameter name="casLatency" value="3" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="columnWidth" value="10" />
+ <parameter name="componentName" value="$${FILENAME}_sdram" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="generateSimulationModel" value="false" />
+ <parameter name="initNOPDelay" value="0.0" />
+ <parameter name="initRefreshCommands" value="2" />
+ <parameter name="masteredTristateBridgeSlave" value="0" />
+ <parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
+ <parameter name="numberOfBanks" value="4" />
+ <parameter name="numberOfChipSelects" value="1" />
+ <parameter name="pinsSharedViaTriState" value="false" />
+ <parameter name="powerUpDelay" value="200.0" />
+ <parameter name="refreshPeriod" value="7.8125" />
+ <parameter name="registerDataIn" value="true" />
+ <parameter name="rowWidth" value="13" />
+ </module>
+ <module name="sdram_pll" kind="altpll" version="17.1" enabled="1">
+ <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+ <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+ <parameter name="BANDWIDTH" value="" />
+ <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+ <parameter name="CLK0_DIVIDE_BY" value="1" />
+ <parameter name="CLK0_DUTY_CYCLE" value="50" />
+ <parameter name="CLK0_MULTIPLY_BY" value="1" />
+ <parameter name="CLK0_PHASE_SHIFT" value="0" />
+ <parameter name="CLK1_DIVIDE_BY" value="1" />
+ <parameter name="CLK1_DUTY_CYCLE" value="50" />
+ <parameter name="CLK1_MULTIPLY_BY" value="1" />
+ <parameter name="CLK1_PHASE_SHIFT" value="-3000" />
+ <parameter name="CLK2_DIVIDE_BY" value="" />
+ <parameter name="CLK2_DUTY_CYCLE" value="" />
+ <parameter name="CLK2_MULTIPLY_BY" value="" />
+ <parameter name="CLK2_PHASE_SHIFT" value="" />
+ <parameter name="CLK3_DIVIDE_BY" value="" />
+ <parameter name="CLK3_DUTY_CYCLE" value="" />
+ <parameter name="CLK3_MULTIPLY_BY" value="" />
+ <parameter name="CLK3_PHASE_SHIFT" value="" />
+ <parameter name="CLK4_DIVIDE_BY" value="" />
+ <parameter name="CLK4_DUTY_CYCLE" value="" />
+ <parameter name="CLK4_MULTIPLY_BY" value="" />
+ <parameter name="CLK4_PHASE_SHIFT" value="" />
+ <parameter name="CLK5_DIVIDE_BY" value="" />
+ <parameter name="CLK5_DUTY_CYCLE" value="" />
+ <parameter name="CLK5_MULTIPLY_BY" value="" />
+ <parameter name="CLK5_PHASE_SHIFT" value="" />
+ <parameter name="CLK6_DIVIDE_BY" value="" />
+ <parameter name="CLK6_DUTY_CYCLE" value="" />
+ <parameter name="CLK6_MULTIPLY_BY" value="" />
+ <parameter name="CLK6_PHASE_SHIFT" value="" />
+ <parameter name="CLK7_DIVIDE_BY" value="" />
+ <parameter name="CLK7_DUTY_CYCLE" value="" />
+ <parameter name="CLK7_MULTIPLY_BY" value="" />
+ <parameter name="CLK7_PHASE_SHIFT" value="" />
+ <parameter name="CLK8_DIVIDE_BY" value="" />
+ <parameter name="CLK8_DUTY_CYCLE" value="" />
+ <parameter name="CLK8_MULTIPLY_BY" value="" />
+ <parameter name="CLK8_PHASE_SHIFT" value="" />
+ <parameter name="CLK9_DIVIDE_BY" value="" />
+ <parameter name="CLK9_DUTY_CYCLE" value="" />
+ <parameter name="CLK9_MULTIPLY_BY" value="" />
+ <parameter name="CLK9_PHASE_SHIFT" value="" />
+ <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+ <parameter name="DOWN_SPREAD" value="" />
+ <parameter name="DPA_DIVIDER" value="" />
+ <parameter name="DPA_DIVIDE_BY" value="" />
+ <parameter name="DPA_MULTIPLY_BY" value="" />
+ <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+ <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+ <parameter name="FEEDBACK_SOURCE" value="" />
+ <parameter name="GATE_LOCK_COUNTER" value="" />
+ <parameter name="GATE_LOCK_SIGNAL" value="" />
+ <parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -3000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED</parameter>
+ <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+ <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+ <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+ <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+ <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+ <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+ <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 50.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -3.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1508024956919499.mif PT#ACTIVECLK_CHECK 0</parameter>
+ <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+ <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+ <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Cyclone IV E" />
+ <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="LOCK_HIGH" value="" />
+ <parameter name="LOCK_LOW" value="" />
+ <parameter name="OPERATION_MODE" value="NORMAL" />
+ <parameter name="PLL_TYPE" value="AUTO" />
+ <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+ <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+ <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+ <parameter name="PORT_ENABLE0" value="" />
+ <parameter name="PORT_ENABLE1" value="" />
+ <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+ <parameter name="PORT_FBOUT" value="" />
+ <parameter name="PORT_INCLK0" value="PORT_USED" />
+ <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+ <parameter name="PORT_LOCKED" value="PORT_UNUSED" />
+ <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+ <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCLKOUT0" value="" />
+ <parameter name="PORT_SCLKOUT1" value="" />
+ <parameter name="PORT_VCOOVERRANGE" value="" />
+ <parameter name="PORT_VCOUNDERRANGE" value="" />
+ <parameter name="PORT_clk0" value="PORT_USED" />
+ <parameter name="PORT_clk1" value="PORT_USED" />
+ <parameter name="PORT_clk2" value="PORT_UNUSED" />
+ <parameter name="PORT_clk3" value="PORT_UNUSED" />
+ <parameter name="PORT_clk4" value="PORT_UNUSED" />
+ <parameter name="PORT_clk5" value="PORT_UNUSED" />
+ <parameter name="PORT_clk6" value="" />
+ <parameter name="PORT_clk7" value="" />
+ <parameter name="PORT_clk8" value="" />
+ <parameter name="PORT_clk9" value="" />
+ <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+ <parameter name="PORT_extclkena0" value="" />
+ <parameter name="PORT_extclkena1" value="" />
+ <parameter name="PORT_extclkena2" value="" />
+ <parameter name="PORT_extclkena3" value="" />
+ <parameter name="PRIMARY_CLOCK" value="" />
+ <parameter name="QUALIFY_CONF_DONE" value="" />
+ <parameter name="SCAN_CHAIN" value="" />
+ <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+ <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+ <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+ <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+ <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+ <parameter name="SKIP_VCO" value="" />
+ <parameter name="SPREAD_FREQUENCY" value="" />
+ <parameter name="SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+ <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+ <parameter name="SWITCH_OVER_TYPE" value="" />
+ <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+ <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="VCO_DIVIDE_BY" value="" />
+ <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+ <parameter name="VCO_MULTIPLY_BY" value="" />
+ <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+ <parameter name="WIDTH_CLOCK" value="5" />
+ <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module
+ name="sysid_qsys_0"
+ kind="altera_avalon_sysid_qsys"
+ version="17.1"
+ enabled="1">
+ <parameter name="id" value="0" />
+ </module>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.data_master"
+ end="audio_0.avalon_audio_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0030" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.data_master"
+ end="sysid_qsys_0.control_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0058" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.data_master"
+ end="nios2_qsys_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0800" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.data_master"
+ end="sdram_pll.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0040" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.data_master"
+ end="sdram.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x10000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.instruction_master"
+ end="audio_0.avalon_audio_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0030" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.instruction_master"
+ end="sysid_qsys_0.control_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0058" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.instruction_master"
+ end="nios2_qsys_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0800" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.instruction_master"
+ end="sdram_pll.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0040" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
+ start="nios2_qsys_0.instruction_master"
+ end="sdram.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x10000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="17.1" start="clk_0.clk" end="audio_0.clk" />
+ <connection kind="clock" version="17.1" start="clk_0.clk" end="nios2_qsys_0.clk" />
+ <connection kind="clock" version="17.1" start="clk_0.clk" end="sdram.clk" />
+ <connection kind="clock" version="17.1" start="clk_0.clk" end="sysid_qsys_0.clk" />
+ <connection
+ kind="clock"
+ version="17.1"
+ start="clk_0.clk"
+ end="onchip_memory2_0.clk1" />
+ <connection
+ kind="clock"
+ version="17.1"
+ start="clk_0.clk"
+ end="sdram_pll.inclk_interface" />
+ <connection
+ kind="clock"
+ version="17.1"
+ start="clk_0.clk"
+ end="audio_pll_0.ref_clk" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_0.clk_reset"
+ end="sdram_pll.inclk_interface_reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_0.clk_reset"
+ end="audio_pll_0.ref_reset" />
+ <connection kind="reset" version="17.1" start="clk_0.clk_reset" end="sdram.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_0.clk_reset"
+ end="sysid_qsys_0.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_0.clk_reset"
+ end="audio_0.reset" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_0.clk_reset"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="17.1"
+ start="clk_0.clk_reset"
+ end="nios2_qsys_0.reset_n" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/audio_test_top.sv b/audio_test_top.sv
new file mode 100644
index 0000000000000000000000000000000000000000..ce9731b6fadd4e678238caa5b4ecf975acc3995f
--- /dev/null
+++ b/audio_test_top.sv
@@ -0,0 +1,52 @@
+module audio_test_top (
+ input logic CLOCK_50,
+ input logic [1:0] KEY,
+ output logic [7:0] LEDG,
+ output logic [17:0] LEDR,
+ //output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
+ output logic [12:0] DRAM_ADDR,
+ output logic [1:0] DRAM_BA,
+ output logic DRAM_CAS_N, DRAM_CKE, DRAM_CS_N,
+ inout wire [31:0] DRAM_DQ,
+ output logic [3:0] DRAM_DQM,
+ output logic DRAM_RAS_N, DRAM_WE_N, DRAM_CLK,
+ output logic AUD_XCK,
+ AUD_DACDAT,
+
+ I2C_SCLK,
+
+ input logic AUD_ADCDAT,
+
+
+ inout wire AUD_BCLK,
+ AUD_ADCLRCK,
+ AUD_DACLRCK,
+ I2C_SDAT
+
+ //output wire [15:0] LEDR
+);
+ otogame main_soc (
+ .clk_clk(CLOCK_50),
+ .reset_reset_n(KEY[0]),
+ .sdram_wire_addr(DRAM_ADDR),
+ .sdram_wire_ba(DRAM_BA),
+ .sdram_wire_cas_n(DRAM_CAS_N),
+ .sdram_wire_cke(DRAM_CKE),
+ .sdram_wire_cs_n(DRAM_CS_N),
+ .sdram_wire_dq(DRAM_DQ),
+ .sdram_wire_dqm(DRAM_DQM),
+ .sdram_wire_ras_n(DRAM_RAS_N),
+ .sdram_wire_we_n(DRAM_WE_N),
+ .sdram_clk_clk(DRAM_CLK),
+ .audio_mclk(AUD_XCK), // audio.mclk
+ .audio_bclk(AUD_BCLK), // .bclk
+ .audio_adc_data( AUD_ADCDAT), // .adc_data
+ .audio_dac_data(AUD_DACDAT), // .dac_data
+ .audio_dac_clk(AUD_DACLRCK), // .dac_clk
+ .audio_adc_clk(AUD_ADCLRCK), // .adc_clk
+ .audio_i2c_sdat(I2C_SDAT), // .i2c_sdat
+ .audio_i2c_sclk(I2C_SCLK),
+ .audio_ledr(LEDR[15:0])
+ );
+
+endmodule
diff --git a/avconf/I2C_Controller.v b/avconf/I2C_Controller.v
new file mode 100644
index 0000000000000000000000000000000000000000..708efb52c2466f5eca0f1c02256cc94c917a96ff
--- /dev/null
+++ b/avconf/I2C_Controller.v
@@ -0,0 +1,147 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2005 by Terasic Technologies Inc.
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+// Terasic grants permission to use and modify this code for use
+// in synthesis for all Terasic Development Boards and Altrea Development
+// Kits made by Terasic. Other use of this code, including the selling
+// ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+// This VHDL or Verilog source code is intended as a design reference
+// which illustrates how these types of functions can be implemented.
+// It is the user's responsibility to verify their design for
+// consistency and functionality through the use of formal
+// verification methods. Terasic provides no warranty regarding the use
+// or functionality of this code.
+//
+// --------------------------------------------------------------------
+//
+// Terasic Technologies Inc
+// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+// HsinChu County, Taiwan
+// 302
+//
+// web: http://www.terasic.com/
+// email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:i2c controller
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+// Ver :| Author :| Mod. Date :| Changes Made:
+// V1.0 :| Joe Yang :| 05/07/10 :| Initial Revision
+// --------------------------------------------------------------------
+module I2C_Controller (
+ CLOCK,
+ I2C_SCLK,//I2C CLOCK
+ I2C_SDAT,//I2C DATA
+ I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+ GO, //GO transfor
+ END, //END transfor
+ W_R, //W_R
+ ACK, //ACK
+ RESET,
+ //TEST
+ SD_COUNTER,
+ SDO
+);
+ input CLOCK;
+ input [23:0]I2C_DATA;
+ input GO;
+ input RESET;
+ input W_R;
+ inout I2C_SDAT;
+ output I2C_SCLK;
+ output END;
+ output ACK;
+
+//TEST
+ output [5:0] SD_COUNTER;
+ output SDO;
+
+
+reg SDO;
+reg SCLK;
+reg END;
+reg [23:0]SD;
+reg [5:0]SD_COUNTER;
+
+wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=30))? ~CLOCK :0 );
+wire I2C_SDAT=SDO?1'bz:0 ;
+
+reg ACK1,ACK2,ACK3;
+wire ACK=ACK1 | ACK2 |ACK3;
+
+//--I2C COUNTER
+always @(negedge RESET or posedge CLOCK ) begin
+if (!RESET) SD_COUNTER=6'b111111;
+else begin
+if (GO==0)
+ SD_COUNTER=0;
+ else
+ if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER+1;
+end
+end
+//----
+
+always @(negedge RESET or posedge CLOCK ) begin
+if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end
+else
+case (SD_COUNTER)
+ 6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end
+ //start
+ 6'd1 : begin SD=I2C_DATA;SDO=0;end
+ 6'd2 : SCLK=0;
+ //SLAVE ADDR
+ 6'd3 : SDO=SD[23];
+ 6'd4 : SDO=SD[22];
+ 6'd5 : SDO=SD[21];
+ 6'd6 : SDO=SD[20];
+ 6'd7 : SDO=SD[19];
+ 6'd8 : SDO=SD[18];
+ 6'd9 : SDO=SD[17];
+ 6'd10 : SDO=SD[16];
+ 6'd11 : SDO=1'b1;//ACK
+
+ //SUB ADDR
+ 6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end
+ 6'd13 : SDO=SD[14];
+ 6'd14 : SDO=SD[13];
+ 6'd15 : SDO=SD[12];
+ 6'd16 : SDO=SD[11];
+ 6'd17 : SDO=SD[10];
+ 6'd18 : SDO=SD[9];
+ 6'd19 : SDO=SD[8];
+ 6'd20 : SDO=1'b1;//ACK
+
+ //DATA
+ 6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end
+ 6'd22 : SDO=SD[6];
+ 6'd23 : SDO=SD[5];
+ 6'd24 : SDO=SD[4];
+ 6'd25 : SDO=SD[3];
+ 6'd26 : SDO=SD[2];
+ 6'd27 : SDO=SD[1];
+ 6'd28 : SDO=SD[0];
+ 6'd29 : SDO=1'b1;//ACK
+
+
+ //stop
+ 6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end
+ 6'd31 : SCLK=1'b1;
+ 6'd32 : begin SDO=1'b1; END=1; end
+
+endcase
+end
+
+
+
+endmodule
diff --git a/avconf/avconf.v b/avconf/avconf.v
new file mode 100644
index 0000000000000000000000000000000000000000..e6f31f6ab873d2facf593811465bbfe4d630ff64
--- /dev/null
+++ b/avconf/avconf.v
@@ -0,0 +1,186 @@
+module avconf ( // Host Side
+ CLOCK_50,
+ reset,
+ // I2C Side
+ I2C_SCLK,
+ I2C_SDAT );
+// Host Side
+input CLOCK_50;
+input reset;
+// I2C Side
+output I2C_SCLK;
+inout I2C_SDAT;
+// Internal Registers/Wires
+reg [15:0] mI2C_CLK_DIV;
+reg [23:0] mI2C_DATA;
+reg mI2C_CTRL_CLK;
+reg mI2C_GO;
+wire mI2C_END;
+wire mI2C_ACK;
+wire iRST_N = !reset;
+reg [15:0] LUT_DATA;
+reg [5:0] LUT_INDEX;
+reg [3:0] mSetup_ST;
+
+parameter USE_MIC_INPUT = 1'b0;
+
+parameter AUD_LINE_IN_LC = 9'd24;
+parameter AUD_LINE_IN_RC = 9'd24;
+parameter AUD_LINE_OUT_LC = 9'd119;
+parameter AUD_LINE_OUT_RC = 9'd119;
+parameter AUD_ADC_PATH = 9'd17;
+parameter AUD_DAC_PATH = 9'd6;
+parameter AUD_POWER = 9'h000;
+parameter AUD_DATA_FORMAT = 9'd77;
+parameter AUD_SAMPLE_CTRL = 9'd0;
+parameter AUD_SET_ACTIVE = 9'h001;
+
+// Clock Setting
+parameter CLK_Freq = 50000000; // 50 MHz
+parameter I2C_Freq = 20000; // 20 KHz
+// LUT Data Number
+parameter LUT_SIZE = 50;
+// Audio Data Index
+parameter SET_LIN_L = 0;
+parameter SET_LIN_R = 1;
+parameter SET_HEAD_L = 2;
+parameter SET_HEAD_R = 3;
+parameter A_PATH_CTRL = 4;
+parameter D_PATH_CTRL = 5;
+parameter POWER_ON = 6;
+parameter SET_FORMAT = 7;
+parameter SAMPLE_CTRL = 8;
+parameter SET_ACTIVE = 9;
+// Video Data Index
+parameter SET_VIDEO = 10;
+
+///////////////////// I2C Control Clock ////////////////////////
+always@(posedge CLOCK_50 or negedge iRST_N)
+begin
+ if(!iRST_N)
+ begin
+ mI2C_CTRL_CLK <= 0;
+ mI2C_CLK_DIV <= 0;
+ end
+ else
+ begin
+ if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
+ mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
+ else
+ begin
+ mI2C_CLK_DIV <= 0;
+ mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
+ end
+ end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
+ .I2C_SCLK(I2C_SCLK), // I2C CLOCK
+ .I2C_SDAT(I2C_SDAT), // I2C DATA
+ .I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+ .GO(mI2C_GO), // GO transfor
+ .END(mI2C_END), // END transfor
+ .ACK(mI2C_ACK), // ACK
+ .RESET(iRST_N) );
+////////////////////////////////////////////////////////////////////
+////////////////////// Config Control ////////////////////////////
+always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+begin
+ if(!iRST_N)
+ begin
+ LUT_INDEX <= 0;
+ mSetup_ST <= 0;
+ mI2C_GO <= 0;
+ end
+ else
+ begin
+ if(LUT_INDEX<LUT_SIZE)
+ begin
+ case(mSetup_ST)
+ 0: begin
+ if(LUT_INDEX<SET_VIDEO)
+ mI2C_DATA <= {8'h34,LUT_DATA};
+ else
+ mI2C_DATA <= {8'h40,LUT_DATA};
+ mI2C_GO <= 1;
+ mSetup_ST <= 1;
+ end
+ 1: begin
+ if(mI2C_END)
+ begin
+ if(!mI2C_ACK)
+ mSetup_ST <= 2;
+ else
+ mSetup_ST <= 0;
+ mI2C_GO <= 0;
+ end
+ end
+ 2: begin
+ LUT_INDEX <= LUT_INDEX+1;
+ mSetup_ST <= 0;
+ end
+ endcase
+ end
+ end
+end
+////////////////////////////////////////////////////////////////////
+///////////////////// Config Data LUT //////////////////////////
+always
+begin
+ case(LUT_INDEX)
+ // Audio Config Data
+ SET_LIN_L : LUT_DATA <= {7'h0, AUD_LINE_IN_LC};
+ SET_LIN_R : LUT_DATA <= {7'h1, AUD_LINE_IN_RC};
+ SET_HEAD_L : LUT_DATA <= {7'h2, AUD_LINE_OUT_LC};
+ SET_HEAD_R : LUT_DATA <= {7'h3, AUD_LINE_OUT_RC};
+ A_PATH_CTRL : LUT_DATA <= {7'h4, AUD_ADC_PATH} + (16'h0004 * USE_MIC_INPUT);
+ D_PATH_CTRL : LUT_DATA <= {7'h5, AUD_DAC_PATH};
+ POWER_ON : LUT_DATA <= {7'h6, AUD_POWER};
+ SET_FORMAT : LUT_DATA <= {7'h7, AUD_DATA_FORMAT};
+ SAMPLE_CTRL : LUT_DATA <= {7'h8, AUD_SAMPLE_CTRL};
+ SET_ACTIVE : LUT_DATA <= {7'h9, AUD_SET_ACTIVE};
+ // Video Config Data
+ SET_VIDEO+0 : LUT_DATA <= 16'h1500;
+ SET_VIDEO+1 : LUT_DATA <= 16'h1741;
+ SET_VIDEO+2 : LUT_DATA <= 16'h3a16;
+ SET_VIDEO+3 : LUT_DATA <= 16'h503f; // 16'h5004;
+ SET_VIDEO+4 : LUT_DATA <= 16'hc305;
+ SET_VIDEO+5 : LUT_DATA <= 16'hc480;
+ SET_VIDEO+6 : LUT_DATA <= 16'h0e80;
+ SET_VIDEO+7 : LUT_DATA <= 16'h503f; // 16'h5020;
+ SET_VIDEO+8 : LUT_DATA <= 16'h5218;
+ SET_VIDEO+9 : LUT_DATA <= 16'h58ed;
+ SET_VIDEO+10: LUT_DATA <= 16'h77c5;
+ SET_VIDEO+11: LUT_DATA <= 16'h7c93;
+ SET_VIDEO+12: LUT_DATA <= 16'h7d00;
+ SET_VIDEO+13: LUT_DATA <= 16'hd048;
+ SET_VIDEO+14: LUT_DATA <= 16'hd5a0;
+ SET_VIDEO+15: LUT_DATA <= 16'hd7ea;
+ SET_VIDEO+16: LUT_DATA <= 16'he43e;
+ SET_VIDEO+17: LUT_DATA <= 16'hea0f;
+ SET_VIDEO+18: LUT_DATA <= 16'h3112;
+ SET_VIDEO+19: LUT_DATA <= 16'h3281;
+ SET_VIDEO+20: LUT_DATA <= 16'h3384;
+ SET_VIDEO+21: LUT_DATA <= 16'h37A0;
+ SET_VIDEO+22: LUT_DATA <= 16'he580;
+ SET_VIDEO+23: LUT_DATA <= 16'he603;
+ SET_VIDEO+24: LUT_DATA <= 16'he785;
+ SET_VIDEO+25: LUT_DATA <= 16'h2778; // 16'h503f; // 16'h5000;
+ SET_VIDEO+26: LUT_DATA <= 16'h5100;
+ SET_VIDEO+27: LUT_DATA <= 16'h0050;
+ SET_VIDEO+28: LUT_DATA <= 16'h1000;
+ SET_VIDEO+29: LUT_DATA <= 16'h0402;
+ SET_VIDEO+30: LUT_DATA <= 16'h0860;
+ SET_VIDEO+31: LUT_DATA <= 16'h0a18;
+ SET_VIDEO+32: LUT_DATA <= 16'h1100;
+ SET_VIDEO+33: LUT_DATA <= 16'h2b00;
+ SET_VIDEO+34: LUT_DATA <= 16'h2c8c;
+ SET_VIDEO+35: LUT_DATA <= 16'h2df8;
+ SET_VIDEO+36: LUT_DATA <= 16'h2eee;
+ SET_VIDEO+37: LUT_DATA <= 16'h2ff4;
+ SET_VIDEO+38: LUT_DATA <= 16'h30d2;
+ SET_VIDEO+39: LUT_DATA <= 16'h0e05;
+ endcase
+end
+////////////////////////////////////////////////////////////////////
+endmodule
diff --git a/osu_fpga_toplevel.qsf b/osu_fpga_toplevel.qsf
index 480fe63973260d581458f996e83a1a66f7531834..b4c6f6c644c6e0861821a49b53ae1f6522d04848 100644
--- a/osu_fpga_toplevel.qsf
+++ b/osu_fpga_toplevel.qsf
@@ -1,66 +1,29 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2017 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other
-# applicable license agreement, including, without limitation,
-# that your use is for the sole purpose of programming logic
-# devices manufactured by Intel and sold by Intel or its
-# authorized distributors. Please refer to the applicable
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-# Date created = 23:41:32 November 11, 2017
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# osu_fpga_toplevel_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
+set_global_assignment -name TOP_LEVEL_ENTITY audio_test_top
+#============================================================
+# Build by Altera University Program
+#============================================================
set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY osu_fpga_toplevel
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:41:32 NOVEMBER 11, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name DEVICE EP4CE115F29C8
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+#============================================================
+# CLOCK
+#============================================================
set_location_assignment PIN_Y2 -to CLOCK_50
set_location_assignment PIN_AG14 -to CLOCK2_50
set_location_assignment PIN_AG15 -to CLOCK3_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50
+
+
+#============================================================
+# Sma
+#============================================================
set_location_assignment PIN_AH14 -to SMA_CLKIN
set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT
+
+#============================================================
+# LED
+#============================================================
set_location_assignment PIN_E21 -to LEDG[0]
set_location_assignment PIN_E22 -to LEDG[1]
set_location_assignment PIN_E25 -to LEDG[2]
@@ -70,15 +33,7 @@ set_location_assignment PIN_G20 -to LEDG[5]
set_location_assignment PIN_G22 -to LEDG[6]
set_location_assignment PIN_G21 -to LEDG[7]
set_location_assignment PIN_F17 -to LEDG[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8]
+
set_location_assignment PIN_G19 -to LEDR[0]
set_location_assignment PIN_E19 -to LEDR[2]
set_location_assignment PIN_F19 -to LEDR[1]
@@ -97,31 +52,18 @@ set_location_assignment PIN_F15 -to LEDR[14]
set_location_assignment PIN_G15 -to LEDR[15]
set_location_assignment PIN_G16 -to LEDR[16]
set_location_assignment PIN_H15 -to LEDR[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17]
+
+#============================================================
+# KEY
+#============================================================
set_location_assignment PIN_M23 -to KEY[0]
set_location_assignment PIN_M21 -to KEY[1]
set_location_assignment PIN_N21 -to KEY[2]
set_location_assignment PIN_R24 -to KEY[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3]
+
+#============================================================
+# SW
+#============================================================
set_location_assignment PIN_AB28 -to SW[0]
set_location_assignment PIN_AC28 -to SW[1]
set_location_assignment PIN_AC27 -to SW[2]
@@ -140,24 +82,10 @@ set_location_assignment PIN_AA23 -to SW[14]
set_location_assignment PIN_AA22 -to SW[15]
set_location_assignment PIN_Y24 -to SW[16]
set_location_assignment PIN_Y23 -to SW[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17]
+
+#============================================================
+# SEG7
+#============================================================
set_location_assignment PIN_G18 -to HEX0[0]
set_location_assignment PIN_F22 -to HEX0[1]
set_location_assignment PIN_E17 -to HEX0[2]
@@ -214,62 +142,10 @@ set_location_assignment PIN_AH17 -to HEX7[3]
set_location_assignment PIN_AF17 -to HEX7[4]
set_location_assignment PIN_AG18 -to HEX7[5]
set_location_assignment PIN_AA14 -to HEX7[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6]
+
+#============================================================
+# LCD
+#============================================================
set_location_assignment PIN_L6 -to LCD_BLON
set_location_assignment PIN_M5 -to LCD_DATA[7]
set_location_assignment PIN_M3 -to LCD_DATA[6]
@@ -283,35 +159,26 @@ set_location_assignment PIN_L4 -to LCD_EN
set_location_assignment PIN_M1 -to LCD_RW
set_location_assignment PIN_M2 -to LCD_RS
set_location_assignment PIN_L5 -to LCD_ON
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON
+
+#============================================================
+# RS232
+#============================================================
set_location_assignment PIN_G9 -to UART_TXD
set_location_assignment PIN_G12 -to UART_RXD
set_location_assignment PIN_G14 -to UART_CTS
set_location_assignment PIN_J13 -to UART_RTS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+#============================================================
+# PS2
+#============================================================
set_location_assignment PIN_G6 -to PS2_KBCLK
set_location_assignment PIN_H5 -to PS2_KBDAT
set_location_assignment PIN_G5 -to PS2_MSCLK
set_location_assignment PIN_F5 -to PS2_MSDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT
+
+#============================================================
+# SDCARD
+#============================================================
set_location_assignment PIN_AE14 -to SD_DAT[0]
set_location_assignment PIN_AF13 -to SD_DAT[1]
set_location_assignment PIN_AB14 -to SD_DAT[2]
@@ -319,13 +186,10 @@ set_location_assignment PIN_AC14 -to SD_DAT[3]
set_location_assignment PIN_AE13 -to SD_CLK
set_location_assignment PIN_AD14 -to SD_CMD
set_location_assignment PIN_AF14 -to SD_WP_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3]
+
+#============================================================
+# VGA
+#============================================================
set_location_assignment PIN_D12 -to VGA_B[7]
set_location_assignment PIN_D11 -to VGA_B[6]
set_location_assignment PIN_C12 -to VGA_B[5]
@@ -355,55 +219,32 @@ set_location_assignment PIN_F11 -to VGA_BLANK_N
set_location_assignment PIN_C10 -to VGA_SYNC_N
set_location_assignment PIN_G13 -to VGA_HS
set_location_assignment PIN_C13 -to VGA_VS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7]
+
+#============================================================
+# Audio
+#============================================================
set_location_assignment PIN_D1 -to AUD_DACDAT
set_location_assignment PIN_E3 -to AUD_DACLRCK
set_location_assignment PIN_D2 -to AUD_ADCDAT
set_location_assignment PIN_C2 -to AUD_ADCLRCK
set_location_assignment PIN_E1 -to AUD_XCK
set_location_assignment PIN_F2 -to AUD_BCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
+
+#============================================================
+# I2C for EEPROM
+#============================================================
set_location_assignment PIN_D14 -to EEP_I2C_SCLK
set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT
+
+#============================================================
+# I2C for Audioand Tv-Decode 1 and 2
+#============================================================
set_location_assignment PIN_B7 -to I2C_SCLK
set_location_assignment PIN_A8 -to I2C_SDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
+
+#============================================================
+# Ethernet 0
+#============================================================
set_location_assignment PIN_A17 -to ENET0_GTX_CLK
set_location_assignment PIN_A21 -to ENET0_INT_N
set_location_assignment PIN_C20 -to ENET0_MDC
@@ -425,25 +266,10 @@ set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
set_location_assignment PIN_A18 -to ENET0_TX_EN
set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RESET_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO
+
+#============================================================
+# Ethernet 1
+#============================================================
set_location_assignment PIN_C23 -to ENET1_GTX_CLK
set_location_assignment PIN_D24 -to ENET1_INT_N
set_location_assignment PIN_D23 -to ENET1_MDC
@@ -465,30 +291,14 @@ set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
set_location_assignment PIN_B25 -to ENET1_TX_EN
set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RESET_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO
+
set_location_assignment PIN_C14 -to ENET0_LINK100
set_location_assignment PIN_D13 -to ENET1_LINK100
set_location_assignment PIN_A14 -to ENETCLK_25
+
+#============================================================
+# TV Decoder
+#============================================================
set_location_assignment PIN_F7 -to TD_DATA[7]
set_location_assignment PIN_E7 -to TD_DATA[6]
set_location_assignment PIN_D6 -to TD_DATA[5]
@@ -501,18 +311,10 @@ set_location_assignment PIN_B14 -to TD_CLK27
set_location_assignment PIN_G7 -to TD_RESET_N
set_location_assignment PIN_E4 -to TD_VS
set_location_assignment PIN_E5 -to TD_HS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7]
+
+#============================================================
+# USB
+#============================================================
set_location_assignment PIN_D4 -to OTG_DACK_N[1]
set_location_assignment PIN_C4 -to OTG_DACK_N[0]
set_location_assignment PIN_A3 -to OTG_CS_N
@@ -543,38 +345,15 @@ set_location_assignment PIN_G3 -to OTG_DATA[12]
set_location_assignment PIN_F1 -to OTG_DATA[13]
set_location_assignment PIN_F3 -to OTG_DATA[14]
set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_OE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED
+
+#============================================================
+# IR Receiver
+#============================================================
set_location_assignment PIN_Y15 -to IRDA_RXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD
+
+#============================================================
+# SDRAM
+#============================================================
set_location_assignment PIN_AE5 -to DRAM_CLK
set_location_assignment PIN_U1 -to DRAM_DQ[31]
set_location_assignment PIN_U4 -to DRAM_DQ[30]
@@ -632,63 +411,10 @@ set_location_assignment PIN_P1 -to DRAM_ADDR[3]
set_location_assignment PIN_U8 -to DRAM_ADDR[2]
set_location_assignment PIN_V8 -to DRAM_ADDR[1]
set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+
+#============================================================
+# SRAM
+#============================================================
set_location_assignment PIN_AG3 -to SRAM_DQ[15]
set_location_assignment PIN_AF3 -to SRAM_DQ[14]
set_location_assignment PIN_AE4 -to SRAM_DQ[13]
@@ -730,47 +456,10 @@ set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N
+
+#============================================================
+# Flash
+#============================================================
set_location_assignment PIN_AF12 -to FL_DQ[7]
set_location_assignment PIN_AH11 -to FL_DQ[6]
set_location_assignment PIN_AG11 -to FL_DQ[5]
@@ -808,43 +497,10 @@ set_location_assignment PIN_AC10 -to FL_WE_N
set_location_assignment PIN_AE11 -to FL_RESET_N
set_location_assignment PIN_AE12 -to FL_WP_N
set_location_assignment PIN_Y1 -to FL_RY
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RESET_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+
+#============================================================
+# GPIO, GPIO connect to GPIO Default
+#============================================================
set_location_assignment PIN_AB22 -to GPIO[0]
set_location_assignment PIN_AC15 -to GPIO[1]
set_location_assignment PIN_AB21 -to GPIO[2]
@@ -881,42 +537,10 @@ set_location_assignment PIN_AF20 -to GPIO[32]
set_location_assignment PIN_AH26 -to GPIO[33]
set_location_assignment PIN_AH23 -to GPIO[34]
set_location_assignment PIN_AG26 -to GPIO[35]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
+
+#============================================================
+# HSMC, HSMC connect to HSMC Default
+#============================================================
set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
@@ -999,35 +623,10 @@ set_location_assignment PIN_AE28 -to HSMC_D[1]
set_location_assignment PIN_AE27 -to HSMC_D[2]
set_location_assignment PIN_AF27 -to HSMC_D[3]
set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2
+
+#============================================================
+# HSMC, HSMC connect to HSMC Default
+#============================================================
set_location_assignment PIN_J10 -to EXT_IO[0]
set_location_assignment PIN_J14 -to EXT_IO[1]
set_location_assignment PIN_H13 -to EXT_IO[2]
@@ -1035,92 +634,62 @@ set_location_assignment PIN_H14 -to EXT_IO[3]
set_location_assignment PIN_F14 -to EXT_IO[4]
set_location_assignment PIN_E10 -to EXT_IO[5]
set_location_assignment PIN_D9 -to EXT_IO[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[1]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[0]
+
+#============================================================
+# End of pin assignments by Altera University Program
+#============================================================
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS64
+
+
+
+
+
+
+
+
+
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to *
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to *
set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to *
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name SOURCE_FILE DE2_115.qsf
+set_global_assignment -name VERILOG_FILE avconf/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE avconf/avconf.v
+set_global_assignment -name VERILOG_FILE Audio_Controller/Audio_Controller.v
+set_global_assignment -name VERILOG_FILE Audio_Controller/Audio_Clock.v
+set_global_assignment -name VERILOG_FILE Audio_Controller/Altera_UP_SYNC_FIFO.v
+set_global_assignment -name VERILOG_FILE Audio_Controller/Altera_UP_Clock_Edge.v
+set_global_assignment -name VERILOG_FILE Audio_Controller/Altera_UP_Audio_Out_Serializer.v
+set_global_assignment -name VERILOG_FILE Audio_Controller/Altera_UP_Audio_In_Deserializer.v
+set_global_assignment -name VERILOG_FILE Audio_Controller/Altera_UP_Audio_Bit_Counter.v
set_global_assignment -name QIP_FILE otogame/synthesis/otogame.qip
-set_global_assignment -name SDC_FILE timing.sdc
-set_global_assignment -name SYSTEMVERILOG_FILE hexdriver.sv
-set_global_assignment -name SYSTEMVERILOG_FILE input/ps2kb.sv
-set_global_assignment -name SYSTEMVERILOG_FILE osu_fpga_toplevel.sv
+set_global_assignment -name SYSTEMVERILOG_FILE audio_test_top.sv
+set_global_assignment -name SYSTEMVERILOG_FILE audio.sv
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/otogame.qsys b/otogame.qsys
index 32161491af34c542d168b3ade4540f48eb6b7143..57a463a207eadb0127f13ead4c8e89c06927fa27 100644
--- a/otogame.qsys
+++ b/otogame.qsys
@@ -9,6 +9,22 @@
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
+ element audio_0
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ }
+ element audio_0.Audio_Slave
+ {
+ datum baseAddress
+ {
+ value = "268439632";
+ type = "String";
+ }
+ }
element clk_50
{
datum _sortIndex
@@ -53,7 +69,7 @@
{
datum baseAddress
{
- value = "8336";
+ value = "268439696";
type = "String";
}
}
@@ -89,6 +105,14 @@
type = "int";
}
}
+ element ocm_null.s1
+ {
+ datum baseAddress
+ {
+ value = "268439648";
+ type = "String";
+ }
+ }
element osu_sysid
{
datum _sortIndex
@@ -101,7 +125,7 @@
{
datum baseAddress
{
- value = "8328";
+ value = "268439688";
type = "String";
}
}
@@ -141,7 +165,7 @@
{
datum baseAddress
{
- value = "6144";
+ value = "268437504";
type = "String";
}
}
@@ -157,7 +181,7 @@
{
datum baseAddress
{
- value = "268435456";
+ value = "134217728";
type = "String";
}
}
@@ -173,7 +197,7 @@
{
datum baseAddress
{
- value = "48";
+ value = "268439664";
type = "String";
}
}
@@ -194,16 +218,16 @@
{
datum baseAddress
{
- value = "64";
+ value = "268439552";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="EP4CE115F29C7" />
+ <parameter name="device" value="EP4CE115F29C8" />
<parameter name="deviceFamily" value="Cyclone IV E" />
- <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="deviceSpeedGrade" value="8" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -219,16 +243,18 @@
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
+ <interface name="audio" internal="audio_0.EXPORT_DATA" type="conduit" dir="end" />
<interface name="clk" internal="clk_50.clk_in" type="clock" dir="end" />
- <interface name="ps2_clk" internal="keyboard.ps2_clk" type="conduit" dir="end" />
+ <interface name="ps2_clk" internal="keyboard.ps2_clk" />
<interface name="ps2_clock_conn" internal="keyboard.ps2_clock_conn" />
<interface name="ps2_conn" internal="keyboard.ps2_export" />
- <interface name="ps2_data" internal="keyboard.ps2_data" type="conduit" dir="end" />
+ <interface name="ps2_data" internal="keyboard.ps2_data" />
<interface name="ps2_data_conn" internal="keyboard.ps2_data_conn" />
<interface name="reset" internal="clk_50.clk_in_reset" type="reset" dir="end" />
<interface name="sdram_clk" internal="sdram_pll.c1" type="clock" dir="start" />
<interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
- <module name="clk_50" kind="clock_source" version="17.0" enabled="1">
+ <module name="audio_0" kind="audio" version="1.0" enabled="1" />
+ <module name="clk_50" kind="clock_source" version="17.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
@@ -237,7 +263,7 @@
<module
name="flash"
kind="Altera_UP_Flash_Memory_IP_Core_Avalon_Interface"
- version="17.0"
+ version="17.1"
enabled="0">
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
@@ -246,7 +272,7 @@
<module
name="jtag_uart"
kind="altera_avalon_jtag_uart"
- version="17.0"
+ version="17.1"
enabled="1">
<parameter name="allowMultipleConnections" value="false" />
<parameter name="avalonSpec" value="2.0" />
@@ -262,11 +288,11 @@
<parameter name="writeBufferDepth" value="64" />
<parameter name="writeIRQThreshold" value="8" />
</module>
- <module name="keyboard" kind="ps2kb" version="1.0" enabled="1" />
+ <module name="keyboard" kind="ps2kb" version="1.0" enabled="0" />
<module
name="ocm_null"
kind="altera_avalon_onchip_memory2"
- version="17.0"
+ version="17.1"
enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_ocm_null</parameter>
@@ -298,7 +324,7 @@
<module
name="osu_sysid"
kind="altera_avalon_sysid_qsys"
- version="17.0"
+ version="17.1"
enabled="1">
<parameter name="id" value="1869837601" />
</module>
@@ -312,7 +338,7 @@
<parameter name="cpuReset" value="false" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
<parameter name="dataAddrWidth" value="29" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='sdram_pll.pll_slave' start='0x30' end='0x40' /><slave name='timer.s1' start='0x40' end='0x60' /><slave name='proc_main.jtag_debug_module' start='0x1800' end='0x2000' /><slave name='osu_sysid.control_slave' start='0x2088' end='0x2090' /><slave name='jtag_uart.avalon_jtag_slave' start='0x2090' end='0x2098' /><slave name='keyboard.key_events' start='0x5000' end='0x5010' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x8000000' end='0x10000000' /><slave name='proc_main.jtag_debug_module' start='0x10000800' end='0x10001000' /><slave name='timer.s1' start='0x10001000' end='0x10001020' /><slave name='audio_0.Audio_Slave' start='0x10001050' end='0x10001060' /><slave name='ocm_null.s1' start='0x10001060' end='0x10001070' /><slave name='sdram_pll.pll_slave' start='0x10001070' end='0x10001080' /><slave name='osu_sysid.control_slave' start='0x10001088' end='0x10001090' /><slave name='jtag_uart.avalon_jtag_slave' start='0x10001090' end='0x10001098' /></address-map>]]></parameter>
<parameter name="dcache_bursts" value="false" />
<parameter name="dcache_lineSize" value="32" />
<parameter name="dcache_numTCDM" value="0" />
@@ -339,7 +365,7 @@
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Tiny" />
<parameter name="instAddrWidth" value="29" />
- <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='sdram_pll.pll_slave' start='0x30' end='0x40' /><slave name='proc_main.jtag_debug_module' start='0x1800' end='0x2000' /><slave name='osu_sysid.control_slave' start='0x2088' end='0x2090' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x8000000' end='0x10000000' /><slave name='proc_main.jtag_debug_module' start='0x10000800' end='0x10001000' /><slave name='ocm_null.s1' start='0x10001060' end='0x10001070' /><slave name='sdram_pll.pll_slave' start='0x10001070' end='0x10001080' /><slave name='osu_sysid.control_slave' start='0x10001088' end='0x10001090' /></address-map>]]></parameter>
<parameter name="internalIrqMaskSystemInfo" value="3" />
<parameter name="manuallyAssignCpuID" value="true" />
<parameter name="mmu_TLBMissExcOffset" value="0" />
@@ -432,7 +458,7 @@
<module
name="sdram"
kind="altera_avalon_new_sdram_controller"
- version="17.0"
+ version="17.1"
enabled="1">
<parameter name="TAC" value="5.5" />
<parameter name="TMRD" value="3" />
@@ -458,7 +484,7 @@
<parameter name="registerDataIn" value="true" />
<parameter name="rowWidth" value="13" />
</module>
- <module name="sdram_pll" kind="altpll" version="17.0" enabled="1">
+ <module name="sdram_pll" kind="altpll" version="17.1" enabled="1">
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
<parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
@@ -625,7 +651,7 @@
<parameter name="WIDTH_CLOCK" value="5" />
<parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
</module>
- <module name="timer" kind="altera_avalon_timer" version="17.0" enabled="1">
+ <module name="timer" kind="altera_avalon_timer" version="17.1" enabled="1">
<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="fixedPeriod" value="false" />
@@ -639,25 +665,34 @@
</module>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
+ start="proc_main.data_master"
+ end="audio_0.Audio_Slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x10001050" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.1"
start="proc_main.data_master"
end="jtag_uart.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2090" />
+ <parameter name="baseAddress" value="0x10001090" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="osu_sysid.control_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2088" />
+ <parameter name="baseAddress" value="0x10001088" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="flash.flash_data">
<parameter name="arbitrationPriority" value="1" />
@@ -666,7 +701,7 @@
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="flash.flash_erase_control">
<parameter name="arbitrationPriority" value="1" />
@@ -675,16 +710,16 @@
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="proc_main.jtag_debug_module">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x1800" />
+ <parameter name="baseAddress" value="0x10000800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="keyboard.key_events">
<parameter name="arbitrationPriority" value="1" />
@@ -693,52 +728,52 @@
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="sdram_pll.pll_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0030" />
+ <parameter name="baseAddress" value="0x10001070" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="ocm_null.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
+ <parameter name="baseAddress" value="0x10001060" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="sdram.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x10000000" />
+ <parameter name="baseAddress" value="0x08000000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.data_master"
end="timer.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0040" />
+ <parameter name="baseAddress" value="0x10001000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
end="osu_sysid.control_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2088" />
+ <parameter name="baseAddress" value="0x10001088" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
end="flash.flash_data">
<parameter name="arbitrationPriority" value="1" />
@@ -747,110 +782,116 @@
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
end="proc_main.jtag_debug_module">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x1800" />
+ <parameter name="baseAddress" value="0x10000800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
end="sdram_pll.pll_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0030" />
+ <parameter name="baseAddress" value="0x10001070" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
end="ocm_null.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
+ <parameter name="baseAddress" value="0x10001060" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="17.0"
+ version="17.1"
start="proc_main.instruction_master"
end="sdram.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x10000000" />
+ <parameter name="baseAddress" value="0x08000000" />
<parameter name="defaultConnection" value="false" />
</connection>
- <connection kind="clock" version="17.0" start="sdram_pll.c0" end="sdram.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="osu_sysid.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="proc_main.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="jtag_uart.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="timer.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="flash.clk" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="ocm_null.clk1" />
- <connection kind="clock" version="17.0" start="clk_50.clk" end="keyboard.clock" />
+ <connection kind="clock" version="17.1" start="sdram_pll.c0" end="sdram.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="audio_0.CLK" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="osu_sysid.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="proc_main.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="jtag_uart.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="timer.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="flash.clk" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="ocm_null.clk1" />
+ <connection kind="clock" version="17.1" start="clk_50.clk" end="keyboard.clock" />
<connection
kind="clock"
- version="17.0"
+ version="17.1"
start="clk_50.clk"
end="sdram_pll.inclk_interface" />
<connection
kind="interrupt"
- version="17.0"
+ version="17.1"
start="proc_main.d_irq"
end="jtag_uart.irq">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
- version="17.0"
+ version="17.1"
start="proc_main.d_irq"
end="timer.irq">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="reset"
- version="17.0"
+ version="17.1"
+ start="clk_50.clk_reset"
+ end="audio_0.RESET" />
+ <connection
+ kind="reset"
+ version="17.1"
start="clk_50.clk_reset"
end="sdram_pll.inclk_interface_reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="sdram.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="osu_sysid.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="jtag_uart.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="timer.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="flash.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="keyboard.reset" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="ocm_null.reset1" />
<connection
kind="reset"
- version="17.0"
+ version="17.1"
start="clk_50.clk_reset"
end="proc_main.reset_n" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
diff --git a/software/oto_audio/.cproject b/software/oto_audio/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..8fc3079f0937f96b139b3fabad671ffe16d391e9
--- /dev/null
+++ b/software/oto_audio/.cproject
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850">
+ <storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850" moduleId="org.eclipse.cdt.core.settings"/>
+ </buildSystem>
+ <cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850">
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850." name="/" resourcePath="">
+ <toolChain id="altera.nios2.mingw.gcc4.522164900" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
+ <targetPlatform id="altera.nios2.mingw.gcc4.1772983844" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
+ <builder buildPath="${workspace_loc://oto_audio}" id="altera.tool.gnu.builder.mingw.2056654465" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
+ <tool id="altera.tool.gnu.c.compiler.mingw.1013930879" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1715282552" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ </tool>
+ <tool id="altera.tool.gnu.cpp.compiler.mingw.56088267" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.833570515" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+ </tool>
+ <tool id="altera.tool.gnu.archiver.mingw.181735596" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
+ <tool id="altera.tool.gnu.c.linker.mingw.406940735" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
+ <tool id="altera.tool.gnu.assembler.mingw.1802949496" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.17920711" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="oto_audio.null.177029163" name="oto_audio"/>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850.;altera.tool.gnu.cpp.compiler.mingw.56088267;cdt.managedbuild.tool.gnu.cpp.compiler.input.833570515">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1940785850.;altera.tool.gnu.c.compiler.mingw.1013930879;cdt.managedbuild.tool.gnu.c.compiler.input.1715282552">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
+ <buildTargets>
+ <target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>mem_init_install</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>false</useDefaultCommand>
+ <runAllBuilders>false</runAllBuilders>
+ </target>
+ <target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>mem_init_generate</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>false</useDefaultCommand>
+ <runAllBuilders>false</runAllBuilders>
+ </target>
+ <target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>help</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>false</useDefaultCommand>
+ <runAllBuilders>false</runAllBuilders>
+ </target>
+ </buildTargets>
+ </storageModule>
+</cproject>
diff --git a/software/oto_audio/.project b/software/oto_audio/.project
new file mode 100644
index 0000000000000000000000000000000000000000..aad0157b55a3822bac26c355f23349f6f88d9300
--- /dev/null
+++ b/software/oto_audio/.project
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>oto_audio</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>com.altera.sbtgui.project.makefileBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>com.altera.sbtgui.project.makefileBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>com.altera.sbtgui.project.SBTGUINature</nature>
+ <nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
+ <nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
+ </natures>
+</projectDescription>
diff --git a/software/oto_audio/Makefile b/software/oto_audio/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f9f77f4222861356aece398ef2fe9f214208d930
--- /dev/null
+++ b/software/oto_audio/Makefile
@@ -0,0 +1,1082 @@
+#------------------------------------------------------------------------------
+# VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS
+#------------------------------------------------------------------------------
+
+# List of include directories for -I compiler option (-I added when used).
+# Includes the BSP.
+ALT_INCLUDE_DIRS :=
+
+# List of library directories for -L linker option (-L added when used).
+# Includes the BSP.
+ALT_LIBRARY_DIRS :=
+
+# List of library names for -l linker option (-l added when used).
+# Includes the BSP.
+ALT_LIBRARY_NAMES :=
+
+# List of library names for -msys-lib linker option (-msys-lib added when used).
+# These are libraries that might be located in the BSP and depend on the BSP
+# library, or vice versa
+ALT_BSP_DEP_LIBRARY_NAMES :=
+
+# List of dependencies for the linker. This is usually the full pathname
+# of each library (*.a) file.
+# Includes the BSP.
+ALT_LDDEPS :=
+
+# List of root library directories that support running make to build them.
+# Includes the BSP and any ALT libraries.
+MAKEABLE_LIBRARY_ROOT_DIRS :=
+
+# Generic flags passed to the compiler for different types of input files.
+ALT_CFLAGS :=
+ALT_CXXFLAGS :=
+ALT_CPPFLAGS :=
+ALT_ASFLAGS :=
+ALT_LDFLAGS :=
+
+
+#------------------------------------------------------------------------------
+# The adjust-path macro
+#
+# If COMSPEC/ComSpec is defined, Make is launched from Windows through
+# Cygwin. The adjust-path macro converts absolute windows paths into
+# unix style paths (Example: c:/dir -> /c/dir). This will ensture
+# paths are readable by GNU Make.
+#
+# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no
+# adjustment is necessary
+#
+#------------------------------------------------------------------------------
+
+ifndef COMSPEC
+ifdef ComSpec
+COMSPEC = $(ComSpec)
+endif # ComSpec
+endif # COMSPEC
+
+ifdef COMSPEC # if Windows OS
+
+ifeq ($(MAKE_VERSION),3.81)
+#
+# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows
+#
+# Example Usage:
+# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb
+# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb
+# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb
+#
+
+#
+# adjust-path
+# - converts back slash characters into forward slashes
+# - if input arg ($1) is an empty string then return the empty string
+# - if input arg ($1) does not contain the string ":/", then return input arg
+# - using sed, convert mixed path [c:/...] into mingw path [/c/...]
+define adjust-path
+$(strip \
+$(if $1,\
+$(if $(findstring :/,$(subst \,/,$1)),\
+$(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\
+$(subst \,/,$1))))
+endef
+
+#
+# adjust-path-mixed
+# - converts back slash characters into forward slashes
+# - if input arg ($1) is an empty string then return the empty string
+# - if input arg ($1) does not begin with a forward slash '/' char, then
+# return input arg
+# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...]
+# into a mixed path [c:/...]
+define adjust-path-mixed
+$(strip \
+$(if $1,\
+$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\
+$(subst \,/,$1),\
+$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,'))))
+endef
+
+else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79)
+#
+# adjust-path for Cygwin Gnu Make
+# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb
+# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb
+#
+adjust-path = $(if $1,$(shell cygpath -u "$1"),)
+adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),)
+endif
+
+else # !COMSPEC
+
+adjust-path = $1
+adjust-path-mixed = $1
+
+endif # COMSPEC
+
+
+#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
+# GENERATED SETTINGS START v
+#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
+
+#START GENERATED
+ACTIVE_BUILD_CONFIG := default
+BUILD_CONFIGS := default
+
+# The following TYPE comment allows tools to identify the 'type' of target this
+# makefile is associated with.
+# TYPE: APP_MAKEFILE
+
+# This following VERSION comment indicates the version of the tool used to
+# generate this makefile. A makefile variable is provided for VERSION as well.
+# ACDS_VERSION: 17.1
+ACDS_VERSION := 17.1
+
+# This following BUILD_NUMBER comment indicates the build number of the tool
+# used to generate this makefile.
+# BUILD_NUMBER: 590
+
+# Define path to the application ELF.
+# It may be used by the makefile fragments so is defined before including them.
+#
+ELF := oto_audio.elf
+
+# Paths to C, C++, and assembly source files.
+C_SRCS := main.c
+CXX_SRCS :=
+ASM_SRCS :=
+
+
+# Path to root of object file tree.
+OBJ_ROOT_DIR := obj
+
+# Options to control objdump.
+CREATE_OBJDUMP := 1
+OBJDUMP_INCLUDE_SOURCE := 1
+OBJDUMP_FULL_CONTENTS := 0
+
+# Options to enable/disable optional files.
+CREATE_ELF_DERIVED_FILES := 0
+CREATE_LINKER_MAP := 1
+
+# Common arguments for ALT_CFLAGSs
+APP_CFLAGS_DEFINED_SYMBOLS :=
+APP_CFLAGS_UNDEFINED_SYMBOLS :=
+APP_CFLAGS_OPTIMIZATION := -O0
+APP_CFLAGS_DEBUG_LEVEL := -g
+APP_CFLAGS_WARNINGS := -Wall
+APP_CFLAGS_USER_FLAGS :=
+
+APP_ASFLAGS_USER :=
+APP_LDFLAGS_USER :=
+
+# Linker options that have default values assigned later if not
+# assigned here.
+LINKER_SCRIPT :=
+CRT0 :=
+SYS_LIB :=
+
+# Define path to the root of the BSP.
+BSP_ROOT_DIR := ../oto_audio_bsp/
+
+# List of application specific include directories, library directories and library names
+APP_INCLUDE_DIRS :=
+APP_LIBRARY_DIRS :=
+APP_LIBRARY_NAMES :=
+
+# Pre- and post- processor settings.
+BUILD_PRE_PROCESS :=
+BUILD_POST_PROCESS :=
+
+QUARTUS_PROJECT_DIR := ../../
+
+
+#END GENERATED
+
+#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+# GENERATED SETTINGS END ^
+#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+
+#------------------------------------------------------------------------------
+# DEFAULT TARGET
+#------------------------------------------------------------------------------
+
+# Define the variable used to echo output if not already defined.
+ifeq ($(ECHO),)
+ECHO := echo
+endif
+
+# Put "all" rule before included makefile fragments because they may
+# define rules and we don't want one of those to become the default rule.
+.PHONY : all
+
+all:
+ @$(ECHO) [$(APP_NAME) build complete]
+
+all : build_pre_process libs app build_post_process
+
+
+#------------------------------------------------------------------------------
+# VARIABLES DEPENDENT ON GENERATED CONTENT
+#------------------------------------------------------------------------------
+
+# Define object file directory per build configuration
+CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG)
+
+ifeq ($(BSP_ROOT_DIR),)
+$(error Edit Makefile and provide a value for BSP_ROOT_DIR)
+endif
+
+ifeq ($(wildcard $(BSP_ROOT_DIR)),)
+$(error BSP directory does not exist: $(BSP_ROOT_DIR))
+endif
+
+# Define absolute path to the root of the BSP.
+ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd))
+
+# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before
+# including each makefile fragment so that it knows the path to itself.
+BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk
+ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR)
+include $(BSP_INCLUDE_FILE)
+# C2H will need this to touch the BSP public.mk and avoid the sopc file
+# out-of-date error during a BSP make
+ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk
+
+
+ifneq ($(WARNING.SMALL_STACK_SIZE),)
+# This WARNING is here to protect you from unknowingly using a very small stack
+# If the warning is set, increase your stack size or enable the BSP small stack
+# setting to eliminate the warning
+$(warning WARNING: $(WARNING.SMALL_STACK_SIZE))
+endif
+
+# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF
+# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_.
+ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),)
+ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF)
+endif
+
+# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to
+# download_elf target
+ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),)
+GMON_OUT_FILENAME := gmon.out
+WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME)
+endif
+
+# Name of ELF application.
+APP_NAME := $(basename $(ELF))
+
+# Set to defaults if variables not already defined in settings.
+ifeq ($(LINKER_SCRIPT),)
+LINKER_SCRIPT := $(BSP_LINKER_SCRIPT)
+endif
+ifeq ($(CRT0),)
+CRT0 := $(BSP_CRT0)
+endif
+ifeq ($(SYS_LIB),)
+SYS_LIB := $(BSP_SYS_LIB)
+endif
+
+OBJDUMP_NAME := $(APP_NAME).objdump
+OBJDUMP_FLAGS := --disassemble --syms --all-header
+ifeq ($(OBJDUMP_INCLUDE_SOURCE),1)
+OBJDUMP_FLAGS += --source
+endif
+ifeq ($(OBJDUMP_FULL_CONTENTS),1)
+OBJDUMP_FLAGS += --full-contents
+endif
+
+# Create list of linker dependencies (*.a files).
+APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS)
+
+# Take lists and add required prefixes.
+APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
+ASM_INC_PREFIX := -Wa,-I
+APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
+APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS))
+APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS))
+
+ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
+
+#
+# Avoid Nios II GCC 3.X options.
+#
+
+# Detect if small newlib C library is requested.
+# If yes, remove the -msmallc option because it is
+# now handled by other means.
+ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),)
+ ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS))
+ ALT_C_LIBRARY := smallc
+else
+ ALT_C_LIBRARY := c
+endif
+
+# Put each BSP dependent library in a group to avoid circular dependencies.
+APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -lm -l$(l) -Wl,--end-group)
+
+else # !AVOID_NIOS2_GCC3_OPTIONS
+
+#
+# Use Nios II GCC 3.X options.
+#
+ALT_BSP_DEP_LIBRARY_NAMES += $(ALT_BSP_DEP_LIBRARY_NAMES) m
+APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES))
+
+endif # !AVOID_NIOS2_GCC3_OPTIONS
+
+# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker.
+APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \
+ $(APP_CFLAGS_UNDEFINED_SYMBOLS) \
+ $(APP_CFLAGS_OPTIMIZATION) \
+ $(APP_CFLAGS_DEBUG_LEVEL) \
+ $(APP_CFLAGS_WARNINGS) \
+ $(APP_CFLAGS_USER_FLAGS) \
+ $(ALT_CFLAGS) \
+ $(CFLAGS)
+
+# Arguments only for the C++ compiler.
+APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS)
+
+# Arguments only for the C preprocessor.
+# Prefix each include directory with -I.
+APP_CPPFLAGS := $(APP_INC_DIRS) \
+ $(ALT_CPPFLAGS) \
+ $(CPPFLAGS)
+
+# Arguments only for the assembler.
+APP_ASFLAGS := $(APP_ASM_INC_DIRS) \
+ $(ALT_ASFLAGS) \
+ $(APP_ASFLAGS_USER) \
+ $(ASFLAGS)
+
+# Arguments only for the linker.
+APP_LDFLAGS := $(APP_LDFLAGS_USER)
+
+ifneq ($(LINKER_SCRIPT),)
+APP_LDFLAGS += -T'$(LINKER_SCRIPT)'
+endif
+
+ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
+
+# Avoid Nios II GCC 3.x options.
+ifneq ($(CRT0),)
+APP_LDFLAGS += $(CRT0)
+endif
+
+# The equivalent of the -msys-lib option is provided
+# by the GROUP() command in the linker script.
+# Note this means the SYS_LIB variable is now ignored.
+
+else # !AVOID_NIOS2_GCC3_OPTIONS
+
+# Use Nios II GCC 3.x options.
+ifneq ($(CRT0),)
+APP_LDFLAGS += -msys-crt0='$(CRT0)'
+endif
+ifneq ($(SYS_LIB),)
+APP_LDFLAGS += -msys-lib=$(SYS_LIB)
+endif
+
+endif # !AVOID_NIOS2_GCC3_OPTIONS
+
+APP_LDFLAGS += \
+ $(APP_LIB_DIRS) \
+ $(ALT_LDFLAGS) \
+ $(LDFLAGS)
+
+LINKER_MAP_NAME := $(APP_NAME).map
+ifeq ($(CREATE_LINKER_MAP), 1)
+APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME)
+endif
+
+# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the
+# mem_init_install target of the mem_init.mk (located in the associated BSP)
+# to know how to copy memory initialization files (e.g. .dat, .hex) into
+# directories required for Quartus compilation or RTL simulation.
+
+# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory
+# initialization files into your Quartus project directory. This is required
+# to provide the initial memory contents of FPGA memories that can be
+# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used
+# for VHDL simulation of on-chip memories.
+
+# Defining SOPC_NAME causes the mem_init_install target to copy memory
+# initialization files into your RTL simulation directory. This is required
+# to provide the initial memory contents of all memories that can be
+# initialized by RTL simulation. This variable should be set to the same name
+# as your SOPC Builder system name. For example, if you have a system called
+# "foo.sopc", this variable should be set to "foo".
+
+# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME.
+ifeq ($(SOPC_NAME),)
+ifneq ($(QUARTUS_PROJECT_DIR),)
+SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo)))
+endif
+endif
+
+# Defining JDI_FILE is required to specify the JTAG Debug Information File
+# path. This file is generated by Quartus, and is needed along with the
+# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU
+# systems. For multi-CPU systems, the processor instance ID is used to select
+# from multiple CPU's during ELF download.
+
+# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during
+# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then
+# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be
+# multiple .sopcinfo files in a Quartus project.
+ifeq ($(JDI_FILE),)
+ifneq ($(QUARTUS_PROJECT_DIR),)
+JDI_FILE := $(firstword $(wildcard $(QUARTUS_PROJECT_DIR)/output_files/*.jdi) $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi))
+endif
+endif
+
+# Path to root runtime directory used for hdl simulation
+RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime
+
+
+
+#------------------------------------------------------------------------------
+# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT
+#------------------------------------------------------------------------------
+# mem_init.mk is a generated makefile fragment. This file defines all targets
+# used to generate HDL initialization simulation files and pre-initialized
+# onchip memory files.
+MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk
+include $(MEM_INIT_FILE)
+
+# Create list of object files to be built using the list of source files.
+# The source file hierarchy is preserved in the object tree.
+# The supported file extensions are:
+#
+# .c - for C files
+# .cxx .cc .cpp - for C++ files
+# .S .s - for assembler files
+#
+# Handle source files specified by --src-dir & --src-rdir differently, to
+# save some processing time in calling the adjust-path macro.
+
+OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS)))
+OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS)))
+OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS)))
+OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS)))
+OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS)))
+OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS)))
+
+OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \
+ $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS))
+
+SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS)))
+SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS)))
+SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS)))
+
+SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \
+ $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \
+ $(SDIR_OBJ_LIST_SS))
+
+# Relative-pathed objects that being with "../" are handled differently.
+#
+# Regular objects are created as
+# $(CONFIG_OBJ_DIR)/<path>/<filename>.o
+# where the path structure is maintained under the obj directory. This
+# applies for both absolute and relative paths; in the absolute path
+# case this means the entire source path will be recreated under the obj
+# directory. This is done to allow two source files with the same name
+# to be included as part of the project.
+#
+# Note: On Cygwin, the path recreated under the obj directory will be
+# the cygpath -u output path.
+#
+# Relative-path objects that begin with "../" cause problems under this
+# scheme, as $(CONFIG_OBJ_DIR)/../<rest of path>/ can potentially put the object
+# files anywhere in the system, creating clutter and polluting the source tree.
+# As such, their paths are flattened - the object file created will be
+# $(CONFIG_OBJ_DIR)/<filename>.o. Due to this, two files specified with
+# "../" in the beginning cannot have the same name in the project. VPATH
+# will be set for these sources to allow make to relocate the source file
+# via %.o rules.
+#
+# The following lines separate the object list into the flatten and regular
+# lists, and then handles them as appropriate.
+
+FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST))
+FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST)))
+
+REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST))
+REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST))
+
+FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST))
+FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST)))
+
+REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST))
+
+VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST)))
+
+APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_C) \
+ $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s)))
+
+APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_CPP) \
+ $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s)))
+
+APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_CXX) \
+ $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s)))
+
+APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_CC) \
+ $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s)))
+
+APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_S) \
+ $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s)))
+
+APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_SS) \
+ $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s)))
+
+APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \
+ $(APP_OBJS_S) $(APP_OBJS_SS) \
+ $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS)
+
+# Add any extra user-provided object files.
+APP_OBJS += $(OBJS)
+
+# Create list of dependancy files for each object file.
+APP_DEPS := $(APP_OBJS:.o=.d)
+
+# Patch the Elf file with system specific information
+
+# Patch the Elf with the name of the sopc system
+ifneq ($(SOPC_NAME),)
+ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME)
+endif
+
+# Patch the Elf with the absolute path to the Quartus Project Directory
+ifneq ($(QUARTUS_PROJECT_DIR),)
+ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd))
+ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)"
+endif
+
+# Patch the Elf and download args with the JDI_FILE if specified
+ifneq ($(wildcard $(JDI_FILE)),)
+ELF_PATCH_FLAG += --jdi $(JDI_FILE)
+DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE)
+endif
+
+# Patch the Elf with the SOPCINFO_FILE if specified
+ifneq ($(wildcard $(SOPCINFO_FILE)),)
+ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE)
+endif
+
+# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use.
+# This is not needed if you only have one cable.
+ifneq ($(DOWNLOAD_CABLE),)
+DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)'
+endif
+
+
+#------------------------------------------------------------------------------
+# BUILD PRE/POST PROCESS
+#------------------------------------------------------------------------------
+build_pre_process :
+ $(BUILD_PRE_PROCESS)
+
+build_post_process :
+ $(BUILD_POST_PROCESS)
+
+.PHONY: build_pre_process build_post_process
+
+
+#------------------------------------------------------------------------------
+# TOOLS
+#------------------------------------------------------------------------------
+
+#
+# Set tool default variables if not already defined.
+# If these are defined, they would typically be defined in an
+# included makefile fragment.
+#
+ifeq ($(DEFAULT_CROSS_COMPILE),)
+DEFAULT_CROSS_COMPILE := nios2-elf-
+endif
+
+ifeq ($(DEFAULT_STACKREPORT),)
+DEFAULT_STACKREPORT := nios2-stackreport
+endif
+
+ifeq ($(DEFAULT_DOWNLOAD),)
+DEFAULT_DOWNLOAD := nios2-download
+endif
+
+ifeq ($(DEFAULT_FLASHPROG),)
+DEFAULT_FLASHPROG := nios2-flash-programmer
+endif
+
+ifeq ($(DEFAULT_ELFPATCH),)
+DEFAULT_ELFPATCH := nios2-elf-insert
+endif
+
+ifeq ($(DEFAULT_RM),)
+DEFAULT_RM := rm -f
+endif
+
+ifeq ($(DEFAULT_CP),)
+DEFAULT_CP := cp -f
+endif
+
+ifeq ($(DEFAULT_MKDIR),)
+DEFAULT_MKDIR := mkdir -p
+endif
+
+#
+# Set tool variables to defaults if not already defined.
+# If these are defined, they would typically be defined by a
+# setting in the generated portion of this makefile.
+#
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE)
+endif
+
+ifeq ($(origin CC),default)
+CC := $(CROSS_COMPILE)gcc -xc
+endif
+
+ifeq ($(origin CXX),default)
+CXX := $(CROSS_COMPILE)gcc -xc++
+endif
+
+ifeq ($(origin AS),default)
+AS := $(CROSS_COMPILE)gcc
+endif
+
+ifeq ($(origin AR),default)
+AR := $(CROSS_COMPILE)ar
+endif
+
+ifeq ($(origin LD),default)
+LD := $(CROSS_COMPILE)g++
+endif
+
+ifeq ($(origin RM),default)
+RM := $(DEFAULT_RM)
+endif
+
+ifeq ($(NM),)
+NM := $(CROSS_COMPILE)nm
+endif
+
+ifeq ($(CP),)
+CP := $(DEFAULT_CP)
+endif
+
+ifeq ($(OBJDUMP),)
+OBJDUMP := $(CROSS_COMPILE)objdump
+endif
+
+ifeq ($(OBJCOPY),)
+OBJCOPY := $(CROSS_COMPILE)objcopy
+endif
+
+ifeq ($(STACKREPORT),)
+STACKREPORT := $(DEFAULT_STACKREPORT) --prefix $(CROSS_COMPILE)
+else
+DISABLE_STACKREPORT := 1
+endif
+
+ifeq ($(DOWNLOAD),)
+DOWNLOAD := $(DEFAULT_DOWNLOAD)
+endif
+
+ifeq ($(FLASHPROG),)
+FLASHPROG := $(DEFAULT_FLASHPROG)
+endif
+
+ifeq ($(ELFPATCH),)
+ELFPATCH := $(DEFAULT_ELFPATCH)
+endif
+
+ifeq ($(MKDIR),)
+MKDIR := $(DEFAULT_MKDIR)
+endif
+
+#------------------------------------------------------------------------------
+# PATTERN RULES TO BUILD OBJECTS
+#------------------------------------------------------------------------------
+
+define compile.c
+@$(ECHO) Info: Compiling $< to $@
+@$(MKDIR) $(@D)
+$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+$(CC_POST_PROCESS)
+endef
+
+define compile.cpp
+@$(ECHO) Info: Compiling $< to $@
+@$(MKDIR) $(@D)
+$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+$(CXX_POST_PROCESS)
+endef
+
+# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS
+ifeq ($(AS),$(patsubst %as,%,$(AS)))
+COMMA := ,
+APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS))))
+endif
+
+define compile.s
+@$(ECHO) Info: Assembling $< to $@
+@$(MKDIR) $(@D)
+$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $<
+$(AS_POST_PROCESS)
+endef
+
+ifeq ($(MAKE_VERSION),3.81)
+.SECONDEXPANSION:
+
+$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c)
+ $(compile.c)
+
+$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp)
+ $(compile.cpp)
+
+$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc)
+ $(compile.cpp)
+
+$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx)
+ $(compile.cpp)
+
+$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S)
+ $(compile.s)
+
+$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s)
+ $(compile.s)
+
+endif # MAKE_VERSION != 3.81
+
+$(CONFIG_OBJ_DIR)/%.o: %.c
+ $(compile.c)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cpp
+ $(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cc
+ $(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cxx
+ $(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.S
+ $(compile.s)
+
+$(CONFIG_OBJ_DIR)/%.o: %.s
+ $(compile.s)
+
+
+#------------------------------------------------------------------------------
+# PATTERN RULES TO INTERMEDIATE FILES
+#------------------------------------------------------------------------------
+
+$(CONFIG_OBJ_DIR)/%.s: %.c
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cpp
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cc
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cxx
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.c
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cpp
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cc
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cxx
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+
+#------------------------------------------------------------------------------
+# TARGET RULES
+#------------------------------------------------------------------------------
+
+.PHONY : help
+help :
+ @$(ECHO) "Summary of Makefile targets"
+ @$(ECHO) " Build targets:"
+ @$(ECHO) " all (default) - Application and all libraries (including BSP)"
+ @$(ECHO) " bsp - Just the BSP"
+ @$(ECHO) " libs - All libraries (including BSP)"
+ @$(ECHO) " flash - All flash files"
+ @$(ECHO) " mem_init_generate - All memory initialization files"
+ @$(ECHO)
+ @$(ECHO) " Clean targets:"
+ @$(ECHO) " clean_all - Application and all libraries (including BSP)"
+ @$(ECHO) " clean - Just the application"
+ @$(ECHO) " clean_bsp - Just the BSP"
+ @$(ECHO) " clean_libs - All libraries (including BSP)"
+ @$(ECHO)
+ @$(ECHO) " Run targets:"
+ @$(ECHO) " download-elf - Download and run your elf executable"
+ @$(ECHO) " program-flash - Program flash contents to the board"
+
+# Handy rule to skip making libraries and just make application.
+.PHONY : app
+app : $(ELF)
+
+ifeq ($(CREATE_OBJDUMP), 1)
+app : $(OBJDUMP_NAME)
+endif
+
+ifeq ($(CREATE_ELF_DERIVED_FILES),1)
+app : elf_derived_files
+endif
+
+.PHONY: elf_derived_files
+elf_derived_files: default_mem_init
+
+# Handy rule for making just the BSP.
+.PHONY : bsp
+bsp :
+ @$(ECHO) Info: Building $(BSP_ROOT_DIR)
+ @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR)
+
+
+# Make sure all makeable libraries (including the BSP) are up-to-date.
+LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
+
+.PHONY : libs
+libs : $(LIB_TARGETS)
+
+ifneq ($(strip $(LIB_TARGETS)),)
+$(LIB_TARGETS): %-recurs-make-lib:
+ @$(ECHO) Info: Building $*
+ $(MAKE) --no-print-directory -C $*
+endif
+
+ifneq ($(strip $(APP_LDDEPS)),)
+$(APP_LDDEPS): libs
+ @true
+endif
+
+# Rules to force your project to rebuild or relink
+# .force_relink file will cause any application that depends on this project to relink
+# .force_rebuild file will cause this project to rebuild object files
+# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files
+
+FORCE_RELINK_DEP := .force_relink
+FORCE_REBUILD_DEP := .force_rebuild
+FORCE_REBUILD_ALL_DEP := .force_rebuild_all
+FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP)
+
+$(FORCE_REBUILD_DEP_LIST):
+
+$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS)))
+
+$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS)))
+
+
+# Clean just the application.
+.PHONY : clean
+ifeq ($(CREATE_ELF_DERIVED_FILES),1)
+clean : clean_elf_derived_files
+endif
+
+clean :
+ @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST)
+ @$(ECHO) [$(APP_NAME) clean complete]
+
+# Clean just the BSP.
+.PHONY : clean_bsp
+clean_bsp :
+ @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR)
+ @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean
+
+# Clean all makeable libraries including the BSP.
+LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
+
+.PHONY : clean_libs
+clean_libs : $(LIB_CLEAN_TARGETS)
+
+ifneq ($(strip $(LIB_CLEAN_TARGETS)),)
+$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib:
+ @$(ECHO) Info: Cleaning $*
+ $(MAKE) --no-print-directory -C $* clean
+endif
+
+.PHONY: clean_elf_derived_files
+clean_elf_derived_files: mem_init_clean
+
+# Clean application and all makeable libraries including the BSP.
+.PHONY : clean_all
+clean_all : clean mem_init_clean clean_libs
+
+# Include the dependency files unless the make goal is performing a clean
+# of the application.
+ifneq ($(firstword $(MAKECMDGOALS)),clean)
+ifneq ($(firstword $(MAKECMDGOALS)),clean_all)
+-include $(APP_DEPS)
+endif
+endif
+
+.PHONY : download-elf
+download-elf : $(ELF)
+ @if [ "$(DOWNLOAD)" = "none" ]; \
+ then \
+ $(ECHO) Downloading $(ELF) not supported; \
+ else \
+ $(ECHO) Info: Downloading $(ELF); \
+ $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \
+ fi
+
+# Delete the target of a rule if it has changed and its commands exit
+# with a nonzero exit status.
+.DELETE_ON_ERROR:
+
+# Rules for flash programming commands
+PROGRAM_FLASH_SUFFIX := -program
+PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES))
+
+.PHONY : program-flash
+program-flash : $(PROGRAM_FLASH_TARGET)
+
+.PHONY : $(PROGRAM_FLASH_TARGET)
+$(PROGRAM_FLASH_TARGET) : flash
+ @if [ "$(FLASHPROG)" = "none" ]; \
+ then \
+ $(ECHO) Programming flash not supported; \
+ else \
+ $(ECHO) Info: Programming $(basename $@).flash; \
+ if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \
+ then \
+ $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
+ $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
+ else \
+ $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
+ $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
+ fi \
+ fi
+
+
+# Rules for simulating with an HDL Simulator [QSYS only]
+ifeq ($(QSYS),1)
+#Create a top level modelsim script load_sim.tcl to source generate msim_setup.tcl and copy mem initialization files
+CREATE_TOP_SIM_SCRIPT := alt-create-top-sim-script
+
+ifeq ($(VSIM),)
+VSIM_EXE := "$(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim"
+ifeq ($(ENABLE_VSIM_GUI),1)
+VSIM := $(VSIM_EXE) -gui
+else
+VSIM := $(VSIM_EXE) -c
+endif # ENABLE_VSIM_GUI == 1
+endif # VSIM not set
+
+ifeq ($(SPD),)
+ifneq ($(ABS_QUARTUS_PROJECT_DIR),)
+ifneq ($(SOPC_NAME),)
+SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb.spd
+LEGACY_SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd
+SPD = $(if $(wildcard $(SPD_LOCATION)),$(SPD_LOCATION),$(LEGACY_SPD_LOCATION))
+endif # SOPC_NAME set
+endif # ABS_QUARTUS_PROJECT_DIR set
+endif # SPD == empty string
+
+
+ifeq ($(LOAD_SIM_SCRIPT),)
+SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim
+LOAD_SIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/load_sim.tcl
+endif # LOAD_SIM_SCRIPT == empty string
+
+ifeq ($(MAKE_VERSION),3.81)
+ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE))
+else
+ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE)
+endif
+
+$(LOAD_SIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE)
+ifeq ($(SPD),)
+ $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set)
+endif
+ @$(MKDIR) $(SIM_SCRIPT_DIR)
+ $(CREATE_TOP_SIM_SCRIPT) --spd=$(SPD) --mem-init-spd=$(abspath $(MEM_INIT_DESCRIPTOR_FILE)) --output-directory=$(SIM_SCRIPT_DIR)
+
+VSIM_COMMAND = \
+ cd $(dir $(LOAD_SIM_SCRIPT)) && \
+ $(VSIM) -do "do $(notdir $(LOAD_SIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)"
+
+.PHONY: sim
+sim: $(LOAD_SIM_SCRIPT) mem_init_generate
+ifeq ($(LOAD_SIM_SCRIPT),)
+ $(error LOAD_SIM_SCRIPT not set)
+endif
+ $(VSIM_COMMAND)
+
+endif # QSYS == 1
+
+
+
+
+#------------------------------------------------------------------------------
+# ELF TARGET RULE
+#------------------------------------------------------------------------------
+# Rule for constructing the executable elf file.
+$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS)
+ @$(ECHO) Info: Linking $@
+ $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS)
+ifneq ($(DISABLE_ELFPATCH),1)
+ $(ELFPATCH) $@ $(ELF_PATCH_FLAG)
+endif
+ifneq ($(DISABLE_STACKREPORT),1)
+ @bash -c "$(STACKREPORT) $@"
+endif
+
+$(OBJDUMP_NAME) : $(ELF)
+ @$(ECHO) Info: Creating $@
+ $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@
+
+# Rule for printing the name of the elf file
+.PHONY: print-elf-name
+print-elf-name:
+ @$(ECHO) $(ELF)
+
+
diff --git a/software/oto_audio/create-this-app b/software/oto_audio/create-this-app
new file mode 100644
index 0000000000000000000000000000000000000000..c2815a24a53933574e3bd3359d273e4b7285cd6b
--- /dev/null
+++ b/software/oto_audio/create-this-app
@@ -0,0 +1,114 @@
+#!/bin/bash
+#
+# This script creates the blank_project application in this directory.
+
+
+BSP_DIR=../oto_audio_bsp
+QUARTUS_PROJECT_DIR=../../
+NIOS2_APP_GEN_ARGS="--elf-name oto_audio.elf --no-src --set OBJDUMP_INCLUDE_SOURCE 1"
+
+
+# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set.
+# This variable is required for the command line tools to execute correctly.
+if [ -z "${SOPC_KIT_NIOS2}" ]
+then
+ echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set!
+ exit 1
+fi
+
+
+# Also make sure that the APP has not been created already. Check for
+# existence of Makefile in the app directory
+if [ -f ./Makefile ]
+then
+ echo Application has already been created! Delete Makefile if you want to create a new application makefile
+ exit 1
+fi
+
+
+# We are selecting hal_default bsp because it supports this application.
+# Check to see if the hal_default has already been generated by checking for
+# existence of the public.mk file. If not, we need to run
+# create-this-bsp file to generate the bsp.
+if [ ! -f ${BSP_DIR}/public.mk ]; then
+ # Since BSP doesn't exist, create the BSP
+ # Pass any command line arguments passed to this script to the BSP.
+ pushd ${BSP_DIR} >> /dev/null
+ ./create-this-bsp "$@" || {
+ echo "create-this-bsp failed"
+ exit 1
+ }
+ popd >> /dev/null
+fi
+
+
+# Don't run make if create-this-app script is called with --no-make arg
+SKIP_MAKE=
+while [ $# -gt 0 ]
+do
+ case "$1" in
+ --no-make)
+ SKIP_MAKE=1
+ ;;
+ esac
+ shift
+done
+
+
+# Now we also need to go copy the sources for this application to the
+# local directory.
+find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || {
+ echo "failed during copying example source files"
+ exit 1
+}
+
+find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || {
+ echo "failed copying readme file"
+}
+
+if [ -d "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" ]
+then
+ cp -RL "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" . || {
+ echo "failed during copying project support files"
+ exit 1
+ }
+fi
+
+chmod -R +w . || {
+ echo "failed during changing file permissions"
+ exit 1
+}
+
+cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}"
+
+echo "create-this-app: Running \"${cmd}\""
+$cmd || {
+ echo "nios2-app-generate-makefile failed"
+ exit 1
+}
+
+if [ -z "$SKIP_MAKE" ]; then
+ cmd="make"
+
+ echo "create-this-app: Running \"$cmd\""
+ $cmd || {
+ echo "make failed"
+ exit 1
+ }
+
+ echo
+ echo "To download and run the application:"
+ echo " 1. Make sure the board is connected to the system."
+ echo " 2. Run 'nios2-configure-sof <SOF_FILE_PATH>' to configure the FPGA with the hardware design."
+ echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell."
+ echo " 4. Run 'make download-elf' from the application directory."
+ echo
+ echo "To debug the application:"
+ echo " Import the project into Nios II Software Build Tools for Eclipse."
+ echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information."
+ echo
+ echo -e ""
+fi
+
+
+exit 0
diff --git a/software/oto_audio/main.c b/software/oto_audio/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..4540f453a6fae5eeee30bdcfd1f6837e5e7b438b
--- /dev/null
+++ b/software/oto_audio/main.c
@@ -0,0 +1,51 @@
+/*
+ * main.c
+ *
+ * Created on: Nov 20, 2017
+ * Author: noman
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <unistd.h>
+#include "system.h"
+#define AUDIO_BASE ((int32_t*)AUDIO_0_BASE)
+volatile int32_t *audioLData = AUDIO_BASE;
+volatile int32_t *audioRData = AUDIO_BASE+1;
+volatile int32_t *audioReady = AUDIO_BASE+3;
+
+int main() {
+ printf("Hello world\n");
+// *audioINIT = 1;
+// *audioINIT = 0;
+ int counter=0;
+ int i;
+ while (1) {
+ //printf("%d\n" ,*audioReady);
+ for (i=1000000;i>0;--i){
+ if (*audioReady == 1){
+ if (counter < (i/6000)){
+ counter ++;
+ *audioLData = -0x10000000;
+ *audioRData = -0x00010000;
+ } else if (counter < (i/3000)){
+ counter ++;
+ *audioLData = 0x10000000;
+ *audioRData = 0x00010000;
+ }else {
+ counter =0;
+ }
+ //printf("%\n");
+ }else{
+ //printf("fucked\n");
+ }
+ }
+ //printf("begin ");
+ //usleep(1000000);
+ //printf("end\n");
+ }
+
+ return 0;
+}
+
+
diff --git a/software/oto_audio/readme.txt b/software/oto_audio/readme.txt
new file mode 100644
index 0000000000000000000000000000000000000000..57f6738b0b6536b3a08e6855442fe02dbf19d94a
--- /dev/null
+++ b/software/oto_audio/readme.txt
@@ -0,0 +1,11 @@
+This template is starting point for creating a project based on your custom C code.
+It will provide you a default project to which you can add your software files. To
+add files to a project, manually copy the file into the application directory (e.g.
+using Windows Explorer), then right click on your application project and select
+refresh.
+
+You can also add files to the project using the Nios II Software Build Tools for Eclipse import function.
+Select File -> Import.
+Expand General and select File System in the Import Window and click Next.
+Identify the appropriate source and destination directories.
+Check the files you want to add and click Finish.