diff --git a/audio.sv b/audio.sv
index 0f9824704f9f9ccae3c2bb93492f3ad35f5a03b9..e12b439cec21218d84d7851f7738943651f96c83 100644
--- a/audio.sv
+++ b/audio.sv
@@ -1,7 +1,7 @@
 module audio(
 	input logic CLK,RESET,
 
-	input logic [1:0]AVL_ADDR,
+	input logic [8:0]AVL_ADDR,
 	input logic AVL_CS,
 	input logic AVL_RD,AVL_WR,
 	input logic [31:0] AVL_WDATA,
@@ -23,13 +23,24 @@ module audio(
 	//output logic [15:0] LEDR
 );
 
+logic should_give,should_give_next;
 
+logic [7:0]counter,counter_next;
 
-logic INIT_FINISH,audio_out_allowed,write_audio_out, write_audio_out_next;
+logic audio_out_allowed,write_audio_out,write_audio_out_next;
 
-logic [31:0] data [2], data_next[2];
+logic [4:0] data,data_next;
 
 logic vol_set,vol_set_next;
+
+logic state,state_next;
+
+logic c_reset;
+
+logic MEM_WE;
+
+logic[31:0] MEM_DATAIN,MEM_DATAOUT /*synthesis keep*/;
+logic[7:0] MEM_ADDR;
 //logic audio_ready,audio_ready_next;
 
 //logic audio_out_allowed;
@@ -37,56 +48,102 @@ logic vol_set,vol_set_next;
 
 always_ff @(negedge CLK) begin
 	if(RESET) begin
-		data[0] <= 32'h0;
-		data[1] <= 32'h0;
-		write_audio_out <= 1'b0;
+		data <= 32'h0;
+		//data[1] <= 32'h0;
+		//write_audio_out <= 1'b0;
 		vol_set <= 1'b0;
+		state <=1'b1;
 	end else begin
-		data[0] <= data_next[0];
-		data[1] <= data_next[1];
-		write_audio_out <= write_audio_out_next;
+		data <= data_next;
+		//data[1] <= data_next[1];
+		//write_audio_out <= write_audio_out_next;
 		vol_set <= vol_set_next;
+		state <= state_next;
+	end
+end
+
+always_ff @(posedge CLK) begin
+	if(c_reset) begin
+		counter <= 0;
+	end else begin
+		counter <= counter_next;
 	end
 end
 
 always_comb begin
 	//audio_ready_next = audio_ready;
-	data_next[0] = data[0];
-	data_next[1] = data[1];
+	data_next = data;
+	//data_next[1] = data[1];
 	//INIT = 1'b0;
-	AVL_RDATA = 31'hCCCC;
-	write_audio_out_next = 1'b0;
-	vol_set_next = 1'b0;
+	c_reset = 0;
+	counter_next = counter;
+	AVL_RDATA = 32'hCCCC;
+	write_audio_out=0;
+	vol_set_next = 0;
+	
+	state_next = state;
+
+	MEM_WE = 1'b0;
+	MEM_ADDR = 8'hCC;
+	MEM_DATAIN = 20'b00000000000000000000;
 	
 	if (AVL_WR && AVL_CS) begin
-		if (AVL_ADDR == 2'b00) begin
-			data_next[0] = AVL_WDATA;
-			write_audio_out_next = 1'b1;
-		end
-		if (AVL_ADDR == 2'b01) begin
-			data_next[1] = AVL_WDATA;
-		end
-		// else if (AVL_ADDR == 2'b10)
-		if (AVL_ADDR == 2'b10) begin
-			vol_set_next = AVL_WDATA;
+		if (!AVL_ADDR[8]) begin
+			MEM_ADDR = AVL_ADDR;
+			MEM_DATAIN = AVL_WDATA;
+			MEM_WE = 1'b1;
+		end else begin
+			if (AVL_ADDR[1:0] == 2'b10) begin
+				data_next = AVL_WDATA;
+			end else if (AVL_ADDR[1:0] == 2'b11) begin
+				vol_set_next = 1;
+			end
 		end
 	end
 
 
 	if (AVL_RD && AVL_CS) begin
-		if (AVL_ADDR == 2'b00) begin
-			AVL_RDATA = data[0];
+		if (AVL_ADDR[8] && (AVL_ADDR[1:0] == 2'b00))begin
+				AVL_RDATA = {31'b0,state};
 		end
-		if (AVL_ADDR == 2'b11)
-			AVL_RDATA = {31'h0,audio_out_allowed};
 	end
 
 //	if (audio_out_allowed) begin
 //		audio_ready_next = 1'b1;
 //	end else
 //		audio_ready_next = 1'b0;
+	case (state)
+		0:begin
+			if (audio_out_allowed) begin
+				counter_next = counter + 1;
+				if (counter == 8'b01111111) begin
+					write_audio_out = 1;
+					state_next = 1;
+					c_reset = 1;
+				end
+			end
+		end
+		1:begin
+			if (AVL_ADDR == 9'b001111111) begin
+				//c_reset = 1;
+				state_next = 0;
+			end
+		end
+	endcase
 end
 
+byte_enabled_simple_dual_port_ram #(
+		.ADDR_WIDTH(7),
+		.WIDTH(32)
+)MEM 
+( 
+	.waddr(MEM_ADDR),
+	.raddr(counter),
+	.wdata(MEM_DATAIN), 
+	.we(MEM_WE),
+	.clk(CLK),
+	.q(MEM_DATAOUT)
+);
 
 Audio_Controller Audio_Controller (
 	// Inputs
@@ -97,8 +154,8 @@ Audio_Controller Audio_Controller (
 	.read_audio_in				(1'b0),
 	
 	.clear_audio_out_memory		(),
-	.left_channel_audio_out		({data[0][31:16],16'h0}),
-	.right_channel_audio_out	({data[0][15:0],16'h0}),
+	.left_channel_audio_out		({4'h0,MEM_DATAOUT[31:16],8'h0}),
+	.right_channel_audio_out	({4'h0,MEM_DATAOUT[15:0],8'h0}),
 	
 	//16'(signed'(IR[5:0]))
 	.write_audio_out			(write_audio_out),
@@ -119,7 +176,7 @@ Audio_Controller Audio_Controller (
 	.audio_out_allowed			(audio_out_allowed),
 
 	.AUD_XCK(),				//(AUD_MCLK),
-	.AUD_DACDAT					(AUD_DACDAT),
+	.AUD_DACDAT					(AUD_DACDAT)
 
 );
 
@@ -127,7 +184,7 @@ avconf #(.USE_MIC_INPUT(0)) avc (
 	.I2C_SCLK					(I2C_SCLK),
 	.I2C_SDAT					(I2C_SDAT),
 	.CLOCK_50					(CLK),
-	.reset						(vol_set),
-	.AUD_VOL 					(data[1][4:0])
+	.reset						(vol_set|RESET),
+	.AUD_VOL 					(data)
 );
 endmodule
diff --git a/audio_extended_buffer.sv b/audio_extended_buffer.sv
new file mode 100644
index 0000000000000000000000000000000000000000..c991d93f49194cbe5d3c7e50b435c9f8424d45cd
--- /dev/null
+++ b/audio_extended_buffer.sv
@@ -0,0 +1,33 @@
+// Quartus Prime SystemVerilog Template
+//
+// Simple Dual-Port RAM with different read/write addresses and single read/write clock
+// and with a control for writing single bytes into the memory word; byte enable
+
+module byte_enabled_simple_dual_port_ram
+	#(parameter int
+		ADDR_WIDTH = 6,
+		//BYTE_WIDTH = 8,
+		WIDTH = 8
+)
+( 
+	input [ADDR_WIDTH-1:0] waddr,
+	input [ADDR_WIDTH-1:0] raddr,
+	//input [BYTES-1:0] be,
+	input [WIDTH-1:0] wdata, 
+	input we, clk,
+	output reg [WIDTH - 1:0] q
+);
+	localparam int WORDS = 1 << ADDR_WIDTH ;
+
+	// use a multi-dimensional packed array to model individual bytes within the word
+	logic [WIDTH-1:0] ram[0:WORDS-1];
+
+	always_ff@(posedge clk)
+	begin
+		if(we) begin
+		// edit this code if using other than four bytes per word
+			ram[waddr] <= wdata;
+	end
+		q <= ram[raddr];
+	end
+endmodule : byte_enabled_simple_dual_port_ram
diff --git a/audio_hw.tcl b/audio_hw.tcl
index 4ac5fdaf140056e5175a491098085d9a35714827..daebb5df84129a70147911d62c550286c18effad 100644
--- a/audio_hw.tcl
+++ b/audio_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 17.1
-# Tue Nov 21 02:55:44 CST 2017
+# Wed Nov 29 09:57:36 CST 2017
 # DO NOT MODIFY
 
 
 # 
 # audio "audio" v1.0
-#  2017.11.21.02:55:44
+#  2017.11.29.09:57:36
 # 
 # 
 
@@ -37,7 +37,7 @@ set_module_property REPORT_HIERARCHY false
 # file sets
 # 
 add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL new_component
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL audio
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file audio.sv SYSTEM_VERILOG PATH audio.sv TOP_LEVEL_FILE
@@ -50,8 +50,10 @@ add_fileset_file Audio_Clock.v VERILOG PATH Audio_Controller/Audio_Clock.v
 add_fileset_file Audio_Controller.v VERILOG PATH Audio_Controller/Audio_Controller.v
 add_fileset_file I2C_Controller.v VERILOG PATH avconf/I2C_Controller.v
 add_fileset_file avconf.v VERILOG PATH avconf/avconf.v
+add_fileset_file audio_extended_buffer.sv SYSTEM_VERILOG PATH audio_extended_buffer.sv
 
 add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL audio
 set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file audio.sv SYSTEM_VERILOG PATH audio.sv
@@ -64,6 +66,7 @@ add_fileset_file Audio_Clock.v VERILOG PATH Audio_Controller/Audio_Clock.v
 add_fileset_file Audio_Controller.v VERILOG PATH Audio_Controller/Audio_Controller.v
 add_fileset_file I2C_Controller.v VERILOG PATH avconf/I2C_Controller.v
 add_fileset_file avconf.v VERILOG PATH avconf/avconf.v
+add_fileset_file audio_extended_buffer.sv SYSTEM_VERILOG PATH audio_extended_buffer.sv
 
 
 # 
@@ -132,7 +135,7 @@ set_interface_property Audio_Slave PORT_NAME_MAP ""
 set_interface_property Audio_Slave CMSIS_SVD_VARIABLES ""
 set_interface_property Audio_Slave SVD_ADDRESS_GROUP ""
 
-add_interface_port Audio_Slave AVL_ADDR address Input 2
+add_interface_port Audio_Slave AVL_ADDR address Input 9
 add_interface_port Audio_Slave AVL_CS chipselect Input 1
 add_interface_port Audio_Slave AVL_RD read Input 1
 add_interface_port Audio_Slave AVL_WR write Input 1
@@ -156,7 +159,6 @@ set_interface_property EXPORT_DATA PORT_NAME_MAP ""
 set_interface_property EXPORT_DATA CMSIS_SVD_VARIABLES ""
 set_interface_property EXPORT_DATA SVD_ADDRESS_GROUP ""
 
-add_interface_port EXPORT_DATA AUD_MCLK mclk Output 1
 add_interface_port EXPORT_DATA AUD_BCLK bclk Bidir 1
 add_interface_port EXPORT_DATA AUD_ADCDAT adc_data Input 1
 add_interface_port EXPORT_DATA AUD_DACDAT dac_data Output 1
@@ -164,5 +166,4 @@ add_interface_port EXPORT_DATA AUD_DACLRCK dac_clk Bidir 1
 add_interface_port EXPORT_DATA AUD_ADCLRCK adc_clk Bidir 1
 add_interface_port EXPORT_DATA I2C_SDAT i2c_sdat Bidir 1
 add_interface_port EXPORT_DATA I2C_SCLK i2c_sclk Output 1
-add_interface_port EXPORT_DATA LEDR ledr Output 16
 
diff --git a/avconf/avconf.v b/avconf/avconf.v
index d5d253669cc2af8a759f55bf12ef3679d8b30e19..5d23ba986cd3638caaeb27e760a1f3a88e9c58c2 100644
--- a/avconf/avconf.v
+++ b/avconf/avconf.v
@@ -1,10 +1,11 @@
 module avconf (	//	Host Side
 						CLOCK_50,
 						reset,
+						AUD_VOL,
 						//	I2C Side
 						I2C_SCLK,
-						I2C_SDAT,
-						AUD_VOL	);
+						I2C_SDAT
+							);
 //	Host Side
 input		CLOCK_50;
 input		reset;
@@ -26,6 +27,8 @@ reg	[15:0]	LUT_DATA;
 reg	[5:0]	LUT_INDEX;
 reg	[3:0]	mSetup_ST;
 
+wire [8:0] AUD_LINE_IN_LC,AUD_LINE_IN_RC;
+
 parameter USE_MIC_INPUT		= 1'b0;
 
 assign AUD_LINE_IN_LC	= {4'b0,AUD_VOL};
diff --git a/final_sd_interface_hw.tcl b/final_sd_interface_hw.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..295c65753e53d147ce4071bb8c4cac0e6bfe62f0
--- /dev/null
+++ b/final_sd_interface_hw.tcl
@@ -0,0 +1,147 @@
+# TCL File Generated by Component Editor 17.1
+# Fri Nov 24 20:46:05 CST 2017
+# DO NOT MODIFY
+
+
+# 
+# final_sd_interface "final_sd_interface" v1.0
+#  2017.11.24.20:46:05
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module final_sd_interface
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME final_sd_interface
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "Final-osu Custom IPs"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME final_sd_interface
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL final_sd_interface
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file final_sd_interface.sv SYSTEM_VERILOG PATH final_sd_interface.sv TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL final_sd_interface
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file final_sd_interface.sv SYSTEM_VERILOG PATH final_sd_interface.sv
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point CLK
+# 
+add_interface CLK clock end
+set_interface_property CLK clockRate 0
+set_interface_property CLK ENABLED true
+set_interface_property CLK EXPORT_OF ""
+set_interface_property CLK PORT_NAME_MAP ""
+set_interface_property CLK CMSIS_SVD_VARIABLES ""
+set_interface_property CLK SVD_ADDRESS_GROUP ""
+
+add_interface_port CLK CLK clk Input 1
+
+
+# 
+# connection point RESET
+# 
+add_interface RESET reset end
+set_interface_property RESET associatedClock CLK
+set_interface_property RESET synchronousEdges DEASSERT
+set_interface_property RESET ENABLED true
+set_interface_property RESET EXPORT_OF ""
+set_interface_property RESET PORT_NAME_MAP ""
+set_interface_property RESET CMSIS_SVD_VARIABLES ""
+set_interface_property RESET SVD_ADDRESS_GROUP ""
+
+add_interface_port RESET RESET reset Input 1
+
+
+# 
+# connection point sd_slave
+# 
+add_interface sd_slave avalon end
+set_interface_property sd_slave addressUnits WORDS
+set_interface_property sd_slave associatedClock CLK
+set_interface_property sd_slave associatedReset RESET
+set_interface_property sd_slave bitsPerSymbol 8
+set_interface_property sd_slave burstOnBurstBoundariesOnly false
+set_interface_property sd_slave burstcountUnits WORDS
+set_interface_property sd_slave explicitAddressSpan 0
+set_interface_property sd_slave holdTime 0
+set_interface_property sd_slave linewrapBursts false
+set_interface_property sd_slave maximumPendingReadTransactions 0
+set_interface_property sd_slave maximumPendingWriteTransactions 0
+set_interface_property sd_slave readLatency 0
+set_interface_property sd_slave readWaitStates 0
+set_interface_property sd_slave readWaitTime 0
+set_interface_property sd_slave setupTime 0
+set_interface_property sd_slave timingUnits Cycles
+set_interface_property sd_slave writeWaitTime 0
+set_interface_property sd_slave ENABLED true
+set_interface_property sd_slave EXPORT_OF ""
+set_interface_property sd_slave PORT_NAME_MAP ""
+set_interface_property sd_slave CMSIS_SVD_VARIABLES ""
+set_interface_property sd_slave SVD_ADDRESS_GROUP ""
+
+add_interface_port sd_slave sd_addr address Input 8
+add_interface_port sd_slave sd_cs chipselect Input 1
+add_interface_port sd_slave sd_readdata readdata Output 32
+add_interface_port sd_slave sd_writedata writedata Input 32
+add_interface_port sd_slave sd_write write Input 1
+add_interface_port sd_slave sd_read read Input 1
+set_interface_assignment sd_slave embeddedsw.configuration.isFlash 0
+set_interface_assignment sd_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment sd_slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment sd_slave embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point EXPORT
+# 
+add_interface EXPORT conduit end
+set_interface_property EXPORT associatedClock CLK
+set_interface_property EXPORT associatedReset RESET
+set_interface_property EXPORT ENABLED true
+set_interface_property EXPORT EXPORT_OF ""
+set_interface_property EXPORT PORT_NAME_MAP ""
+set_interface_property EXPORT CMSIS_SVD_VARIABLES ""
+set_interface_property EXPORT SVD_ADDRESS_GROUP ""
+
+add_interface_port EXPORT SD_DAT sd_dat Bidir 4
+add_interface_port EXPORT SD_CMD sd_cmd Bidir 1
+add_interface_port EXPORT SD_CLK sd_clk Output 1
+add_interface_port EXPORT LEDG led_green Output 7
+add_interface_port EXPORT LEDR led_red Output 16
+
diff --git a/software/audio_sd_other/main.c b/software/audio_sd_other/main.c
index db47c5b82fc1aa5962084c8cbc08a8b0d86ccd6c..b9a2261498edd12962f1e9870abcac1703a5200f 100644
--- a/software/audio_sd_other/main.c
+++ b/software/audio_sd_other/main.c
@@ -21,9 +21,9 @@
 //#include "xab.h"
 #define AUDIO_BASE ((uint32_t*)AUDIO_0_BASE)
 volatile uint32_t *audioData = AUDIO_BASE;
-volatile uint32_t *audioVol = AUDIO_BASE+1;
-volatile uint32_t *VolReset = AUDIO_BASE+2;
-volatile uint32_t *audioReady = AUDIO_BASE+3;
+volatile uint32_t *audioVol = AUDIO_BASE+0x102;
+volatile uint32_t *VolReset = AUDIO_BASE+0x103;
+volatile uint32_t *audioReady = AUDIO_BASE+0x100;
 
 int main() {
 	printf("Hello world\n");
@@ -37,7 +37,7 @@ int main() {
     FAT_HANDLE hFat;
     FAT_FILE_HANDLE fileP;
     unsigned int fileSize;
-
+    int i,j;
 
     //unsigned char audioBuffer[32768];
    
@@ -72,25 +72,28 @@ int main() {
 	
 	//pin point the beginning of file
 	fileSize = Fat_FileSize(fileP);
-	uint32_t* audioDataInDram = malloc(fileSize);
+	uint32_t* audioDataInDram = malloc(512);
 	//memset(audioDataInDram,0xCC,fileSize);
 	//start mp3 decoding
-	printf("start decoding mp3\n");
+	//printf("start decoding mp3\n");
 	//decode(audioBuffer,2048,fileP,audioDataInDram);
-	size_t start = clock();
-	Fat_FileRead(fileP,audioDataInDram,fileSize);
-	size_t end = clock();
-	printf("mp3 decoding finished!\n %d ms used!\n",end-start);
+	//size_t start = clock();
+
+	//size_t end = clock();
+	//printf("mp3 decoding finished!\n %d ms used!\n",end-start);
 	
-	unsigned int ptr=0;
-	while (ptr < (fileSize>>2)){
-		if (*audioReady){
-			*audioData = audioDataInDram[ptr];
-			++ptr;
-		}
-		if (audioDataInDram[ptr]==0xCCCCCCCC){
-			printf("%x",ptr);
-			break;
+	//unsigned int ptr=0;
+	bool flag = 0;
+	fileSize = fileSize>>9;
+	for (i=0;i<(fileSize);++i){
+		if (*audioReady && flag){
+			for(j=0;j<256;j+=2){
+				audioData[j] = (audioDataInDram[j>>1]&(0xFF00)>>16);
+				audioData[j+1] = (audioDataInDram[j>>1]&(0x00FF));
+			}
+		}else{
+			Fat_FileRead(fileP,audioDataInDram,512);
+			if (!flag) flag=1;
 		}
 	}
 	printf("Playback completed\n");
diff --git a/software/audio_sd_other/terasic_sdcard/sd_hal.c b/software/audio_sd_other/terasic_sdcard/sd_hal.c
index 657d43d0c34d279a325058281356f4f87b23730c..92071fbb011ebe7da3a9fcaee924534fad1ad5a5 100644
--- a/software/audio_sd_other/terasic_sdcard/sd_hal.c
+++ b/software/audio_sd_other/terasic_sdcard/sd_hal.c
@@ -35,10 +35,10 @@
 #include "sd_hw.h"
 #include "crc16.h"
 #include <inttypes.h>
-#include "system.h"
+//#include "system.h"
 
-//#define SD_BASE (uint32_t*(FINAL_SD_INTERFACE_0_BASE))
-#define SD_BASE ((uint32_t*)0x10001000)
+#define SD_BASE ((uint32_t*)(FINAL_SD_INTERFACE_0_BASE))
+//#define SD_BASE ((uint32_t*)0x10001000)
 volatile uint32_t* InterfaceCmd = SD_BASE + 0x81;
 volatile uint32_t* SDCmd = SD_BASE + 0x88;
 volatile uint32_t* SDResponse = SD_BASE + 0x82;