From 2ad40f28a7ec470d4d4d83f8266bbba4882c2459 Mon Sep 17 00:00:00 2001
From: Fang Lu <cc2lufang@gmail.com>
Date: Sat, 18 Nov 2017 22:23:36 -0600
Subject: [PATCH] ps2kb - avalon testing
---
.gitignore | 5 +
LICENSE | 1 +
RemoteSystemsTempFiles/.project | 12 +
input/ps2kb.sv | 183 ++---
osu_fpga_toplevel.qsf | 5 +-
osu_fpga_toplevel.sv | 67 +-
otogame.qsys | 860 +++++++++++++++++++++++
ps2kb_hw.tcl | 138 ++--
software/.gitignore | 7 +
software/osu_main/.cproject | 83 +++
software/osu_main/.project | 40 ++
software/osu_main/Makefile | 1082 +++++++++++++++++++++++++++++
software/osu_main/create-this-app | 114 +++
software/osu_main/readme.txt | 11 +
software/osu_main/src/main.c | 34 +
timing.sdc | 60 ++
16 files changed, 2530 insertions(+), 172 deletions(-)
create mode 100644 LICENSE
create mode 100644 RemoteSystemsTempFiles/.project
create mode 100644 otogame.qsys
create mode 100644 software/.gitignore
create mode 100644 software/osu_main/.cproject
create mode 100644 software/osu_main/.project
create mode 100644 software/osu_main/Makefile
create mode 100644 software/osu_main/create-this-app
create mode 100644 software/osu_main/readme.txt
create mode 100644 software/osu_main/src/main.c
create mode 100644 timing.sdc
diff --git a/.gitignore b/.gitignore
index 9a78170..d35ba51 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,3 +6,8 @@ simulation/
*.qws
*.qarlog
*.bak
+.qsys_edit/
+otogame/
+*.sopcinfo
+*.tcl~
+.metadata/
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..6c8bc24
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1 @@
+Copyright (c) 2017 by Fang Lu and Xutao J. Jiang. All rights reserved.
diff --git a/RemoteSystemsTempFiles/.project b/RemoteSystemsTempFiles/.project
new file mode 100644
index 0000000..5447a64
--- /dev/null
+++ b/RemoteSystemsTempFiles/.project
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>RemoteSystemsTempFiles</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.rse.ui.remoteSystemsTempNature</nature>
+ </natures>
+</projectDescription>
diff --git a/input/ps2kb.sv b/input/ps2kb.sv
index 79c1630..abe6b57 100644
--- a/input/ps2kb.sv
+++ b/input/ps2kb.sv
@@ -1,5 +1,5 @@
/**
- * ps2
+ * ps2kb
*
* PS2 Keyboard driver (Avalon slave)
*
@@ -31,21 +31,17 @@ module ps2kb (
input logic AVL_WRITE, // Avalon-MM Write
input logic AVL_CS, // Avalon-MM Chip Select
input logic [3:0] AVL_BYTE_EN, // Avalon-MM Byte Enable
- input logic [3:0] AVL_ADDR, // Avalon-MM Address
+ input logic [1:0] AVL_ADDR, // Avalon-MM Address
input logic [31:0] AVL_WRITEDATA, // Avalon-MM Write Data
output logic [31:0] AVL_READDATA, // Avalon-MM Read Data
// Exported Conduit
- inout wire PS2_CLK, PS2_DATA, // Exported Conduit Signal to LEDs
+ inout wire PS2_CLK, PS2_DATA
// Debug exports
- // output logic [7:0] debug_keycode,
- // output logic [2:0] debug_state, debug_counter
+ // output logic [7:0] debug_kdr1, debug_kdr2, debug_kur1, debug_kur2, debug_kc,
+ // output logic [2:0] debug_state
);
-
-// Debug
-// logic [7:0] debug_keycode_next;
-
// Static assignments
logic clock_we, data_we, clock_out, data_out, clock_in, data_in;
@@ -58,56 +54,54 @@ enum logic [2:0] {
logic [2:0] counter, counter_next;
logic clock_wait, clock_wait_next, error, error_next;
-// assign debug_state = state;
-// assign debug_counter = counter;
-
// Avalon MM functionalities
-logic[7:0] keydown[8], keydown_next[8], keyup[8], keyup_next[8];
+logic[7:0] keydown[2], keydown_next[2], keyup[2], keyup_next[2];
logic[7:0] keycode, keycode_next, keycode_out;
logic is_release, is_release_next, is_e0code, is_e0code_next;
assign keycode_out = {keycode[7] | is_e0code, keycode[6:0]};
+// assign debug_kdr1 = keydown[0];
+// assign debug_kdr2 = keydown[1];
+// assign debug_kur1 = keyup[0];
+// assign debug_kur2 = keyup[1];
+// assign debug_state = state;
+// assign debug_kc = keycode_out;
+
always_ff @(posedge CLK) begin
if(RESET) begin
- for (int i = 0; i < 8; i++) begin
- keydown[i] <= 8'h0;
- keyup[i] <= 8'h0;
-
- clock_in <= 1'b1;
- data_in <= 1'b1;
-
- state <= idle;
- keycode <= 8'h0;
- counter <= 3'b0;
- clock_wait <= 1'b0;
- error <= 0;
-
- is_release <= 0;
- is_e0code <= 0;
-
- // debug_keycode <= 8'hCC;
- end
+ keydown[0] <= 8'h00;
+ keydown[1] <= 8'h00;
+ keyup[0] <= 8'h00;
+ keyup[1] <= 8'h00;
+ clock_in <= 1'b1;
+ data_in <= 1'b1;
+
+ state <= idle;
+ keycode <= 8'h0;
+ counter <= 3'b0;
+ clock_wait <= 1'b0;
+ error <= 1'b0;
+
+ is_release <= 1'b0;
+ is_e0code <= 1'b0;
end else begin
- for (int i = 0; i < 4; i++) begin
- keydown[i] <= keydown_next[i];
- keyup[i] <= keyup_next[i];
-
- clock_in <= PS2_CLK;
- data_in <= PS2_DATA;
-
- state <= state_next;
- keycode <= keycode_next;
- counter <= counter_next;
- clock_wait <= clock_wait_next;
- error <= error_next;
-
- is_release <= is_release_next;
- is_e0code <= is_e0code_next;
-
- // debug_keycode <= debug_keycode_next;
- end
+ keydown[0] <= keydown_next[0];
+ keydown[1] <= keydown_next[1];
+ keyup[0] <= keyup_next[0];
+ keyup[1] <= keyup_next[1];
+ clock_in <= PS2_CLK;
+ data_in <= PS2_DATA;
+
+ state <= state_next;
+ keycode <= keycode_next;
+ counter <= counter_next;
+ clock_wait <= clock_wait_next;
+ error <= error_next;
+
+ is_release <= is_release_next;
+ is_e0code <= is_e0code_next;
end
end
@@ -115,30 +109,40 @@ always_comb begin
// Avalon IO
// Defaults
- for (int i = 0; i < 4; i++) begin
- keydown_next[i] = keydown[i];
- keyup_next[i] = keyup[i];
- end
+ keydown_next[0] = keydown[0];
+ keydown_next[1] = keydown[1];
+ keyup_next[0] = keyup[0];
+ keyup_next[1] = keyup[1];
AVL_READDATA = 32'hCCCC;
if (AVL_CS) begin
if (AVL_READ) begin
- if (AVL_ADDR[3] == 1'b0) // Keydown
- AVL_READDATA = {24'h0, keydown[AVL_ADDR[2:0]]};
- else
- AVL_READDATA = {24'h0, keyup[AVL_ADDR[2:0]]};
+ case (AVL_ADDR)
+ 2'b00:
+ AVL_READDATA = {24'h0, keydown[0]};
+ 2'b01:
+ AVL_READDATA = {24'h0, keydown[1]};
+ 2'b10:
+ AVL_READDATA = {24'h0, keyup[0]};
+ 2'b11:
+ AVL_READDATA = {24'h0, keyup[1]};
+ endcase
end else if (AVL_WRITE && AVL_BYTE_EN[0]) begin
- if (AVL_ADDR[3] == 1'b0) // Keydown
- keydown_next[AVL_ADDR[2:0]] = AVL_WRITEDATA[7:0];
- else
- keyup_next[AVL_ADDR[2:0]] = AVL_WRITEDATA[7:0];
+ case (AVL_ADDR)
+ 2'b00:
+ keydown_next[0] = AVL_WRITEDATA[7:0];
+ 2'b01:
+ keydown_next[1] = AVL_WRITEDATA[7:0];
+ 2'b10:
+ keyup_next[0] = AVL_WRITEDATA[7:0];
+ 2'b11:
+ keyup_next[1] = AVL_WRITEDATA[7:0];
+ endcase
end
end
// PS2 Logic
- debug_keycode_next = debug_keycode;
-
state_next = state;
counter_next = counter;
clock_wait_next = clock_wait;
@@ -154,9 +158,9 @@ always_comb begin
idle: begin
if (!clock_in && !clock_wait) begin
clock_wait_next = 1'b1;
- if (data_in != 1'b0)
- error_next = 1'b1;
- else
+ // if (data_in != 1'b0)
+ // error_next = 1'b1;
+ // else
error_next = 1'b0;
end
if (clock_in && clock_wait) begin
@@ -171,11 +175,11 @@ always_comb begin
if (!clock_in && !clock_wait) begin
clock_wait_next = 1'b1;
// keycode_next[counter] = data_in;
- keycode_next = {keycode[6:0], data_in};
+ keycode_next = {data_in, keycode[7:1]};
end
if (clock_in && clock_wait) begin
clock_wait_next = 1'b0;
- counter_next = counter+1;
+ counter_next = counter + 3'b1;
if (counter == 3'h7)
state_next = b_parity;
end
@@ -184,10 +188,10 @@ always_comb begin
b_parity: begin
if (!clock_in && !clock_wait) begin
clock_wait_next = 1'b1;
- if (data_in != keycode[0] ^ keycode[1] ^ keycode[2] ^
- keycode[3] ^ keycode[4] ^ keycode[5] ^ keycode[6] ^
- keycode[7])
- error_next = 1'b1;
+ // if (data_in != keycode[0] ^ keycode[1] ^ keycode[2] ^
+ // keycode[3] ^ keycode[4] ^ keycode[5] ^ keycode[6] ^
+ // keycode[7])
+ // error_next = 1'b1;
end
if (clock_in && clock_wait) begin
clock_wait_next = 1'b0;
@@ -198,12 +202,12 @@ always_comb begin
b_end: begin
if (!clock_in && !clock_wait) begin
clock_wait_next = 1'b1;
- if (data_in != 1'b1)
- error_next = 1'b1;
+ // if (data_in != 1'b1)
+ // error_next = 1'b1;
end
if (clock_in && clock_wait) begin
clock_wait_next = 1'b0;
- counter_next = 0;
+ counter_next = 3'b0;
if (error)
state_next = b_error;
else
@@ -213,39 +217,44 @@ always_comb begin
state_next = idle;
end
if (keycode == 8'hF0) begin
- is_release_next = 1;
+ is_release_next = 1'b1;
state_next = idle;
end
end
end
b_enqueue: begin
- // debug_keycode_next = keycode;
if (is_release) begin
- if (keyup[counter] == 8'h0) begin
- keyup_next[counter] = keycode_out;
+ if (keyup[0] == 8'h0) begin
+ keyup_next[0] = keycode_out;
+ state_next = b_fin;
+ end else if (keyup[1] == 8'h0) begin
+ keyup_next[1] = keycode_out;
state_next = b_fin;
end else
- state_next = b_enqueue;
+ state_next = b_fin;
end else begin
- if (keydown[counter] == 8'h0) begin
- keydown_next[counter] = keycode_out;
+ if (keydown[0] == 8'h0) begin
+ keydown_next[0] = keycode_out;
+ state_next = b_fin;
+ end else if (keydown[1] == 8'h0) begin
+ keydown_next[1] = keycode_out;
state_next = b_fin;
end else
- state_next = b_enqueue;
+ state_next = b_fin;
end
- counter_next = counter + 1;
end
b_error: begin
- // debug_keycode_next = 8'hDD;
// Just ignore any error
+ keydown_next[0] = 8'had;
+ keydown_next[1] = 8'hde;
state_next = b_fin;
end
b_fin: begin
- is_e0code_next = 0;
- is_release_next = 0;
+ is_e0code_next = 1'b0;
+ is_release_next = 1'b0;
state_next = idle;
end
diff --git a/osu_fpga_toplevel.qsf b/osu_fpga_toplevel.qsf
index 5378b7c..480fe63 100644
--- a/osu_fpga_toplevel.qsf
+++ b/osu_fpga_toplevel.qsf
@@ -1118,6 +1118,9 @@ set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to *
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name SYSTEMVERILOG_FILE input/ps2.sv
+set_global_assignment -name QIP_FILE otogame/synthesis/otogame.qip
+set_global_assignment -name SDC_FILE timing.sdc
+set_global_assignment -name SYSTEMVERILOG_FILE hexdriver.sv
+set_global_assignment -name SYSTEMVERILOG_FILE input/ps2kb.sv
set_global_assignment -name SYSTEMVERILOG_FILE osu_fpga_toplevel.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/osu_fpga_toplevel.sv b/osu_fpga_toplevel.sv
index e934c39..8705405 100644
--- a/osu_fpga_toplevel.sv
+++ b/osu_fpga_toplevel.sv
@@ -1,22 +1,59 @@
+/**
+* osu!fpga
+*
+* An osu!-like rhythm game on DE2-115
+*
+* See README for more information
+*
+* Copyright (c) 2017 by Fang Lu and Xutao J. Jiang. See LICENSE file
+*
+*/
module osu_fpga_toplevel (
input logic CLOCK_50,
- input logic[3:0] KEY,
- inout wire PS2_KBCLK, PS2_KBDAT,
- output logic [6:0] HEX0, HEX1, HEX4, HEX6
+ input logic [1:0] KEY,
+ output logic [7:0] LEDG,
+ output logic [17:0] LEDR,
+ output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
+ output logic [12:0] DRAM_ADDR,
+ output logic [1:0] DRAM_BA,
+ output logic DRAM_CAS_N, DRAM_CKE, DRAM_CS_N,
+ inout wire [31:0] DRAM_DQ,
+ output logic [3:0] DRAM_DQM,
+ output logic DRAM_RAS_N, DRAM_WE_N, DRAM_CLK,
+ inout wire PS2_KBCLK, PS2_KBDAT
);
+ otogame main_soc (
+ .clk_clk(CLOCK_50),
+ .reset_reset_n(KEY[0]),
+ .sdram_wire_addr(DRAM_ADDR),
+ .sdram_wire_ba(DRAM_BA),
+ .sdram_wire_cas_n(DRAM_CAS_N),
+ .sdram_wire_cke(DRAM_CKE),
+ .sdram_wire_cs_n(DRAM_CS_N),
+ .sdram_wire_dq(DRAM_DQ),
+ .sdram_wire_dqm(DRAM_DQM),
+ .sdram_wire_ras_n(DRAM_RAS_N),
+ .sdram_wire_we_n(DRAM_WE_N),
+ .sdram_clk_clk(DRAM_CLK),
+ .ps2_data_export(PS2_KBDAT),
+ .ps2_clk_export(PS2_KBCLK)
+ );
+ // logic[7:0] kdr1, kdr2, kur1, kur2, kc;
+ // logic[2:0] st;
-logic [7:0] keycode;
-logic [2:0] state, counter;
-
-ps2 kb(.CLK(CLOCK_50), .RESET(~KEY[0]), .AVL_READ(0), .AVL_WRITE(0), .AVL_CS(0),
- .AVL_BYTE_EN(0), .AVL_ADDR(0), .AVL_WRITEDATA(0), .AVL_READDATA(0),
- .PS2_CLK(PS2_KBCLK), .PS2_DATA(PS2_KBDAT),
- .debug_keycode(keycode), .debug_state(state), .debug_counter(counter));
-
-hexdriver h0(.In(keycode[3:0]), .Out(HEX0));
-hexdriver h1(.In(keycode[7:4]), .Out(HEX1));
-hexdriver h4(.In({1'b0, state}), .Out(HEX4));
-hexdriver h6(.In({1'b0, counter}), .Out(HEX6));
+ // ps2kb kb(.CLK(CLOCK_50), .RESET(~KEY[0]), .AVL_READ(0), .AVL_WRITE(0), .AVL_CS(0),
+ // .AVL_BYTE_EN(0), .AVL_ADDR(0), .AVL_WRITEDATA(0), .AVL_READDATA(0),
+ // .PS2_CLK(PS2_KBCLK), .PS2_DATA(PS2_KBDAT), .debug_state(LEDG[2:0]), .debug_kc(LEDR[7:0]),
+ // .debug_kdr1(kdr1), .debug_kdr2(kdr2), .debug_kur1(kur1), .debug_kur2(kur2));
+ // hexdriver kd1l(.In(kdr1[3:0]), .Out(HEX0));
+ // hexdriver kd1h(.In(kdr1[7:4]), .Out(HEX1));
+ // hexdriver kd2l(.In(kdr2[3:0]), .Out(HEX2));
+ // hexdriver kd2h(.In(kdr2[7:4]), .Out(HEX3));
+ // hexdriver ku1l(.In(kur1[3:0]), .Out(HEX4));
+ // hexdriver ku1h(.In(kur1[7:4]), .Out(HEX5));
+ // hexdriver ku2l(.In(kur2[3:0]), .Out(HEX6));
+ // hexdriver ku2h(.In(kur2[7:4]), .Out(HEX7));
+ // hexdriver sthex(.In({1'b0,st}), .Out(HEX7));
endmodule
diff --git a/otogame.qsys b/otogame.qsys
new file mode 100644
index 0000000..3216149
--- /dev/null
+++ b/otogame.qsys
@@ -0,0 +1,860 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element clk_50
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element flash
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ }
+ element flash.flash_data
+ {
+ datum baseAddress
+ {
+ value = "402653184";
+ type = "String";
+ }
+ }
+ element flash.flash_erase_control
+ {
+ datum baseAddress
+ {
+ value = "406847488";
+ type = "String";
+ }
+ }
+ element jtag_uart
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ }
+ element jtag_uart.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "8336";
+ type = "String";
+ }
+ }
+ element keyboard
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element keyboard.key_events
+ {
+ datum baseAddress
+ {
+ value = "20480";
+ type = "String";
+ }
+ }
+ element lab9_soc
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Cyclone IV E";
+ type = "String";
+ }
+ }
+ element ocm_null
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ }
+ element osu_sysid
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ }
+ element osu_sysid.control_slave
+ {
+ datum baseAddress
+ {
+ value = "8328";
+ type = "String";
+ }
+ }
+ element otogame
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Cyclone IV E";
+ type = "String";
+ }
+ }
+ element otogame
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Cyclone IV E";
+ type = "String";
+ }
+ }
+ element otogame
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Cyclone IV E";
+ type = "String";
+ }
+ }
+ element proc_main
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ }
+ element proc_main.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "6144";
+ type = "String";
+ }
+ }
+ element sdram
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ }
+ element sdram.s1
+ {
+ datum baseAddress
+ {
+ value = "268435456";
+ type = "String";
+ }
+ }
+ element sdram_pll
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ }
+ element sdram_pll.pll_slave
+ {
+ datum baseAddress
+ {
+ value = "48";
+ type = "String";
+ }
+ }
+ element timer
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element timer.s1
+ {
+ datum baseAddress
+ {
+ value = "64";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4CE115F29C7" />
+ <parameter name="deviceFamily" value="Cyclone IV E" />
+ <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="osu_fpga.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk" internal="clk_50.clk_in" type="clock" dir="end" />
+ <interface name="ps2_clk" internal="keyboard.ps2_clk" type="conduit" dir="end" />
+ <interface name="ps2_clock_conn" internal="keyboard.ps2_clock_conn" />
+ <interface name="ps2_conn" internal="keyboard.ps2_export" />
+ <interface name="ps2_data" internal="keyboard.ps2_data" type="conduit" dir="end" />
+ <interface name="ps2_data_conn" internal="keyboard.ps2_data_conn" />
+ <interface name="reset" internal="clk_50.clk_in_reset" type="reset" dir="end" />
+ <interface name="sdram_clk" internal="sdram_pll.c1" type="clock" dir="start" />
+ <interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
+ <module name="clk_50" kind="clock_source" version="17.0" enabled="1">
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+ name="flash"
+ kind="Altera_UP_Flash_Memory_IP_Core_Avalon_Interface"
+ version="17.0"
+ enabled="0">
+ <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ <parameter name="FLASH_MEMORY_ADDRESS_WIDTH" value="22" />
+ </module>
+ <module
+ name="jtag_uart"
+ kind="altera_avalon_jtag_uart"
+ version="17.0"
+ enabled="1">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="avalonSpec" value="2.0" />
+ <parameter name="clkFreq" value="50000000" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream" value="" />
+ <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module name="keyboard" kind="ps2kb" version="1.0" enabled="1" />
+ <module
+ name="ocm_null"
+ kind="altera_avalon_onchip_memory2"
+ version="17.0"
+ enabled="1">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">$${FILENAME}_ocm_null</parameter>
+ <parameter name="blockType" value="AUTO" />
+ <parameter name="copyInitFile" value="false" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="dataWidth2" value="32" />
+ <parameter name="deviceFamily" value="Cyclone IV E" />
+ <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="dualPort" value="false" />
+ <parameter name="ecc_enabled" value="false" />
+ <parameter name="enPRInitMode" value="false" />
+ <parameter name="enableDiffWidth" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_mem.hex" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="16" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="false" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ name="osu_sysid"
+ kind="altera_avalon_sysid_qsys"
+ version="17.0"
+ enabled="1">
+ <parameter name="id" value="1869837601" />
+ </module>
+ <module name="proc_main" kind="altera_nios2_qsys" version="16.1" enabled="1">
+ <parameter name="bht_ramBlockType" value="Automatic" />
+ <parameter name="breakOffset" value="32" />
+ <parameter name="breakSlave">proc_main.jtag_debug_module</parameter>
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="cpuID_stored" value="0" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="dataAddrWidth" value="29" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='sdram_pll.pll_slave' start='0x30' end='0x40' /><slave name='timer.s1' start='0x40' end='0x60' /><slave name='proc_main.jtag_debug_module' start='0x1800' end='0x2000' /><slave name='osu_sysid.control_slave' start='0x2088' end='0x2090' /><slave name='jtag_uart.avalon_jtag_slave' start='0x2090' end='0x2098' /><slave name='keyboard.key_events' start='0x5000' end='0x5010' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dcache_lineSize" value="32" />
+ <parameter name="dcache_numTCDM" value="0" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_size" value="2048" />
+ <parameter name="dcache_tagramBlockType" value="Automatic" />
+ <parameter name="dcache_victim_buf_impl" value="ram" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="deviceFamilyName" value="Cyclone IV E" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="exceptionSlave" value="sdram.s1" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="icache_numTCIM" value="0" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_size" value="4096" />
+ <parameter name="icache_tagramBlockType" value="Automatic" />
+ <parameter name="impl" value="Tiny" />
+ <parameter name="instAddrWidth" value="29" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='ocm_null.s1' start='0x0' end='0x10' /><slave name='sdram_pll.pll_slave' start='0x30' end='0x40' /><slave name='proc_main.jtag_debug_module' start='0x1800' end='0x2000' /><slave name='osu_sysid.control_slave' start='0x2088' end='0x2090' /><slave name='sdram.s1' start='0x10000000' end='0x18000000' /></address-map>]]></parameter>
+ <parameter name="internalIrqMaskSystemInfo" value="3" />
+ <parameter name="manuallyAssignCpuID" value="true" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="mmu_TLBMissExcSlave" value="None" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_processIDNumBits" value="8" />
+ <parameter name="mmu_ramBlockType" value="Automatic" />
+ <parameter name="mmu_tlbNumWays" value="16" />
+ <parameter name="mmu_tlbPtrSz" value="7" />
+ <parameter name="mmu_udtlbNumEntries" value="6" />
+ <parameter name="mmu_uitlbNumEntries" value="4" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mpu_minDataRegionSize" value="12" />
+ <parameter name="mpu_minInstRegionSize" value="12" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
+ <parameter name="ocimem_ramBlockType" value="Automatic" />
+ <parameter name="regfile_ramBlockType" value="Automatic" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="resetSlave" value="sdram.s1" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTrace_user" value="false" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_asic_enabled" value="false" />
+ <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_bhtPtrSz" value="8" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_breakslaveoveride" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_dc_ecc_present" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_dtcm_ecc_present" value="false" />
+ <parameter name="setting_ecc_present" value="false" />
+ <parameter name="setting_ecc_sim_test_ports" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_export_large_RAMs" value="false" />
+ <parameter name="setting_exportvectors" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_ic_ecc_present" value="true" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_itcm_ecc_present" value="false" />
+ <parameter name="setting_mmu_ecc_present" value="true" />
+ <parameter name="setting_oci_export_jtag_signals" value="false" />
+ <parameter name="setting_perfCounterWidth" value="32" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_removeRAMinit" value="false" />
+ <parameter name="setting_rf_ecc_present" value="true" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+ name="sdram"
+ kind="altera_avalon_new_sdram_controller"
+ version="17.0"
+ enabled="1">
+ <parameter name="TAC" value="5.5" />
+ <parameter name="TMRD" value="3" />
+ <parameter name="TRCD" value="20.0" />
+ <parameter name="TRFC" value="70.0" />
+ <parameter name="TRP" value="20.0" />
+ <parameter name="TWR" value="14.0" />
+ <parameter name="casLatency" value="3" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="columnWidth" value="10" />
+ <parameter name="componentName" value="$${FILENAME}_sdram" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="generateSimulationModel" value="false" />
+ <parameter name="initNOPDelay" value="0.0" />
+ <parameter name="initRefreshCommands" value="2" />
+ <parameter name="masteredTristateBridgeSlave" value="0" />
+ <parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
+ <parameter name="numberOfBanks" value="4" />
+ <parameter name="numberOfChipSelects" value="1" />
+ <parameter name="pinsSharedViaTriState" value="false" />
+ <parameter name="powerUpDelay" value="200.0" />
+ <parameter name="refreshPeriod" value="7.8125" />
+ <parameter name="registerDataIn" value="true" />
+ <parameter name="rowWidth" value="13" />
+ </module>
+ <module name="sdram_pll" kind="altpll" version="17.0" enabled="1">
+ <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+ <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+ <parameter name="BANDWIDTH" value="" />
+ <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+ <parameter name="CLK0_DIVIDE_BY" value="1" />
+ <parameter name="CLK0_DUTY_CYCLE" value="50" />
+ <parameter name="CLK0_MULTIPLY_BY" value="1" />
+ <parameter name="CLK0_PHASE_SHIFT" value="0" />
+ <parameter name="CLK1_DIVIDE_BY" value="1" />
+ <parameter name="CLK1_DUTY_CYCLE" value="50" />
+ <parameter name="CLK1_MULTIPLY_BY" value="1" />
+ <parameter name="CLK1_PHASE_SHIFT" value="-3000" />
+ <parameter name="CLK2_DIVIDE_BY" value="" />
+ <parameter name="CLK2_DUTY_CYCLE" value="" />
+ <parameter name="CLK2_MULTIPLY_BY" value="" />
+ <parameter name="CLK2_PHASE_SHIFT" value="" />
+ <parameter name="CLK3_DIVIDE_BY" value="" />
+ <parameter name="CLK3_DUTY_CYCLE" value="" />
+ <parameter name="CLK3_MULTIPLY_BY" value="" />
+ <parameter name="CLK3_PHASE_SHIFT" value="" />
+ <parameter name="CLK4_DIVIDE_BY" value="" />
+ <parameter name="CLK4_DUTY_CYCLE" value="" />
+ <parameter name="CLK4_MULTIPLY_BY" value="" />
+ <parameter name="CLK4_PHASE_SHIFT" value="" />
+ <parameter name="CLK5_DIVIDE_BY" value="" />
+ <parameter name="CLK5_DUTY_CYCLE" value="" />
+ <parameter name="CLK5_MULTIPLY_BY" value="" />
+ <parameter name="CLK5_PHASE_SHIFT" value="" />
+ <parameter name="CLK6_DIVIDE_BY" value="" />
+ <parameter name="CLK6_DUTY_CYCLE" value="" />
+ <parameter name="CLK6_MULTIPLY_BY" value="" />
+ <parameter name="CLK6_PHASE_SHIFT" value="" />
+ <parameter name="CLK7_DIVIDE_BY" value="" />
+ <parameter name="CLK7_DUTY_CYCLE" value="" />
+ <parameter name="CLK7_MULTIPLY_BY" value="" />
+ <parameter name="CLK7_PHASE_SHIFT" value="" />
+ <parameter name="CLK8_DIVIDE_BY" value="" />
+ <parameter name="CLK8_DUTY_CYCLE" value="" />
+ <parameter name="CLK8_MULTIPLY_BY" value="" />
+ <parameter name="CLK8_PHASE_SHIFT" value="" />
+ <parameter name="CLK9_DIVIDE_BY" value="" />
+ <parameter name="CLK9_DUTY_CYCLE" value="" />
+ <parameter name="CLK9_MULTIPLY_BY" value="" />
+ <parameter name="CLK9_PHASE_SHIFT" value="" />
+ <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+ <parameter name="DOWN_SPREAD" value="" />
+ <parameter name="DPA_DIVIDER" value="" />
+ <parameter name="DPA_DIVIDE_BY" value="" />
+ <parameter name="DPA_MULTIPLY_BY" value="" />
+ <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+ <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+ <parameter name="FEEDBACK_SOURCE" value="" />
+ <parameter name="GATE_LOCK_COUNTER" value="" />
+ <parameter name="GATE_LOCK_SIGNAL" value="" />
+ <parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -3000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED</parameter>
+ <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+ <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+ <parameter name="HIDDEN_IF_PORTS">IF#phasecounterselect {input 4} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}</parameter>
+ <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+ <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+ <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+ <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -3.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 ns PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1508019453416741.mif PT#ACTIVECLK_CHECK 0</parameter>
+ <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+ <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+ <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Cyclone IV E" />
+ <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="LOCK_HIGH" value="" />
+ <parameter name="LOCK_LOW" value="" />
+ <parameter name="OPERATION_MODE" value="NORMAL" />
+ <parameter name="PLL_TYPE" value="AUTO" />
+ <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+ <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+ <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+ <parameter name="PORT_ENABLE0" value="" />
+ <parameter name="PORT_ENABLE1" value="" />
+ <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+ <parameter name="PORT_FBOUT" value="" />
+ <parameter name="PORT_INCLK0" value="PORT_USED" />
+ <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+ <parameter name="PORT_LOCKED" value="PORT_UNUSED" />
+ <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+ <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCLKOUT0" value="" />
+ <parameter name="PORT_SCLKOUT1" value="" />
+ <parameter name="PORT_VCOOVERRANGE" value="" />
+ <parameter name="PORT_VCOUNDERRANGE" value="" />
+ <parameter name="PORT_clk0" value="PORT_USED" />
+ <parameter name="PORT_clk1" value="PORT_USED" />
+ <parameter name="PORT_clk2" value="PORT_UNUSED" />
+ <parameter name="PORT_clk3" value="PORT_UNUSED" />
+ <parameter name="PORT_clk4" value="PORT_UNUSED" />
+ <parameter name="PORT_clk5" value="PORT_UNUSED" />
+ <parameter name="PORT_clk6" value="" />
+ <parameter name="PORT_clk7" value="" />
+ <parameter name="PORT_clk8" value="" />
+ <parameter name="PORT_clk9" value="" />
+ <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+ <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+ <parameter name="PORT_extclkena0" value="" />
+ <parameter name="PORT_extclkena1" value="" />
+ <parameter name="PORT_extclkena2" value="" />
+ <parameter name="PORT_extclkena3" value="" />
+ <parameter name="PRIMARY_CLOCK" value="" />
+ <parameter name="QUALIFY_CONF_DONE" value="" />
+ <parameter name="SCAN_CHAIN" value="" />
+ <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+ <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+ <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+ <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+ <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+ <parameter name="SKIP_VCO" value="" />
+ <parameter name="SPREAD_FREQUENCY" value="" />
+ <parameter name="SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+ <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+ <parameter name="SWITCH_OVER_TYPE" value="" />
+ <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+ <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="VCO_DIVIDE_BY" value="" />
+ <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+ <parameter name="VCO_MULTIPLY_BY" value="" />
+ <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+ <parameter name="WIDTH_CLOCK" value="5" />
+ <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module name="timer" kind="altera_avalon_timer" version="17.0" enabled="1">
+ <parameter name="alwaysRun" value="false" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="false" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="true" />
+ <parameter name="systemFrequency" value="50000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="watchdogPulse" value="2" />
+ </module>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="jtag_uart.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2090" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="osu_sysid.control_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2088" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="flash.flash_data">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x18000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="flash.flash_erase_control">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x18400000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="proc_main.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1800" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="keyboard.key_events">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x5000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="sdram_pll.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0030" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="ocm_null.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="sdram.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x10000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.data_master"
+ end="timer.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0040" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.instruction_master"
+ end="osu_sysid.control_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2088" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.instruction_master"
+ end="flash.flash_data">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x18000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.instruction_master"
+ end="proc_main.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1800" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.instruction_master"
+ end="sdram_pll.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0030" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.instruction_master"
+ end="ocm_null.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="17.0"
+ start="proc_main.instruction_master"
+ end="sdram.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x10000000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="17.0" start="sdram_pll.c0" end="sdram.clk" />
+ <connection kind="clock" version="17.0" start="clk_50.clk" end="osu_sysid.clk" />
+ <connection kind="clock" version="17.0" start="clk_50.clk" end="proc_main.clk" />
+ <connection kind="clock" version="17.0" start="clk_50.clk" end="jtag_uart.clk" />
+ <connection kind="clock" version="17.0" start="clk_50.clk" end="timer.clk" />
+ <connection kind="clock" version="17.0" start="clk_50.clk" end="flash.clk" />
+ <connection kind="clock" version="17.0" start="clk_50.clk" end="ocm_null.clk1" />
+ <connection kind="clock" version="17.0" start="clk_50.clk" end="keyboard.clock" />
+ <connection
+ kind="clock"
+ version="17.0"
+ start="clk_50.clk"
+ end="sdram_pll.inclk_interface" />
+ <connection
+ kind="interrupt"
+ version="17.0"
+ start="proc_main.d_irq"
+ end="jtag_uart.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="17.0"
+ start="proc_main.d_irq"
+ end="timer.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+ kind="reset"
+ version="17.0"
+ start="clk_50.clk_reset"
+ end="sdram_pll.inclk_interface_reset" />
+ <connection
+ kind="reset"
+ version="17.0"
+ start="clk_50.clk_reset"
+ end="sdram.reset" />
+ <connection
+ kind="reset"
+ version="17.0"
+ start="clk_50.clk_reset"
+ end="osu_sysid.reset" />
+ <connection
+ kind="reset"
+ version="17.0"
+ start="clk_50.clk_reset"
+ end="jtag_uart.reset" />
+ <connection
+ kind="reset"
+ version="17.0"
+ start="clk_50.clk_reset"
+ end="timer.reset" />
+ <connection
+ kind="reset"
+ version="17.0"
+ start="clk_50.clk_reset"
+ end="flash.reset" />
+ <connection
+ kind="reset"
+ version="17.0"
+ start="clk_50.clk_reset"
+ end="keyboard.reset" />
+ <connection
+ kind="reset"
+ version="17.0"
+ start="clk_50.clk_reset"
+ end="ocm_null.reset1" />
+ <connection
+ kind="reset"
+ version="17.0"
+ start="clk_50.clk_reset"
+ end="proc_main.reset_n" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/ps2kb_hw.tcl b/ps2kb_hw.tcl
index c577390..1cfbad3 100644
--- a/ps2kb_hw.tcl
+++ b/ps2kb_hw.tcl
@@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 17.0
-# Sat Nov 18 17:39:55 CST 2017
+# Sat Nov 18 22:12:04 CST 2017
# DO NOT MODIFY
#
# ps2kb "PS/2 Keyboard Interface" v1.0
-# 2017.11.18.17:39:54
+# 2017.11.18.22:12:04
# This module produces key events for PS/2 keyboard
#
@@ -89,71 +89,71 @@ add_interface_port reset RESET reset Input 1
#
-# connection point ps2_data_conn
-#
-add_interface ps2_data_conn conduit end
-set_interface_property ps2_data_conn associatedClock clock
-set_interface_property ps2_data_conn associatedReset ""
-set_interface_property ps2_data_conn ENABLED true
-set_interface_property ps2_data_conn EXPORT_OF ""
-set_interface_property ps2_data_conn PORT_NAME_MAP ""
-set_interface_property ps2_data_conn CMSIS_SVD_VARIABLES ""
-set_interface_property ps2_data_conn SVD_ADDRESS_GROUP ""
-
-add_interface_port ps2_data_conn PS2_DATA export Bidir 1
-
-
-#
-# connection point ps2_clock_conn
-#
-add_interface ps2_clock_conn conduit end
-set_interface_property ps2_clock_conn associatedClock clock
-set_interface_property ps2_clock_conn associatedReset ""
-set_interface_property ps2_clock_conn ENABLED true
-set_interface_property ps2_clock_conn EXPORT_OF ""
-set_interface_property ps2_clock_conn PORT_NAME_MAP ""
-set_interface_property ps2_clock_conn CMSIS_SVD_VARIABLES ""
-set_interface_property ps2_clock_conn SVD_ADDRESS_GROUP ""
-
-add_interface_port ps2_clock_conn PS2_CLK export Bidir 1
-
-
-#
-# connection point keystroke_events
-#
-add_interface keystroke_events avalon end
-set_interface_property keystroke_events addressUnits WORDS
-set_interface_property keystroke_events associatedClock clock
-set_interface_property keystroke_events associatedReset reset
-set_interface_property keystroke_events bitsPerSymbol 8
-set_interface_property keystroke_events burstOnBurstBoundariesOnly false
-set_interface_property keystroke_events burstcountUnits WORDS
-set_interface_property keystroke_events explicitAddressSpan 0
-set_interface_property keystroke_events holdTime 0
-set_interface_property keystroke_events linewrapBursts false
-set_interface_property keystroke_events maximumPendingReadTransactions 0
-set_interface_property keystroke_events maximumPendingWriteTransactions 0
-set_interface_property keystroke_events readLatency 0
-set_interface_property keystroke_events readWaitStates 0
-set_interface_property keystroke_events readWaitTime 0
-set_interface_property keystroke_events setupTime 0
-set_interface_property keystroke_events timingUnits Cycles
-set_interface_property keystroke_events writeWaitTime 0
-set_interface_property keystroke_events ENABLED true
-set_interface_property keystroke_events EXPORT_OF ""
-set_interface_property keystroke_events PORT_NAME_MAP ""
-set_interface_property keystroke_events CMSIS_SVD_VARIABLES ""
-set_interface_property keystroke_events SVD_ADDRESS_GROUP ""
-
-add_interface_port keystroke_events AVL_READ read Input 1
-add_interface_port keystroke_events AVL_WRITE write Input 1
-add_interface_port keystroke_events AVL_WRITEDATA writedata Input 32
-add_interface_port keystroke_events AVL_READDATA readdata Output 32
-add_interface_port keystroke_events AVL_ADDR address Input 4
-add_interface_port keystroke_events AVL_BYTE_EN byteenable Input 4
-add_interface_port keystroke_events AVL_CS chipselect Input 1
-set_interface_assignment keystroke_events embeddedsw.configuration.isFlash 0
-set_interface_assignment keystroke_events embeddedsw.configuration.isMemoryDevice 0
-set_interface_assignment keystroke_events embeddedsw.configuration.isNonVolatileStorage 0
-set_interface_assignment keystroke_events embeddedsw.configuration.isPrintableDevice 0
+# connection point ps2_clk
+#
+add_interface ps2_clk conduit end
+set_interface_property ps2_clk associatedClock clock
+set_interface_property ps2_clk associatedReset ""
+set_interface_property ps2_clk ENABLED true
+set_interface_property ps2_clk EXPORT_OF ""
+set_interface_property ps2_clk PORT_NAME_MAP ""
+set_interface_property ps2_clk CMSIS_SVD_VARIABLES ""
+set_interface_property ps2_clk SVD_ADDRESS_GROUP ""
+
+add_interface_port ps2_clk PS2_CLK export Bidir 1
+
+
+#
+# connection point ps2_data
+#
+add_interface ps2_data conduit end
+set_interface_property ps2_data associatedClock clock
+set_interface_property ps2_data associatedReset ""
+set_interface_property ps2_data ENABLED true
+set_interface_property ps2_data EXPORT_OF ""
+set_interface_property ps2_data PORT_NAME_MAP ""
+set_interface_property ps2_data CMSIS_SVD_VARIABLES ""
+set_interface_property ps2_data SVD_ADDRESS_GROUP ""
+
+add_interface_port ps2_data PS2_DATA export Bidir 1
+
+
+#
+# connection point key_events
+#
+add_interface key_events avalon end
+set_interface_property key_events addressUnits WORDS
+set_interface_property key_events associatedClock clock
+set_interface_property key_events associatedReset reset
+set_interface_property key_events bitsPerSymbol 8
+set_interface_property key_events burstOnBurstBoundariesOnly false
+set_interface_property key_events burstcountUnits WORDS
+set_interface_property key_events explicitAddressSpan 0
+set_interface_property key_events holdTime 0
+set_interface_property key_events linewrapBursts false
+set_interface_property key_events maximumPendingReadTransactions 0
+set_interface_property key_events maximumPendingWriteTransactions 0
+set_interface_property key_events readLatency 0
+set_interface_property key_events readWaitStates 0
+set_interface_property key_events readWaitTime 0
+set_interface_property key_events setupTime 0
+set_interface_property key_events timingUnits Cycles
+set_interface_property key_events writeWaitTime 0
+set_interface_property key_events ENABLED true
+set_interface_property key_events EXPORT_OF ""
+set_interface_property key_events PORT_NAME_MAP ""
+set_interface_property key_events CMSIS_SVD_VARIABLES ""
+set_interface_property key_events SVD_ADDRESS_GROUP ""
+
+add_interface_port key_events AVL_READ read Input 1
+add_interface_port key_events AVL_WRITE write Input 1
+add_interface_port key_events AVL_WRITEDATA writedata Input 32
+add_interface_port key_events AVL_READDATA readdata Output 32
+add_interface_port key_events AVL_ADDR address Input 2
+add_interface_port key_events AVL_BYTE_EN byteenable Input 4
+add_interface_port key_events AVL_CS chipselect Input 1
+set_interface_assignment key_events embeddedsw.configuration.isFlash 0
+set_interface_assignment key_events embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment key_events embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment key_events embeddedsw.configuration.isPrintableDevice 0
diff --git a/software/.gitignore b/software/.gitignore
new file mode 100644
index 0000000..a450043
--- /dev/null
+++ b/software/.gitignore
@@ -0,0 +1,7 @@
+.settings/
+*_bsp/
+*.d
+*.o
+*.objdump
+*.elf
+*.map
diff --git a/software/osu_main/.cproject b/software/osu_main/.cproject
new file mode 100644
index 0000000..745f9bc
--- /dev/null
+++ b/software/osu_main/.cproject
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065">
+ <storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065" moduleId="org.eclipse.cdt.core.settings"/>
+ </buildSystem>
+ <cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065">
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065." name="/" resourcePath="">
+ <toolChain id="altera.nios2.mingw.gcc4.1695715586" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
+ <targetPlatform id="altera.nios2.mingw.gcc4.2130013499" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
+ <builder buildPath="${workspace_loc://osu_main}" id="altera.tool.gnu.builder.mingw.1243813729" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
+ <tool id="altera.tool.gnu.c.compiler.mingw.1512907719" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1040711810" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ </tool>
+ <tool id="altera.tool.gnu.cpp.compiler.mingw.1573963372" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.232317194" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+ </tool>
+ <tool id="altera.tool.gnu.archiver.mingw.1684988338" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
+ <tool id="altera.tool.gnu.c.linker.mingw.1482049235" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
+ <tool id="altera.tool.gnu.assembler.mingw.1402728829" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.422854114" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="osu_main.null.1539812112" name="osu_main"/>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065.;altera.tool.gnu.cpp.compiler.mingw.1573963372;cdt.managedbuild.tool.gnu.cpp.compiler.input.232317194">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1934673065.;altera.tool.gnu.c.compiler.mingw.1512907719;cdt.managedbuild.tool.gnu.c.compiler.input.1040711810">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
+ <buildTargets>
+ <target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>mem_init_install</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>false</useDefaultCommand>
+ <runAllBuilders>false</runAllBuilders>
+ </target>
+ <target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>mem_init_generate</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>false</useDefaultCommand>
+ <runAllBuilders>false</runAllBuilders>
+ </target>
+ <target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>help</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>false</useDefaultCommand>
+ <runAllBuilders>false</runAllBuilders>
+ </target>
+ </buildTargets>
+ </storageModule>
+</cproject>
diff --git a/software/osu_main/.project b/software/osu_main/.project
new file mode 100644
index 0000000..cb1a8b2
--- /dev/null
+++ b/software/osu_main/.project
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>osu_main</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>com.altera.sbtgui.project.makefileBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>com.altera.sbtgui.project.makefileBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>com.altera.sbtgui.project.SBTGUINature</nature>
+ <nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
+ <nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
+ </natures>
+</projectDescription>
diff --git a/software/osu_main/Makefile b/software/osu_main/Makefile
new file mode 100644
index 0000000..472b018
--- /dev/null
+++ b/software/osu_main/Makefile
@@ -0,0 +1,1082 @@
+#------------------------------------------------------------------------------
+# VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS
+#------------------------------------------------------------------------------
+
+# List of include directories for -I compiler option (-I added when used).
+# Includes the BSP.
+ALT_INCLUDE_DIRS :=
+
+# List of library directories for -L linker option (-L added when used).
+# Includes the BSP.
+ALT_LIBRARY_DIRS :=
+
+# List of library names for -l linker option (-l added when used).
+# Includes the BSP.
+ALT_LIBRARY_NAMES :=
+
+# List of library names for -msys-lib linker option (-msys-lib added when used).
+# These are libraries that might be located in the BSP and depend on the BSP
+# library, or vice versa
+ALT_BSP_DEP_LIBRARY_NAMES :=
+
+# List of dependencies for the linker. This is usually the full pathname
+# of each library (*.a) file.
+# Includes the BSP.
+ALT_LDDEPS :=
+
+# List of root library directories that support running make to build them.
+# Includes the BSP and any ALT libraries.
+MAKEABLE_LIBRARY_ROOT_DIRS :=
+
+# Generic flags passed to the compiler for different types of input files.
+ALT_CFLAGS :=
+ALT_CXXFLAGS :=
+ALT_CPPFLAGS :=
+ALT_ASFLAGS :=
+ALT_LDFLAGS :=
+
+
+#------------------------------------------------------------------------------
+# The adjust-path macro
+#
+# If COMSPEC/ComSpec is defined, Make is launched from Windows through
+# Cygwin. The adjust-path macro converts absolute windows paths into
+# unix style paths (Example: c:/dir -> /c/dir). This will ensture
+# paths are readable by GNU Make.
+#
+# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no
+# adjustment is necessary
+#
+#------------------------------------------------------------------------------
+
+ifndef COMSPEC
+ifdef ComSpec
+COMSPEC = $(ComSpec)
+endif # ComSpec
+endif # COMSPEC
+
+ifdef COMSPEC # if Windows OS
+
+ifeq ($(MAKE_VERSION),3.81)
+#
+# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows
+#
+# Example Usage:
+# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb
+# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb
+# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb
+#
+
+#
+# adjust-path
+# - converts back slash characters into forward slashes
+# - if input arg ($1) is an empty string then return the empty string
+# - if input arg ($1) does not contain the string ":/", then return input arg
+# - using sed, convert mixed path [c:/...] into mingw path [/c/...]
+define adjust-path
+$(strip \
+$(if $1,\
+$(if $(findstring :/,$(subst \,/,$1)),\
+$(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\
+$(subst \,/,$1))))
+endef
+
+#
+# adjust-path-mixed
+# - converts back slash characters into forward slashes
+# - if input arg ($1) is an empty string then return the empty string
+# - if input arg ($1) does not begin with a forward slash '/' char, then
+# return input arg
+# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...]
+# into a mixed path [c:/...]
+define adjust-path-mixed
+$(strip \
+$(if $1,\
+$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\
+$(subst \,/,$1),\
+$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,'))))
+endef
+
+else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79)
+#
+# adjust-path for Cygwin Gnu Make
+# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb
+# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb
+#
+adjust-path = $(if $1,$(shell cygpath -u "$1"),)
+adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),)
+endif
+
+else # !COMSPEC
+
+adjust-path = $1
+adjust-path-mixed = $1
+
+endif # COMSPEC
+
+
+#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
+# GENERATED SETTINGS START v
+#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
+
+#START GENERATED
+ACTIVE_BUILD_CONFIG := default
+BUILD_CONFIGS := default
+
+# The following TYPE comment allows tools to identify the 'type' of target this
+# makefile is associated with.
+# TYPE: APP_MAKEFILE
+
+# This following VERSION comment indicates the version of the tool used to
+# generate this makefile. A makefile variable is provided for VERSION as well.
+# ACDS_VERSION: 17.0
+ACDS_VERSION := 17.0
+
+# This following BUILD_NUMBER comment indicates the build number of the tool
+# used to generate this makefile.
+# BUILD_NUMBER: 595
+
+# Define path to the application ELF.
+# It may be used by the makefile fragments so is defined before including them.
+#
+ELF := osu_main.elf
+
+# Paths to C, C++, and assembly source files.
+C_SRCS := src/main.c
+CXX_SRCS :=
+ASM_SRCS :=
+
+
+# Path to root of object file tree.
+OBJ_ROOT_DIR := obj
+
+# Options to control objdump.
+CREATE_OBJDUMP := 1
+OBJDUMP_INCLUDE_SOURCE := 1
+OBJDUMP_FULL_CONTENTS := 0
+
+# Options to enable/disable optional files.
+CREATE_ELF_DERIVED_FILES := 0
+CREATE_LINKER_MAP := 1
+
+# Common arguments for ALT_CFLAGSs
+APP_CFLAGS_DEFINED_SYMBOLS :=
+APP_CFLAGS_UNDEFINED_SYMBOLS :=
+APP_CFLAGS_OPTIMIZATION := -O0
+APP_CFLAGS_DEBUG_LEVEL := -g
+APP_CFLAGS_WARNINGS := -Wall
+APP_CFLAGS_USER_FLAGS :=
+
+APP_ASFLAGS_USER :=
+APP_LDFLAGS_USER :=
+
+# Linker options that have default values assigned later if not
+# assigned here.
+LINKER_SCRIPT :=
+CRT0 :=
+SYS_LIB :=
+
+# Define path to the root of the BSP.
+BSP_ROOT_DIR := ../otofpga_main_bsp/
+
+# List of application specific include directories, library directories and library names
+APP_INCLUDE_DIRS :=
+APP_LIBRARY_DIRS :=
+APP_LIBRARY_NAMES :=
+
+# Pre- and post- processor settings.
+BUILD_PRE_PROCESS :=
+BUILD_POST_PROCESS :=
+
+QUARTUS_PROJECT_DIR := ../../
+
+
+#END GENERATED
+
+#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+# GENERATED SETTINGS END ^
+#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+
+#------------------------------------------------------------------------------
+# DEFAULT TARGET
+#------------------------------------------------------------------------------
+
+# Define the variable used to echo output if not already defined.
+ifeq ($(ECHO),)
+ECHO := echo
+endif
+
+# Put "all" rule before included makefile fragments because they may
+# define rules and we don't want one of those to become the default rule.
+.PHONY : all
+
+all:
+ @$(ECHO) [$(APP_NAME) build complete]
+
+all : build_pre_process libs app build_post_process
+
+
+#------------------------------------------------------------------------------
+# VARIABLES DEPENDENT ON GENERATED CONTENT
+#------------------------------------------------------------------------------
+
+# Define object file directory per build configuration
+CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG)
+
+ifeq ($(BSP_ROOT_DIR),)
+$(error Edit Makefile and provide a value for BSP_ROOT_DIR)
+endif
+
+ifeq ($(wildcard $(BSP_ROOT_DIR)),)
+$(error BSP directory does not exist: $(BSP_ROOT_DIR))
+endif
+
+# Define absolute path to the root of the BSP.
+ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd))
+
+# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before
+# including each makefile fragment so that it knows the path to itself.
+BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk
+ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR)
+include $(BSP_INCLUDE_FILE)
+# C2H will need this to touch the BSP public.mk and avoid the sopc file
+# out-of-date error during a BSP make
+ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk
+
+
+ifneq ($(WARNING.SMALL_STACK_SIZE),)
+# This WARNING is here to protect you from unknowingly using a very small stack
+# If the warning is set, increase your stack size or enable the BSP small stack
+# setting to eliminate the warning
+$(warning WARNING: $(WARNING.SMALL_STACK_SIZE))
+endif
+
+# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF
+# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_.
+ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),)
+ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF)
+endif
+
+# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to
+# download_elf target
+ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),)
+GMON_OUT_FILENAME := gmon.out
+WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME)
+endif
+
+# Name of ELF application.
+APP_NAME := $(basename $(ELF))
+
+# Set to defaults if variables not already defined in settings.
+ifeq ($(LINKER_SCRIPT),)
+LINKER_SCRIPT := $(BSP_LINKER_SCRIPT)
+endif
+ifeq ($(CRT0),)
+CRT0 := $(BSP_CRT0)
+endif
+ifeq ($(SYS_LIB),)
+SYS_LIB := $(BSP_SYS_LIB)
+endif
+
+OBJDUMP_NAME := $(APP_NAME).objdump
+OBJDUMP_FLAGS := --disassemble --syms --all-header
+ifeq ($(OBJDUMP_INCLUDE_SOURCE),1)
+OBJDUMP_FLAGS += --source
+endif
+ifeq ($(OBJDUMP_FULL_CONTENTS),1)
+OBJDUMP_FLAGS += --full-contents
+endif
+
+# Create list of linker dependencies (*.a files).
+APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS)
+
+# Take lists and add required prefixes.
+APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
+ASM_INC_PREFIX := -Wa,-I
+APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
+APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS))
+APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS))
+
+ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
+
+#
+# Avoid Nios II GCC 3.X options.
+#
+
+# Detect if small newlib C library is requested.
+# If yes, remove the -msmallc option because it is
+# now handled by other means.
+ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),)
+ ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS))
+ ALT_C_LIBRARY := smallc
+else
+ ALT_C_LIBRARY := c
+endif
+
+# Put each BSP dependent library in a group to avoid circular dependencies.
+APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -lm -l$(l) -Wl,--end-group)
+
+else # !AVOID_NIOS2_GCC3_OPTIONS
+
+#
+# Use Nios II GCC 3.X options.
+#
+ALT_BSP_DEP_LIBRARY_NAMES += $(ALT_BSP_DEP_LIBRARY_NAMES) m
+APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES))
+
+endif # !AVOID_NIOS2_GCC3_OPTIONS
+
+# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker.
+APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \
+ $(APP_CFLAGS_UNDEFINED_SYMBOLS) \
+ $(APP_CFLAGS_OPTIMIZATION) \
+ $(APP_CFLAGS_DEBUG_LEVEL) \
+ $(APP_CFLAGS_WARNINGS) \
+ $(APP_CFLAGS_USER_FLAGS) \
+ $(ALT_CFLAGS) \
+ $(CFLAGS)
+
+# Arguments only for the C++ compiler.
+APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS)
+
+# Arguments only for the C preprocessor.
+# Prefix each include directory with -I.
+APP_CPPFLAGS := $(APP_INC_DIRS) \
+ $(ALT_CPPFLAGS) \
+ $(CPPFLAGS)
+
+# Arguments only for the assembler.
+APP_ASFLAGS := $(APP_ASM_INC_DIRS) \
+ $(ALT_ASFLAGS) \
+ $(APP_ASFLAGS_USER) \
+ $(ASFLAGS)
+
+# Arguments only for the linker.
+APP_LDFLAGS := $(APP_LDFLAGS_USER)
+
+ifneq ($(LINKER_SCRIPT),)
+APP_LDFLAGS += -T'$(LINKER_SCRIPT)'
+endif
+
+ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
+
+# Avoid Nios II GCC 3.x options.
+ifneq ($(CRT0),)
+APP_LDFLAGS += $(CRT0)
+endif
+
+# The equivalent of the -msys-lib option is provided
+# by the GROUP() command in the linker script.
+# Note this means the SYS_LIB variable is now ignored.
+
+else # !AVOID_NIOS2_GCC3_OPTIONS
+
+# Use Nios II GCC 3.x options.
+ifneq ($(CRT0),)
+APP_LDFLAGS += -msys-crt0='$(CRT0)'
+endif
+ifneq ($(SYS_LIB),)
+APP_LDFLAGS += -msys-lib=$(SYS_LIB)
+endif
+
+endif # !AVOID_NIOS2_GCC3_OPTIONS
+
+APP_LDFLAGS += \
+ $(APP_LIB_DIRS) \
+ $(ALT_LDFLAGS) \
+ $(LDFLAGS)
+
+LINKER_MAP_NAME := $(APP_NAME).map
+ifeq ($(CREATE_LINKER_MAP), 1)
+APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME)
+endif
+
+# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the
+# mem_init_install target of the mem_init.mk (located in the associated BSP)
+# to know how to copy memory initialization files (e.g. .dat, .hex) into
+# directories required for Quartus compilation or RTL simulation.
+
+# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory
+# initialization files into your Quartus project directory. This is required
+# to provide the initial memory contents of FPGA memories that can be
+# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used
+# for VHDL simulation of on-chip memories.
+
+# Defining SOPC_NAME causes the mem_init_install target to copy memory
+# initialization files into your RTL simulation directory. This is required
+# to provide the initial memory contents of all memories that can be
+# initialized by RTL simulation. This variable should be set to the same name
+# as your SOPC Builder system name. For example, if you have a system called
+# "foo.sopc", this variable should be set to "foo".
+
+# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME.
+ifeq ($(SOPC_NAME),)
+ifneq ($(QUARTUS_PROJECT_DIR),)
+SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo)))
+endif
+endif
+
+# Defining JDI_FILE is required to specify the JTAG Debug Information File
+# path. This file is generated by Quartus, and is needed along with the
+# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU
+# systems. For multi-CPU systems, the processor instance ID is used to select
+# from multiple CPU's during ELF download.
+
+# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during
+# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then
+# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be
+# multiple .sopcinfo files in a Quartus project.
+ifeq ($(JDI_FILE),)
+ifneq ($(QUARTUS_PROJECT_DIR),)
+JDI_FILE := $(firstword $(wildcard $(QUARTUS_PROJECT_DIR)/output_files/*.jdi) $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi))
+endif
+endif
+
+# Path to root runtime directory used for hdl simulation
+RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime
+
+
+
+#------------------------------------------------------------------------------
+# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT
+#------------------------------------------------------------------------------
+# mem_init.mk is a generated makefile fragment. This file defines all targets
+# used to generate HDL initialization simulation files and pre-initialized
+# onchip memory files.
+MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk
+include $(MEM_INIT_FILE)
+
+# Create list of object files to be built using the list of source files.
+# The source file hierarchy is preserved in the object tree.
+# The supported file extensions are:
+#
+# .c - for C files
+# .cxx .cc .cpp - for C++ files
+# .S .s - for assembler files
+#
+# Handle source files specified by --src-dir & --src-rdir differently, to
+# save some processing time in calling the adjust-path macro.
+
+OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS)))
+OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS)))
+OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS)))
+OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS)))
+OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS)))
+OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS)))
+
+OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \
+ $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS))
+
+SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS)))
+SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS)))
+SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS)))
+
+SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \
+ $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \
+ $(SDIR_OBJ_LIST_SS))
+
+# Relative-pathed objects that being with "../" are handled differently.
+#
+# Regular objects are created as
+# $(CONFIG_OBJ_DIR)/<path>/<filename>.o
+# where the path structure is maintained under the obj directory. This
+# applies for both absolute and relative paths; in the absolute path
+# case this means the entire source path will be recreated under the obj
+# directory. This is done to allow two source files with the same name
+# to be included as part of the project.
+#
+# Note: On Cygwin, the path recreated under the obj directory will be
+# the cygpath -u output path.
+#
+# Relative-path objects that begin with "../" cause problems under this
+# scheme, as $(CONFIG_OBJ_DIR)/../<rest of path>/ can potentially put the object
+# files anywhere in the system, creating clutter and polluting the source tree.
+# As such, their paths are flattened - the object file created will be
+# $(CONFIG_OBJ_DIR)/<filename>.o. Due to this, two files specified with
+# "../" in the beginning cannot have the same name in the project. VPATH
+# will be set for these sources to allow make to relocate the source file
+# via %.o rules.
+#
+# The following lines separate the object list into the flatten and regular
+# lists, and then handles them as appropriate.
+
+FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST))
+FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST)))
+
+REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST))
+REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST))
+
+FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST))
+FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST)))
+
+REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST))
+
+VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST)))
+
+APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_C) \
+ $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s)))
+
+APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_CPP) \
+ $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s)))
+
+APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_CXX) \
+ $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s)))
+
+APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_CC) \
+ $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s)))
+
+APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_S) \
+ $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s)))
+
+APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\
+ $(REGULAR_SDIR_OBJ_LIST_SS) \
+ $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s)))
+
+APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \
+ $(APP_OBJS_S) $(APP_OBJS_SS) \
+ $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS)
+
+# Add any extra user-provided object files.
+APP_OBJS += $(OBJS)
+
+# Create list of dependancy files for each object file.
+APP_DEPS := $(APP_OBJS:.o=.d)
+
+# Patch the Elf file with system specific information
+
+# Patch the Elf with the name of the sopc system
+ifneq ($(SOPC_NAME),)
+ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME)
+endif
+
+# Patch the Elf with the absolute path to the Quartus Project Directory
+ifneq ($(QUARTUS_PROJECT_DIR),)
+ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd))
+ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)"
+endif
+
+# Patch the Elf and download args with the JDI_FILE if specified
+ifneq ($(wildcard $(JDI_FILE)),)
+ELF_PATCH_FLAG += --jdi $(JDI_FILE)
+DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE)
+endif
+
+# Patch the Elf with the SOPCINFO_FILE if specified
+ifneq ($(wildcard $(SOPCINFO_FILE)),)
+ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE)
+endif
+
+# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use.
+# This is not needed if you only have one cable.
+ifneq ($(DOWNLOAD_CABLE),)
+DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)'
+endif
+
+
+#------------------------------------------------------------------------------
+# BUILD PRE/POST PROCESS
+#------------------------------------------------------------------------------
+build_pre_process :
+ $(BUILD_PRE_PROCESS)
+
+build_post_process :
+ $(BUILD_POST_PROCESS)
+
+.PHONY: build_pre_process build_post_process
+
+
+#------------------------------------------------------------------------------
+# TOOLS
+#------------------------------------------------------------------------------
+
+#
+# Set tool default variables if not already defined.
+# If these are defined, they would typically be defined in an
+# included makefile fragment.
+#
+ifeq ($(DEFAULT_CROSS_COMPILE),)
+DEFAULT_CROSS_COMPILE := nios2-elf-
+endif
+
+ifeq ($(DEFAULT_STACKREPORT),)
+DEFAULT_STACKREPORT := nios2-stackreport
+endif
+
+ifeq ($(DEFAULT_DOWNLOAD),)
+DEFAULT_DOWNLOAD := nios2-download
+endif
+
+ifeq ($(DEFAULT_FLASHPROG),)
+DEFAULT_FLASHPROG := nios2-flash-programmer
+endif
+
+ifeq ($(DEFAULT_ELFPATCH),)
+DEFAULT_ELFPATCH := nios2-elf-insert
+endif
+
+ifeq ($(DEFAULT_RM),)
+DEFAULT_RM := rm -f
+endif
+
+ifeq ($(DEFAULT_CP),)
+DEFAULT_CP := cp -f
+endif
+
+ifeq ($(DEFAULT_MKDIR),)
+DEFAULT_MKDIR := mkdir -p
+endif
+
+#
+# Set tool variables to defaults if not already defined.
+# If these are defined, they would typically be defined by a
+# setting in the generated portion of this makefile.
+#
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE)
+endif
+
+ifeq ($(origin CC),default)
+CC := $(CROSS_COMPILE)gcc -xc
+endif
+
+ifeq ($(origin CXX),default)
+CXX := $(CROSS_COMPILE)gcc -xc++
+endif
+
+ifeq ($(origin AS),default)
+AS := $(CROSS_COMPILE)gcc
+endif
+
+ifeq ($(origin AR),default)
+AR := $(CROSS_COMPILE)ar
+endif
+
+ifeq ($(origin LD),default)
+LD := $(CROSS_COMPILE)g++
+endif
+
+ifeq ($(origin RM),default)
+RM := $(DEFAULT_RM)
+endif
+
+ifeq ($(NM),)
+NM := $(CROSS_COMPILE)nm
+endif
+
+ifeq ($(CP),)
+CP := $(DEFAULT_CP)
+endif
+
+ifeq ($(OBJDUMP),)
+OBJDUMP := $(CROSS_COMPILE)objdump
+endif
+
+ifeq ($(OBJCOPY),)
+OBJCOPY := $(CROSS_COMPILE)objcopy
+endif
+
+ifeq ($(STACKREPORT),)
+STACKREPORT := $(DEFAULT_STACKREPORT) --prefix $(CROSS_COMPILE)
+else
+DISABLE_STACKREPORT := 1
+endif
+
+ifeq ($(DOWNLOAD),)
+DOWNLOAD := $(DEFAULT_DOWNLOAD)
+endif
+
+ifeq ($(FLASHPROG),)
+FLASHPROG := $(DEFAULT_FLASHPROG)
+endif
+
+ifeq ($(ELFPATCH),)
+ELFPATCH := $(DEFAULT_ELFPATCH)
+endif
+
+ifeq ($(MKDIR),)
+MKDIR := $(DEFAULT_MKDIR)
+endif
+
+#------------------------------------------------------------------------------
+# PATTERN RULES TO BUILD OBJECTS
+#------------------------------------------------------------------------------
+
+define compile.c
+@$(ECHO) Info: Compiling $< to $@
+@$(MKDIR) $(@D)
+$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+$(CC_POST_PROCESS)
+endef
+
+define compile.cpp
+@$(ECHO) Info: Compiling $< to $@
+@$(MKDIR) $(@D)
+$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+$(CXX_POST_PROCESS)
+endef
+
+# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS
+ifeq ($(AS),$(patsubst %as,%,$(AS)))
+COMMA := ,
+APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS))))
+endif
+
+define compile.s
+@$(ECHO) Info: Assembling $< to $@
+@$(MKDIR) $(@D)
+$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $<
+$(AS_POST_PROCESS)
+endef
+
+ifeq ($(MAKE_VERSION),3.81)
+.SECONDEXPANSION:
+
+$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c)
+ $(compile.c)
+
+$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp)
+ $(compile.cpp)
+
+$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc)
+ $(compile.cpp)
+
+$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx)
+ $(compile.cpp)
+
+$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S)
+ $(compile.s)
+
+$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s)
+ $(compile.s)
+
+endif # MAKE_VERSION != 3.81
+
+$(CONFIG_OBJ_DIR)/%.o: %.c
+ $(compile.c)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cpp
+ $(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cc
+ $(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cxx
+ $(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.S
+ $(compile.s)
+
+$(CONFIG_OBJ_DIR)/%.o: %.s
+ $(compile.s)
+
+
+#------------------------------------------------------------------------------
+# PATTERN RULES TO INTERMEDIATE FILES
+#------------------------------------------------------------------------------
+
+$(CONFIG_OBJ_DIR)/%.s: %.c
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cpp
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cc
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cxx
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.c
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cpp
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cc
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cxx
+ @$(ECHO) Info: Compiling $< to $@
+ @$(MKDIR) $(@D)
+ $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+
+#------------------------------------------------------------------------------
+# TARGET RULES
+#------------------------------------------------------------------------------
+
+.PHONY : help
+help :
+ @$(ECHO) "Summary of Makefile targets"
+ @$(ECHO) " Build targets:"
+ @$(ECHO) " all (default) - Application and all libraries (including BSP)"
+ @$(ECHO) " bsp - Just the BSP"
+ @$(ECHO) " libs - All libraries (including BSP)"
+ @$(ECHO) " flash - All flash files"
+ @$(ECHO) " mem_init_generate - All memory initialization files"
+ @$(ECHO)
+ @$(ECHO) " Clean targets:"
+ @$(ECHO) " clean_all - Application and all libraries (including BSP)"
+ @$(ECHO) " clean - Just the application"
+ @$(ECHO) " clean_bsp - Just the BSP"
+ @$(ECHO) " clean_libs - All libraries (including BSP)"
+ @$(ECHO)
+ @$(ECHO) " Run targets:"
+ @$(ECHO) " download-elf - Download and run your elf executable"
+ @$(ECHO) " program-flash - Program flash contents to the board"
+
+# Handy rule to skip making libraries and just make application.
+.PHONY : app
+app : $(ELF)
+
+ifeq ($(CREATE_OBJDUMP), 1)
+app : $(OBJDUMP_NAME)
+endif
+
+ifeq ($(CREATE_ELF_DERIVED_FILES),1)
+app : elf_derived_files
+endif
+
+.PHONY: elf_derived_files
+elf_derived_files: default_mem_init
+
+# Handy rule for making just the BSP.
+.PHONY : bsp
+bsp :
+ @$(ECHO) Info: Building $(BSP_ROOT_DIR)
+ @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR)
+
+
+# Make sure all makeable libraries (including the BSP) are up-to-date.
+LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
+
+.PHONY : libs
+libs : $(LIB_TARGETS)
+
+ifneq ($(strip $(LIB_TARGETS)),)
+$(LIB_TARGETS): %-recurs-make-lib:
+ @$(ECHO) Info: Building $*
+ $(MAKE) --no-print-directory -C $*
+endif
+
+ifneq ($(strip $(APP_LDDEPS)),)
+$(APP_LDDEPS): libs
+ @true
+endif
+
+# Rules to force your project to rebuild or relink
+# .force_relink file will cause any application that depends on this project to relink
+# .force_rebuild file will cause this project to rebuild object files
+# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files
+
+FORCE_RELINK_DEP := .force_relink
+FORCE_REBUILD_DEP := .force_rebuild
+FORCE_REBUILD_ALL_DEP := .force_rebuild_all
+FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP)
+
+$(FORCE_REBUILD_DEP_LIST):
+
+$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS)))
+
+$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS)))
+
+
+# Clean just the application.
+.PHONY : clean
+ifeq ($(CREATE_ELF_DERIVED_FILES),1)
+clean : clean_elf_derived_files
+endif
+
+clean :
+ @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST)
+ @$(ECHO) [$(APP_NAME) clean complete]
+
+# Clean just the BSP.
+.PHONY : clean_bsp
+clean_bsp :
+ @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR)
+ @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean
+
+# Clean all makeable libraries including the BSP.
+LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
+
+.PHONY : clean_libs
+clean_libs : $(LIB_CLEAN_TARGETS)
+
+ifneq ($(strip $(LIB_CLEAN_TARGETS)),)
+$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib:
+ @$(ECHO) Info: Cleaning $*
+ $(MAKE) --no-print-directory -C $* clean
+endif
+
+.PHONY: clean_elf_derived_files
+clean_elf_derived_files: mem_init_clean
+
+# Clean application and all makeable libraries including the BSP.
+.PHONY : clean_all
+clean_all : clean mem_init_clean clean_libs
+
+# Include the dependency files unless the make goal is performing a clean
+# of the application.
+ifneq ($(firstword $(MAKECMDGOALS)),clean)
+ifneq ($(firstword $(MAKECMDGOALS)),clean_all)
+-include $(APP_DEPS)
+endif
+endif
+
+.PHONY : download-elf
+download-elf : $(ELF)
+ @if [ "$(DOWNLOAD)" = "none" ]; \
+ then \
+ $(ECHO) Downloading $(ELF) not supported; \
+ else \
+ $(ECHO) Info: Downloading $(ELF); \
+ $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \
+ fi
+
+# Delete the target of a rule if it has changed and its commands exit
+# with a nonzero exit status.
+.DELETE_ON_ERROR:
+
+# Rules for flash programming commands
+PROGRAM_FLASH_SUFFIX := -program
+PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES))
+
+.PHONY : program-flash
+program-flash : $(PROGRAM_FLASH_TARGET)
+
+.PHONY : $(PROGRAM_FLASH_TARGET)
+$(PROGRAM_FLASH_TARGET) : flash
+ @if [ "$(FLASHPROG)" = "none" ]; \
+ then \
+ $(ECHO) Programming flash not supported; \
+ else \
+ $(ECHO) Info: Programming $(basename $@).flash; \
+ if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \
+ then \
+ $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
+ $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
+ else \
+ $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
+ $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
+ fi \
+ fi
+
+
+# Rules for simulating with an HDL Simulator [QSYS only]
+ifeq ($(QSYS),1)
+#Create a top level modelsim script load_sim.tcl to source generate msim_setup.tcl and copy mem initialization files
+CREATE_TOP_SIM_SCRIPT := alt-create-top-sim-script
+
+ifeq ($(VSIM),)
+VSIM_EXE := "$(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim"
+ifeq ($(ENABLE_VSIM_GUI),1)
+VSIM := $(VSIM_EXE) -gui
+else
+VSIM := $(VSIM_EXE) -c
+endif # ENABLE_VSIM_GUI == 1
+endif # VSIM not set
+
+ifeq ($(SPD),)
+ifneq ($(ABS_QUARTUS_PROJECT_DIR),)
+ifneq ($(SOPC_NAME),)
+SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb.spd
+LEGACY_SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd
+SPD = $(if $(wildcard $(SPD_LOCATION)),$(SPD_LOCATION),$(LEGACY_SPD_LOCATION))
+endif # SOPC_NAME set
+endif # ABS_QUARTUS_PROJECT_DIR set
+endif # SPD == empty string
+
+
+ifeq ($(LOAD_SIM_SCRIPT),)
+SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim
+LOAD_SIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/load_sim.tcl
+endif # LOAD_SIM_SCRIPT == empty string
+
+ifeq ($(MAKE_VERSION),3.81)
+ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE))
+else
+ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE)
+endif
+
+$(LOAD_SIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE)
+ifeq ($(SPD),)
+ $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set)
+endif
+ @$(MKDIR) $(SIM_SCRIPT_DIR)
+ $(CREATE_TOP_SIM_SCRIPT) --spd=$(SPD) --mem-init-spd=$(abspath $(MEM_INIT_DESCRIPTOR_FILE)) --output-directory=$(SIM_SCRIPT_DIR)
+
+VSIM_COMMAND = \
+ cd $(dir $(LOAD_SIM_SCRIPT)) && \
+ $(VSIM) -do "do $(notdir $(LOAD_SIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)"
+
+.PHONY: sim
+sim: $(LOAD_SIM_SCRIPT) mem_init_generate
+ifeq ($(LOAD_SIM_SCRIPT),)
+ $(error LOAD_SIM_SCRIPT not set)
+endif
+ $(VSIM_COMMAND)
+
+endif # QSYS == 1
+
+
+
+
+#------------------------------------------------------------------------------
+# ELF TARGET RULE
+#------------------------------------------------------------------------------
+# Rule for constructing the executable elf file.
+$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS)
+ @$(ECHO) Info: Linking $@
+ $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS)
+ifneq ($(DISABLE_ELFPATCH),1)
+ $(ELFPATCH) $@ $(ELF_PATCH_FLAG)
+endif
+ifneq ($(DISABLE_STACKREPORT),1)
+ @bash -c "$(STACKREPORT) $@"
+endif
+
+$(OBJDUMP_NAME) : $(ELF)
+ @$(ECHO) Info: Creating $@
+ $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@
+
+# Rule for printing the name of the elf file
+.PHONY: print-elf-name
+print-elf-name:
+ @$(ECHO) $(ELF)
+
+
diff --git a/software/osu_main/create-this-app b/software/osu_main/create-this-app
new file mode 100644
index 0000000..4e1d5e0
--- /dev/null
+++ b/software/osu_main/create-this-app
@@ -0,0 +1,114 @@
+#!/bin/bash
+#
+# This script creates the blank_project application in this directory.
+
+
+BSP_DIR=../otofpga_main_bsp
+QUARTUS_PROJECT_DIR=../../
+NIOS2_APP_GEN_ARGS="--elf-name osu_main.elf --no-src --set OBJDUMP_INCLUDE_SOURCE 1"
+
+
+# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set.
+# This variable is required for the command line tools to execute correctly.
+if [ -z "${SOPC_KIT_NIOS2}" ]
+then
+ echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set!
+ exit 1
+fi
+
+
+# Also make sure that the APP has not been created already. Check for
+# existence of Makefile in the app directory
+if [ -f ./Makefile ]
+then
+ echo Application has already been created! Delete Makefile if you want to create a new application makefile
+ exit 1
+fi
+
+
+# We are selecting hal_default bsp because it supports this application.
+# Check to see if the hal_default has already been generated by checking for
+# existence of the public.mk file. If not, we need to run
+# create-this-bsp file to generate the bsp.
+if [ ! -f ${BSP_DIR}/public.mk ]; then
+ # Since BSP doesn't exist, create the BSP
+ # Pass any command line arguments passed to this script to the BSP.
+ pushd ${BSP_DIR} >> /dev/null
+ ./create-this-bsp "$@" || {
+ echo "create-this-bsp failed"
+ exit 1
+ }
+ popd >> /dev/null
+fi
+
+
+# Don't run make if create-this-app script is called with --no-make arg
+SKIP_MAKE=
+while [ $# -gt 0 ]
+do
+ case "$1" in
+ --no-make)
+ SKIP_MAKE=1
+ ;;
+ esac
+ shift
+done
+
+
+# Now we also need to go copy the sources for this application to the
+# local directory.
+find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || {
+ echo "failed during copying example source files"
+ exit 1
+}
+
+find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || {
+ echo "failed copying readme file"
+}
+
+if [ -d "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" ]
+then
+ cp -RL "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" . || {
+ echo "failed during copying project support files"
+ exit 1
+ }
+fi
+
+chmod -R +w . || {
+ echo "failed during changing file permissions"
+ exit 1
+}
+
+cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}"
+
+echo "create-this-app: Running \"${cmd}\""
+$cmd || {
+ echo "nios2-app-generate-makefile failed"
+ exit 1
+}
+
+if [ -z "$SKIP_MAKE" ]; then
+ cmd="make"
+
+ echo "create-this-app: Running \"$cmd\""
+ $cmd || {
+ echo "make failed"
+ exit 1
+ }
+
+ echo
+ echo "To download and run the application:"
+ echo " 1. Make sure the board is connected to the system."
+ echo " 2. Run 'nios2-configure-sof <SOF_FILE_PATH>' to configure the FPGA with the hardware design."
+ echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell."
+ echo " 4. Run 'make download-elf' from the application directory."
+ echo
+ echo "To debug the application:"
+ echo " Import the project into Nios II Software Build Tools for Eclipse."
+ echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information."
+ echo
+ echo -e ""
+fi
+
+
+exit 0
diff --git a/software/osu_main/readme.txt b/software/osu_main/readme.txt
new file mode 100644
index 0000000..57f6738
--- /dev/null
+++ b/software/osu_main/readme.txt
@@ -0,0 +1,11 @@
+This template is starting point for creating a project based on your custom C code.
+It will provide you a default project to which you can add your software files. To
+add files to a project, manually copy the file into the application directory (e.g.
+using Windows Explorer), then right click on your application project and select
+refresh.
+
+You can also add files to the project using the Nios II Software Build Tools for Eclipse import function.
+Select File -> Import.
+Expand General and select File System in the Import Window and click Next.
+Identify the appropriate source and destination directories.
+Check the files you want to add and click Finish.
diff --git a/software/osu_main/src/main.c b/software/osu_main/src/main.c
new file mode 100644
index 0000000..2ee8849
--- /dev/null
+++ b/software/osu_main/src/main.c
@@ -0,0 +1,34 @@
+/*
+ * main.c
+ *
+ * Created on: Nov 18, 2017
+ * Author: ilufang
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+
+#include "system.h"
+
+volatile uint32_t *kbdr = (uint32_t *) KEYBOARD_BASE;
+
+int main() {
+ printf("Hello world\n");
+
+ while (1) {
+ for (int i=0; i<2; i++) {
+ if (kbdr[i]) {
+ printf("Key pressed (%d): %02x\n", i, (int)kbdr[i]);
+ kbdr[i] = 0;
+ }
+ }
+ for (int i=2; i<4; i++) {
+ if (kbdr[i]) {
+ printf("Key released (%d): %02x\n", i, (int)kbdr[i]);
+ kbdr[i] = 0;
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/timing.sdc b/timing.sdc
new file mode 100644
index 0000000..fc32e3a
--- /dev/null
+++ b/timing.sdc
@@ -0,0 +1,60 @@
+# Create Clocks
+create_clock -name {Clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
+# create_generated_clock -name {lab9_qsystem|altpll_0|sd1|pll|clk[0]} -source [get_pins {lab9_qsystem|altpll_0|sd1|pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -phase -54.000 -master_clock {CLOCK_50} [get_pins {lab9_qsystem|altpll_0|sd1|pll|clk[0]}]
+
+# Constrain the input I/O path
+set_input_delay -clock {Clk} -max 3 [all_inputs]
+set_input_delay -clock {Clk} -min 2 [all_inputs]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {KEY[0]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {KEY[0]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {KEY[1]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {KEY[1]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {KEY[2]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {KEY[2]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {KEY[3]}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {KEY[3]}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {PS2_KBCLK}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {PS2_KBCLK}]
+set_input_delay -add_delay -max -clock [get_clocks {Clk}] 3.000 [get_ports {PS2_KBDAT}]
+set_input_delay -add_delay -min -clock [get_clocks {Clk}] 2.000 [get_ports {PS2_KBDAT}]
+
+# Constrain the output I/O path
+set_output_delay -clock {Clk} 2 [all_outputs]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {LEDG[7]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX0[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX1[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX1[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX1[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX1[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX1[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX1[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX1[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX2[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX2[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX2[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX2[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX2[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX2[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX2[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[0]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[1]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[2]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[3]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[4]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[5]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {HEX3[6]}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {PS2_KBCLK}]
+set_output_delay -add_delay -clock [get_clocks {Clk}] 2.000 [get_ports {PS2_KBDAT}]
--
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