diff --git a/FSR_circuit_sims/FSR_voltage_divider.asc b/FSR_circuit_sims/FSR_voltage_divider.asc new file mode 100644 index 0000000000000000000000000000000000000000..ac8aca80eb3b75aeef5af494b70cb0066536c35e --- /dev/null +++ b/FSR_circuit_sims/FSR_voltage_divider.asc @@ -0,0 +1,41 @@ +Version 4 +SHEET 1 880 680 +WIRE 64 112 64 96 +WIRE 240 208 240 144 +WIRE 64 224 64 192 +WIRE 208 224 64 224 +WIRE 352 240 272 240 +WIRE 448 240 352 240 +WIRE 64 256 64 224 +WIRE 208 256 176 256 +WIRE 176 288 176 256 +WIRE 352 288 352 240 +WIRE 352 288 176 288 +WIRE 240 304 240 272 +FLAG 64 336 0 +FLAG 64 16 0 +FLAG 240 384 0 +FLAG 448 240 Vout +FLAG 240 144 0 +SYMBOL res 48 96 R0 +SYMATTR InstName FSR +SYMATTR Value {R} +SYMBOL res 48 240 R0 +SYMATTR InstName RM +SYMATTR Value 8k +SYMBOL voltage 64 112 R180 +WINDOW 0 24 96 Left 2 +WINDOW 3 24 16 Left 2 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 5 +SYMBOL OpAmps\\LT1014 240 304 M180 +SYMATTR InstName U1 +SYMBOL voltage 240 288 R0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value 5 +TEXT 30 412 Left 2 !.op +TEXT 32 560 Left 2 !.step param R 1 1000k 4k